DOCSLIB.ORG

Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY AX11001/AX11005 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Features Product Brief compatible Fast Ethernet MAC and PHY with MCU dedicated 12KB SRAM for Ethernet packet 8-bit pipelined RISC, single cycle per buffering. Support full-duplex and half-duplex instruction with maximum operating operations frequency of 100Mhz (100 MIPS) Support twisted pair crossover detection and 100% software compatible with standard auto-correction (Auto-MDIX) 8051/80390 Support wakeup via Link-up, Magic packet, 2 GPIO ports of 8 bits each Wakeup frame, external input pin, or UART 2 external interrupt sources with 2 priority levels TCP/IP Support power management unit, Build in TCP/IP accelerator in hardware to programmable watchdog timer, and 3 16-bit improve network transfer throughput. Support timer/counters IP/TCP/UDP/ICMP/IGMP checksum and Debug port for connecting to In-Circuit ARP in hardware Emulation (ICE) adaptor Support TCP, UDP, ICMP, IGMP, IPv4, 5 channels of Programmable Counter Array DHCP, BOOTP, ARP, and HTTP in software (PCA) Communication Interface On-chip Program and Data Memory 3 UART interface (with 1 supporting Embed 128K (AX11001) or 512KB 921.6Kbps and Modem control) (AX11005) Flash memory without bank 1 I2C interface (master and slave mode) select, and 16KB SRAM for program code SPI/Micro wire interface (3 masters or 1 slave mirroring mode) Support initial Flash memory programming 1 1-Wire controller interface (master mode) via UART or ICE adaptor, the so-called In 10/100 Ethernet PHY interface System Programming (ISP) Support network boot over Ethernet using BOOTP Support run-time firmware or driver update and TFTP through Ethernet or UART, the so-called In Integrate on-chip 3.3V to 1.8V voltage regulator and Application Programming (IAP) require single power supply of 3.3V only Embed 32KB SRAM for data memory Integrate on-chip oscillator and PLL. Require only Buffer Management one 25Mhz crystal to operate Embed DMA engine and memory arbiter. Integrate on-chip power-on reset circuit Support 3 DMA channels for high 80-pin LQFP or 80-pin TFBGA RoHS package performance data movement needed for Operating temperature: 0 to 70°C or -40 to 85°C network protocol stack processing *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. On-chip 10/100M Fast Ethernet MAC and PHY *All other trademarks and registered trademark are the property of their Integrate IEEE 802.3 10BASE-T/100BASE-TX respective holders. Product Description The AX11001/AX11005, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip (SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol suite on-chip and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from system CPU in an embedded system. ASIX Electronics Corporation 6 Released Date: 5/31/2007 4F, No.8, Hsin Ann Rd., ASIX Proprietary and Confidential TEL: +886-3-579-9500 Hsinchu Science Park, FAX: +886-3-579-9558 Hsinchu 30078, Taiwan http://www.asix.com.tw/ AX11001/AX11005 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Block Diagram Applications The AX11001/AX11005, with on-chip high performance RISC CPU, built-in TCP/IP protocol suite, and rich communication peripherals supported, provides a very low cost yet very high performance SoC solution to enable easy and simple LAN or Internet access capability to almost every application needs in the Internet era. The AX11001/AX11005 is targeted for home appliances, factory/building automation, industrial equipments, security systems, remote control/monitoring/management, and streaming media applications such as network camera/remote surveillance, hardware TCP/IP offload engine, audio over Internet, automatic meter reading, vending system/POS, environment monitoring or network sensor, networked UPS, serial to Ethernet adaptor and Ethernet to ZigBee bridge, etc. ASIX Electronics Corporation 6 Released Date: 5/31/2007 4F, No.8, Hsin Ann Rd., ASIX Proprietary and Confidential TEL: +886-3-579-9500 Hsinchu Science Park, FAX: +886-3-579-9558 Hsinchu 30078, Taiwan http://www.asix.com.tw/.
Load more

Recommended publications
  • AX11001/AX11005 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY
    AX11001/AX11005 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Features Product Brief compatible Fast Ethernet MAC and PHY with MCU dedicated 12KB SRAM for Ethernet packet 8-bit pipelined RISC, single cycle per buffering. Support full-duplex and half-duplex instruction with maximum operating operations frequency of 100Mhz (100 MIPS) Support twisted pair crossover detection and 100% software compatible with standard auto-correction (Auto-MDIX) 8051/80390 Support wakeup via Link-up, Magic packet, 2 GPIO ports of 8 bits each Wakeup frame, external input pin, or UART 2 external interrupt sources with 2 priority levels TCP/IP Support power management unit, Build in TCP/IP accelerator in hardware to programmable watchdog timer, and 3 16-bit improve network transfer throughput. Support timer/counters IP/TCP/UDP/ICMP/IGMP checksum and Debug port for connecting to In-Circuit ARP in hardware Emulation (ICE) adaptor Support TCP, UDP, ICMP, IGMP, IPv4, 5 channels of Programmable Counter Array DHCP, BOOTP, ARP, and HTTP in software (PCA) Communication Interface On-chip Program and Data Memory 3 UART interface (with 1 supporting Embed 128K (AX11001) or 512KB 921.6Kbps and Modem control) (AX11005) Flash memory without bank 1 I2C interface (master and slave mode) select, and 16KB SRAM for program code SPI/Micro wire interface (3 masters or 1 slave mirroring mode) Support initial Flash memory programming 1 1-Wire controller interface (master mode) via UART or ICE adaptor, the so-called In 10/100 Ethernet PHY interface System Programming (ISP) Support network boot over Ethernet using BOOTP Support run-time firmware or driver update and TFTP through Ethernet or UART, the so-called In Integrate on-chip 3.3V to 1.8V voltage regulator and Application Programming (IAP) require single power supply of 3.3V only Embed 32KB SRAM for data memory Integrate on-chip oscillator and PLL.
    [Show full text]
  • AX88179/AX88178A Macos Driver Installation Guide
    AX88179/AX88178A macOS Driver Installation Guide AX88179/AX88178A macOS Driver Installation Guide Revision 2.20 th Nov. 30 , 2017 1 Copyright (C) 2012-2017 Reserved by ASIX Electronics Corporation, All Rights Reserved. AX88179/AX88178A macOS Driver Installation Guide Revision History Revision Date Description 1.00 2012/09/10 Initial release. 2.00 2014/02/25 1. Modified to support macOS 10.9 driver installer. 2. Modified some descriptions in Section 1. 3. Replaced Section 4-1 “Driver Installation Failure on macOS 10.8 Issue” with new Section 4-1 “How to identify the Vendor ID and Product ID of your USB dongle?”. 4. Added Section 4-2 and Section 4-3. 5. Removed “Appendix A. AX88179/AX88178A Script Files” section. 2.01 2014/06/10 1. Modified some descriptions in Section 2. 2.10 2016/11/08 1. Modified some descriptions and pictures to meet the latest macOS driver installer. 2. Added Section 4-3. 2.20 2017/11/30 1. Updated all descriptions to use unique “macOS” wording. 2. Added more information in Section 4-3. 3. Added Section 4-5 “How to configure AX88179/178A macOS driver VLAN setting?”. 2 Copyright (C) 2012-2017 Reserved by ASIX Electronics Corporation, All Rights Reserved. AX88179/AX88178A macOS Driver Installation Guide Contents 1. Introduction ............................................................................. 4 2. Driver Installation Procedures ............................................... 4 3. Driver Uninstallation Procedures ........................................ 11 4. Troubleshooting .................................................................... 12 4-1. How to identify the Vendor ID and Product ID of your USB dongle? .. 12 4-2. How to identify the installed macOS driver revision? ......................... 13 4-3. How to isolate driver failure issues after upgrading macOS system? 14 4-4.
    [Show full text]
  • Single Chip Microcontroller
    AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Features Product Brief Supports Suspend mode and Remote Wakeup via Single chip USB 2.0 to 10/100M Fast Ethernet controller – Link-up, Magic packet, MS wakeup frame and external AX88772A pin Single chip USB 2.0 to MII, single chip MII to Ethernet and Optional PHY power down during Suspend mode USB Bridging controller in Dual-PHY mode (US Patent Pending) – AX88172A Versatile External Media Interface Optional MII interface in MAC mode allows AX88172A USB Device Interface to work with external 100BASE-FX Ethernet PHY or Integrates on-chip USB 2.0 transceiver and SIE HomePNA PHY compliant to USB Spec 1.1 and 2.0 Optional Reverse-MII or Reverse-RMII interface in Supports USB Full and High Speed modes with PHY mode allows AX88172A to work with external Bus-Power or Self-Power capability HomePlug PHY or glueless MAC-to-MAC connections Supports 4 or 6 programmable endpoints on USB Optional Reverse-MII interface in Dual-PHY mode (US interface Patent Pending) allows AX88172A to act as an Ethernet High performance packet transfer rate over USB bus PHY or USB 2.0 PHY for external MAC device that using proprietary burst transfer mechanism (US Patent needs Ethernet and USB in system application Approval) Supports USB to Ethernet bridging or vice versa in Supports 256/512 bytes (93c56/93c66) of serial EEPROM hardware (for storing USB Descriptors) Supports automatic loading of Ethernet ID, USB Fast Ethernet Controller Descriptors and Adapter Configuration from EEPROM after Integrates
    [Show full text]
  • Success-Story Asix-1334040905.Pdf (484.10KB)
    Success Story ASIX & Digital Core Design The key to new network solutions We are glad to integrate DCD IP core into ASIX’s Network SoC solutions. We rely on DCD IP core to make our Network SoC products become more reliable and cost - effective. Mr. Allan Chou FAE Director, ASIX Electronics Corp. THE COMPANIES CHALENGES Digital Core Design - one of the major Intellectual HAD2 firmware modification for shorter Property (IP) Core and System-on-Chip (SoC) pro- programming time from DoCDTM level viders. Since 1999 DCD is working on its reputabil- ity, constantly proving to be an expert in IP Cores DoCDTM debug software adjustment architecture improvements. The high market posi- & alteration for FLASH support tion has been confirmed by over 300 licenses sold to over 200 international clients, including: INTEL, Keil uVision 3/4 dedicated driver for direct SIEMENS, TOYOTA, OSRAM, and ASIX - of course. AX110x & AX220x devices support from IDE uVision environment ASIX Electronics Corporation - the leading fabless semiconductor supplier, mainly focused on networking, communication and connectivity applications. The company has been established in 1995 and since then, it specializes in network IP SOLUTIONS connectivity solutions and provides Ethernet- centric silicon products, such as non-PCI Ethernet DP80390 controllers, USB-to-LAN controllers and network TM system-on-a-chip SoC products for embedded DoCD networking applications. Copyright© 1999-2012 DCD – Digital Core Design. All Rights Reserved All trademarks mentioned in this document are trademarks
    [Show full text]
  • かんたんセットアップガイド 右の画面が表示されたら、［完了］をクリックします。 Lan-Gtj/U2b ：ギガビットイーサネット対応 Usb 2.0 Lan アダプタ 4 Lan-Tx/U2b ：イーサネット対応 Usb 2.0 Lan アダプタ
    かんたんセットアップガイド 右の画面が表示されたら、［完了］をクリックします。 LAN-GTJ/U2B ：ギガビットイーサネット対応 USB 2.0 LAN アダプタ 4 LAN-TX/U2B ：イーサネット対応 USB 2.0 LAN アダプタ このたびは、ロジテックの LAN アダプタをお買い上げいただき誠にありがとうございます。この「かんたんセットアッ プガイド」は、本製品をパソコンに導入するにあたっての手順を説明しています。導入作業を始める前に、必ず製 品に添付の「取り扱い上のご注意」をお読みになったうえで、正しく導入作業をおこなってください。 本製品は、人命にかかわる設備や機器、および高い信頼性や安全性を必要とする設備や機器（医療関係、航空宇宙関係、輸送関係、 原子力関係）への組み込み等は考慮されていません。これらの機器での使用により、人身事故や財産損害が発生しても、弊社ではいか 本製品をパソコンに取り付けます。 なる責任も負いかねます。 5 ① USB コネクタをパソコンの USB ポートに接続します。 ② 本製品に LAN ケーブルを接続します。 STEP 1 パッケージの内容を確認しましょう パッケージを開封し、梱包物がすべてそろっていることを確認してください。 ツメ 万が一不足しているものがありましたら、お買い求めの販売店にご連絡ください。 溝 LANケーブルの向きは、LAN ポートの溝のある側にLANケ ーブルのツメがくるようにし □製品本体（どちらか一方、お買い求めの製品が梱包されています） □ セットアップガイド（このシート） ます。 ※保証書が含まれています。 LAN-GTJ/U2B（ブラック） LAN-TX/U2B（ホワイト） □ソフトウェアパック（CD-ROM） ① ※Macintosh では使用しません。 ② □ Wii 接続ガイド（LAN-TX/U2B のみ） ※任天堂ゲーム機「Wii」と接続する場合に お読みください。 ③ LAN ケーブルの反対側を、ご利用のネットワーク機器（ハブやルータなど）に接続します。 ● 本製品は、パソコンの USB ポートに直接接続してください。USB ハブなどを経由して接 続すると、供給電力が不足し、正常に動作しないことがあります。 ※ USB ケーブルは取り外せません。 ● 接触不良による誤動作を防ぐため、本体は安定した場所に設置してください。空中にぶら下 がることのないようにしてください。 各部の名称とはたらき 6 しばらくすると、自動的にパソコンに認識さ れ、画面右下のタスクバーにメッセージが表 ① 電源ランプ（PWR） 示されます。 ① 本体の電源が入っているときに、緑色に点灯します。 ● LAN-GTJ/U2B の場合 ASIX AX88178 USB2.0 to Gigabit Ethernet Adapter ② ステータスランプ ● LAN-TX/U2B の場合 ② LAN-GTJ/U2B：100 ASIX AX88772 USB2.0 to Fast Ethernet Adapter 表示される型番は本製品とは異なりますが、 100BASE-TX でリンクが確立しているときに緑色に点灯します。 これで、本製品のセットアップは完了です。 本製品のことを示しています。 ③ 100BASE-TX でデータを送受信しているときに緑色に点滅します。 LAN-TX/U2B：Act データを送受信しているときに緑色に点滅します。 このあとの作業 ○本製品のセットアップが完了しただけでは、インターネットへの接続や、ファイル共有などのネットワーク ③ ステータスランプ LAN-GTJ/U2B：1000
    [Show full text]
  • AX88772C USB 2.0 to 10/100M Fast Ethernet Controller with Microsoft AOAC Support
    AX88772C USB 2.0 to 10/100M Fast Ethernet Controller with Microsoft AOAC Support Features Document No: AX88772C/V1.31/04/11/16 Single chip USB 2.0 to 10/100M Fast Ethernet Support Wake-on-LAN Function controller Supports Suspend Mode and Remote Wakeup Single chip USB 2.0 to RMII, support via Link-change, Magic packet, MS wakeup HomePNA and HomePlug PHY frame and external wakeup pin Single chip USB 2.0 to Reverse-RMII, supports Supports Protocol Offload (ARP & NS) for glueless MAC-to-MAC connections Windows 7 Networking Power Management Optional PHY power down during Suspend USB Device Interface Mode Integrates on-chip USB 2.0 transceiver and Supports 32 MS Wakeup Patterns SIE compliant to USB Spec 1.1 and 2.0 Supports Wakeup packet indication Supports USB Full and High Speed modes Supports Receive Filter Wakeup with Bus-Power or Self-Power capability Supports 4 endpoints on USB interface Supports AutoDetach power saving. Detach Versatile External Media Interface from USB host when Ethernet cable is Optional RMII interface in MAC mode allows unplugged AX88772C to work with HomePNA and High performance packet transfer rate over HomePlug PHY USB bus using proprietary burst transfer Optional Reverse-RMII interface in PHY mechanism (US Patent Approval) mode allows AX88772C to support glueless MAC-to-MAC connections Fast Ethernet Controller Integrates 10/100Mbps Fast Ethernet Advanced Power Management Features MAC/PHY Supports dynamic power management to IEEE 802.3 10BASE-T/100BASE-TX reduce power dissipation during idle or light compatible traffic IEEE 802.3 100BASE-FX compatible Supports very low power Wake-on-LAN Supports twisted pair crossover detection and (WOL) mode when the system enters suspend auto-correction (HP Auto-MDIX) mode and waits for network events to wake it Embedded SRAM for RX/TX packet up.
    [Show full text]
  • Single Chip Microcontroller
    AX88179 USB 3.0 to 10/100/1000M Gigabit Ethernet Controller Features Product Brief Single chip USB 3.0 to 10/100/1000M Gigabit Supports IEEE 802.1Q VLAN tagging and 2 Ethernet controller with Energy Efficient Ethernet VLAN ID filtering; received VLAN Tag (4 bytes) (EEE) base on digital signal processing (DSP) can be stripped off or preserved technology with low dissipation Supports Jumbo frame up to 4KB USB Device Controller PHY loop-back diagnostic capability Integrates on-chip USB 3.0 PHY and controller Support Wake-on-LAN Function compliant to USB Spec 3.0, 2.0 and 1.1 Supports suspend mode and remote wakeup via Supports all USB 3.0 power saving modes (U0, U1, link-change, Magic Packet, Microsoft Wakeup U2, and U3) Frame and external wakeup pin Supports USB Super/High/Full Speed modes with Supports Bonjour wake-on-demand Bus-power or Self-power device auto-detect capability Advanced Power Management Features High performance packet transfer rate over USB Supports power management offload (ARP & NS) bus using proprietary burst transfer mechanism Supports dynamic power management to reduce (US Patent Approval) power dissipation during idle or light traffic Gigabit Ethernet Controller Supports AutoDetach power saving – Supports IEEE 802.3az (Energy Efficient Ethernet) Soft-disconnected from USB host when Ethernet cable is unplugged IEEE 802.3, 802.3u and 802.3ab compatible Supports advanced link down power saving when Integrates 10/100/1000Mbps Gigabit Ethernet Ethernet cable is unplugged MAC/PHY Supports optional serial EEPROM (93c56/66) for Supports dynamic cable length detection and storing USB Descriptors, Node-ID, etc.
    [Show full text]
  • Single Chip Microcontroller
    AX78120/AX78140 USB 2.0 to Multi I/O Controller Features Product Brief Single chip USB 2.0 to Multi I/O (1S, 2S, 4S, operate without external transceivers over short 2S+1P) controller cable Pin-to-Pin compatible with MCS7810 / USB Device Controller MCS7820 / MCS7840 Integrates on-chip USB 2.0 PHY and controller Driver backward compatible with MCS7810 / compliant to USB Spec 2.0 and 1.1 MCS7820 / MCS7840 Supports all USB 2.0 power saving modes (L1, L2) Support Remote Wake Up Function Supports USB High/Full Speed modes with Supports Suspend Mode and Remote Wakeup Bus-power or Self-power device auto-detect via RXD, RI, DSR, DCD and CTS pin capability Supports USB LPM (Link Power Management) Advanced Power Management Features Supports USB LPM (Link Power Management) Dual/Quad Serial Port Controller Supports remote wake up re-trigger Two/four 16c450/16c550 compatible UARTs Supports SIR IrDA mode on any/all ports Parallel Port Supports RS-232, RS-422 and RS-485 serial AX78140 supports optional 2 Serial Port and 1 ports Parallel Port configuration Supports multi-protocol serial transceivers On-Chip 1024-Byte FIFO for upstream and Supports 5, 6, 7 & 8 bit serial data 512-Byte for downstream data transfer for Parallel Port Supports automatic data direction control Supports multi-drop mode with auto address Integrates on-chip 1.8V and 3.3V voltage regulator detection and only requires a single 5V power supply Supports hardware and software flow control Single 12MHz clock input from either crystal or Supports baud rates from 50bps to 6Mbps oscillator
    [Show full text]
  • AX11025 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY
    查询AX11025供应商 捷多邦，专业PCB打样工厂，24小时加急出货 AX11025 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Features Product Brief network protocol stack processing MCU 8-bit pipelined RISC, single cycle per On-chip 10/100M Fast Ethernet MAC and PHY instruction with maximum operating Integrate IEEE 802.3 10BASE-T/100BASE-TX frequency of 100Mhz (100 MIPS) compatible Fast Ethernet MAC and PHY with 100% software compatible with standard dedicated 12KB SRAM for Ethernet packet 8051/80390 buffering. Support full-duplex and half-duplex 4 GPIO ports of 8 bits each operations. Provide optional MII interface (for 2 external interrupt sources with 2 priority HomePNA and HomePlug) levels Support twisted pair crossover detection and Support power management unit, auto-correction (HP Auto-MDIX) programmable watchdog timer, and 3 16-bit Support wakeup via Link-up, Magic packet, timer/counters Wakeup frame or external input pin Debug port for connecting to In-Circuit TCP/IP Emulation (ICE) adaptor Build in TCP/IP accelerator in hardware to 5 channels of Programmable Counter Array improve network transfer throughput. Support (PCA) IP/TCP/UDP/ICMP/IGMP checksum and On-chip Program and Data Memory ARP in hardware Embed 512KB Flash memory, and 16KB Support TCP, UDP, ICMP, IGMP, IPv4, SRAM for program code mirroring. The DHCP, BOOTP, ARP, and HTTP in software external program memory can grow up to Communication Interface 2MB without bank select 3 UART interface (with 1 supporting Support initial Flash memory programming 921.6Kbps and Modem control)
    [Show full text]
  • AX88772B Product Introduction
    AX88772B Product Introduction AX88772B Product Introduction Revision 1.11 st May 21 , 2012 1 Copyright (C) 2010-2012 Reserved by ASIX Electronics Corporation AX88772B Product Introduction Revision History Revision Date Description 1.00 2010/04/29 Initial release 1.10 2010/06/21 1. Added AX88772B USB to 100Base-TX Ethernet (with RMII) Demo Board related information. 2. Updated the Selection Guide in Section 3. 3. Updated AX88772B demo boards naming in Section 4 and 7. 4. Updated Figure 9 “AX88772B USB to 100Base-TX Ethernet Demo Board” picture in Section 7-1. 5. Modified some descriptions in Section 8. 1.11 2012/05/21 1. Updated the Selection Guide in Section 3. 2. Corrected a typo in Section 6. 3. Modified some descriptions in Section 8. 2 Copyright (C) 2010-2012 Reserved by ASIX Electronics Corporation AX88772B Product Introduction Table of Contents 1. Introduction ....................................................................................... 4 2. Block Diagram ................................................................................... 5 2-1. Typical System Block Diagrams ...................................................................... 6 3. Selection Guide .................................................................................. 8 4. Ordering Information ....................................................................... 9 5. Target Applications ......................................................................... 10 6. Mass Production Solutions ............................................................
    [Show full text]
  • ASIX Electronics Corporation
    ASIX Electronics Corporation 4F, NO. 8, Hsin Ann Rd., Science-Based 亞信電子股份有限公司 Industrial Park, Hsin Chu, Taiwan, R.O.C 新竹市科學工業園區新安路 8 號 4F http://www.asix.com.tw TEL:886-3-5799500 FAX:886-3-5799558 ASIX Electronics buys MosChip assets ASIX Electronics Corp. recently announced it has acquired the business line of I/O connectivity, including all assets and intellectual property rights, from India-based MosChip Semiconductor Technology Ltd. The acquisition enhances ASIX’s portfolio of embedded networking and connectivity products by adding single, multi-port Serial, Parallel, Ethernet, VGA, and IrDA connectivity for various computer and peripheral equipment with PCI Express (PCIe), Peripheral Component Interconnect (PCI) and USB host interface. The I/O connectivity products include three series: MCS99xx PCIe bridge controllers, MCS98xx PCI bridge controllers and MCS78xx/MCS77xx USB bridge controllers. For chip-to-chip or system-to-system connections, these controllers provide cost effective, standards compliant, and high-performance embedded system applications, such as remote access servers, storage network management, data acquisition systems, point-of-sale (POS) terminals, handheld devices, set-top box, digital TVs, industrial control and building automation equipment. The PCIe bridge series, MCS99xx, provide a single-chip, PCI Express x1 (single-lane) to a peripheral controller with support for single and multi-port Serial, Parallel, VGA, ISA and USB interfaces. PCIe is an interconnection system based on the PCI standard connecting a microprocessor to attached devices for high-speed operation. The electrical and mechanical interfaces of PCIe are not compatible with the PCI bus interface. This bus also provides a high-speed 2.5GBs data rate.
    [Show full text]
  • Ax220xx RS-232 to Wifi Reference Design User Guide
    AX220xx RS-232 to WiFi Reference Design User Guide AX220xx RS-232 to WiFi Reference Design User Guide Revision 1.20 July 08th, 2011 1 Copyright © 2011 ASIX Electronics Corporation. All rights reserved. AX220xx RS-232 to WiFi Reference Design User Guide Revision History Revision Date Description 1.00 2011/03/10 Initial release. 1.10 2011/04/07 1. Replaced Hyper Terminal with Tera Term for demonstration. 2. Added Appendix C performance report. 1.20 2011/07/08 1. Added the WiFi Wizard and firmware upgrade for Boot Loader, MCPU, and WCPU image. Updated all the related web page figures. 2. Added the WiFi configuration item for Protection Frame Type. 3. Added section 4-3 RS-232 to WiFi Reference Design Jumpers Setting. 4. Added section 7-1-6 Firmware Upgrade Dialog. 5. Updated two web page figures in section 7-3-3 and 7-3-6-1 to correct the configuration description about the file name length and SSID length. 2 Copyright © 2011 ASIX Electronics Corporation. All rights reserved. AX220xx RS-232 to WiFi Reference Design User Guide Table of Contents 1 Introduction ............................................................................... 8 1-1 System Architecture Overview ............................................................. 9 1-2 User Guide Contents .......................................................................... 10 1-3 Additional Resources .......................................................................... 10 2 Block Diagram ......................................................................... 11 3 Features ..................................................................................
    [Show full text]