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Nrf51 Series Reference Manual Version 3.0

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Nrf51 Series Reference Manual Version 3.0 nRF51 Series Reference Manual Version 3.0 The nRF51 series offers a range of ultra-low power System on Chip solutions for your 2.4 GHz wireless products. With the nRF51 series you have a diverse selection of devices including those with embedded Bluetooth® low energy and/or ANT™ protocol stacks as well as open devices enabling you to develop your own proprietary wireless stack and ecosystem. The nRF51 series combines Nordic Semiconductor’s leading 2.4 GHz transceiver technology with a powerful but low power ARM® Cortex™-M0 core, a range of peripherals and memory options. The pin and code compatible devices of the nRF51 series offer you the most flexible platform for all your 2.4 GHz wireless applications. All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. 2014-10-20 Contents Contents 1 Revision history................................................................................... 8 2 About this document...........................................................................9 2.1 Peripheral naming and abbreviations..................................................................................... 9 2.2 Register tables........................................................................................................................ 9 2.2.1 Fields and values...................................................................................................... 9 3 System overview................................................................................11 3.1 Summary............................................................................................................................... 11 3.2 Block diagram....................................................................................................................... 11 3.3 System blocks....................................................................................................................... 12 3.3.1 ARM® Cortex™-M0................................................................................................. 12 3.3.2 2.4 GHz radio..........................................................................................................13 3.3.3 Power management................................................................................................ 13 3.3.4 PPI system.............................................................................................................. 13 3.3.5 Debugger support....................................................................................................13 4 CPU......................................................................................................14 5 Memory................................................................................................15 5.1 Functional description........................................................................................................... 15 5.1.1 Memory categories..................................................................................................15 5.1.2 Memory types..........................................................................................................15 5.1.3 Code memory..........................................................................................................16 5.1.4 Random Access Memory........................................................................................ 16 5.1.5 Peripheral registers................................................................................................. 16 5.2 Instantiation........................................................................................................................... 17 6 Non-Volatile Memory Controller (NVMC)......................................... 18 6.1 Functional description........................................................................................................... 18 6.1.1 Writing to the NVM..................................................................................................18 6.1.2 Writing to User Information Configuration Registers...............................................18 6.1.3 Erase all.................................................................................................................. 18 6.1.4 Erasing a page in code region 1............................................................................ 18 6.1.5 Erasing a page in code region 0............................................................................ 18 6.2 Register Overview.................................................................................................................18 6.3 Register Details.....................................................................................................................19 7 Factory Information Configuration Registers (FICR)......................21 7.1 Functional description........................................................................................................... 21 7.2 Override parameters............................................................................................................. 21 7.3 Register Overview.................................................................................................................21 7.4 Register Details.....................................................................................................................22 Page 2 Contents 8 User Information Configuration Registers (UICR).......................... 25 8.1 Functional description........................................................................................................... 25 8.2 Register Overview.................................................................................................................25 8.3 Register Details.....................................................................................................................26 9 Memory Protection Unit (MPU).........................................................28 9.1 Functional description........................................................................................................... 28 9.1.1 Inputs....................................................................................................................... 28 9.1.2 Output...................................................................................................................... 29 9.1.3 Output decision table.............................................................................................. 29 9.1.4 Exceptions from table..............................................................................................30 9.1.5 NVM protection blocks............................................................................................ 30 9.2 Register Overview.................................................................................................................31 9.3 Register Details.....................................................................................................................31 10 Peripheral interface..........................................................................37 10.1 Functional description......................................................................................................... 37 10.1.1 Peripheral ID......................................................................................................... 37 10.1.2 Bit set and clear....................................................................................................38 10.1.3 Tasks..................................................................................................................... 38 10.1.4 Events....................................................................................................................38 10.1.5 Shortcuts................................................................................................................38 10.1.6 Interrupts................................................................................................................38 11 Debugger Interface (DIF)................................................................. 40 11.1 Functional description......................................................................................................... 40 11.1.1 Normal mode.........................................................................................................40 11.1.2 Debug interface mode...........................................................................................40 11.1.3 Resuming normal mode........................................................................................ 40 12 Power management (POWER)........................................................ 42 12.1 Functional description......................................................................................................... 42 12.1.1 Power supply.........................................................................................................42 12.1.2 Internal LDO setup................................................................................................ 42 12.1.3 DC/DC converter setup......................................................................................... 42 12.1.4 Low voltage mode setup.......................................................................................43 12.1.5 System OFF mode................................................................................................ 44 12.1.6 Emulated System OFF
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