EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884 One Technology Way • P

EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884 One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD7770, AD7771, and AD7779 8-Channel, 24-Bit, Simultaneous Sampling, Sigma-Delta ADCs with Power Scaling

FEATURES GENERAL DESCRIPTION Full featured evaluation board for the AD7770, AD7771, and The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ AD7779 EVAL-AD7779FMCZ evaluation kit features the AD7770, PC control in conjunction with the Analog Devices, Inc., AD7771, and AD7779 24-bit, analog-to-digital converters SDP, EVAL-SDP-CH1Z (ADCs). The board interfaces with the system demonstration PC software control and data analysis platform SDP-H1 controller board (EVAL-SDP-CH1Z). The Time and frequency domain SDP-H1 controller board supplies power to the EVAL- Standalone hardware capability AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ ONLINE RESOURCES evaluation board and also connects to a PC running a Windows® operating system via a USB cable. The AD777x evaluation software Evaluation Kit Contents fully configures the AD7770, AD7771, and AD7779 device EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ register functionality and provides dc and ac time domain EVAL-AD7779FMCZ evaluation board analysis in the form of waveform graphs, histograms, and AD777x evaluation software associated noise analysis for ADC performance evaluation. Documents Needed AD7770, AD7771, and AD7779 data sheet The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL- EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ AD7779FMCZ evaluation board allows the user to evaluate the EVAL-AD7779FMCZ user guide features of the ADC. The user PC software executable controls Required Software the AD7770, AD7771, and AD7779 over the USB cable through AD777x evaluation software the SDP-H1 controller board. EQUIPMENT NEEDED Full specifications for the AD7770, AD7771, or AD7779 are available in the AD7770, AD7771, or AD7779 data sheets and EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ should be consulted in conjunction with this user guide when EVAL-AD7779FMCZ evaluation board working with the evaluation board. System demonstration platform (SDP)—high speed (SDP-H1) controller board (EVAL-SDP-CH1Z) DC/AC signal source (Audio Precision or similar) USB cable PC running Windows 7 with USB 2.0 port An Internet connection may be required on a PC running Windows 8.1 or Windows 10 External 9 V supply (for standalone use)

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

TABLE OF CONTENTS Features ...... 1 Launching the Software ...... 11 Online Resources ...... 1 Software Operation ...... 12 Equipment Needed ...... 1 Overview of the Main Window ...... 12 General Description ...... 1 Configuration Tab ...... 12 Revision History ...... 2 Waveform Tab ...... 14 Evaluation Board Photograph ...... 3 Analysis Tab ...... 15 Evaluation Board Quick Start Guide ...... 4 SAR Tab ...... 17 Analog Inputs and Front-End Circuit ...... 5 Register Map Tab ...... 19 Evaluation Board Hardware ...... 6 Exiting the Software ...... 19 Device Description ...... 6 Evaluation Board Schematics and Layout ...... 20 Hardware Link Options ...... 6 Ordering Information ...... 30 Serial Configuration Interface ...... 9 Bill of Materials ...... 30 Evaluation Board Software ...... 10 Software Installation ...... 10

REVISION HISTORY 7/2017—Rev. A to Rev. B Added AD7771 ...... Universal Added EVAL-AD7771FMCZ ...... Universal Change to Table 5 ...... 30

9/2016—Rev. 0 to Rev. A Added EVAL-AD7770FMCZ ...... Universal Changes to Figure 2 ...... 4 Changes to Device Description Section ...... 6 Changes to Software Installation Section ...... 10 Added Figure 5; Renumbered Sequentially ...... 10 Changes to Overview of the Main Window Section and SD Input Configuration Pop-Up Buttons Section ...... 12 Changes to SAR Configuration Section ...... 17

2/2016—Revision 0: Initial Version

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EVALUATION BOARD PHOTOGRAPH

13550-001 Figure 1. EVAL-AD7770FMCZ Evaluation Board with SDP-H1 Controller Board

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EVALUATION BOARD QUICK START GUIDE To begin using the evaluation board, take the following steps: 3. Ensure that the boards are connected firmly together. 1. Ensure that the evaluation board is disconnected from the 4. By default, the power for the evaluation board is supplied USB port of the PC. Install the AD777x evaluation software from the SDP-H1 controller board. A number of power from the CD included in the evaluation board kit. Restart options available; see Table 3 for more information. the PC after the software installation is complete. (For 5. Connect the SDP-H1 board to the PC using the supplied complete software installation instructions, see the USB cable. Software Installation section.) 6. Launch the AD777x evaluation software from the Analog 2. Connect the SDP-H1 board to the evaluation board: Devices subfolder in the Programs menu. CON J4 of the SDP-H1 board adapts to the receiving socket The pin control mode is not directly supported in the Rev. H on the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ version of the software. EVAL-AD7779FMCZ printed circuit board (PCB).

9V WALL WART, LDO BYPASS OPTIONS

ADR4451 2.5V REFERENCE

AD777x 24-BIT, 8-CHANNEL SAMPLING ADC

SAR AUX_IN±/–SMB

AINx CONNECTIONS SMB/AC INPUTS TERMINAL BLOCK DC INPUTS 13550-002 Figure 2. Hardware Configuration—Setting Up the EVAL-AD7770FMCZ

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ANALOG INPUTS AND FRONT-END CIRCUIT As shown in Figure 2, the AIN0± to AIN7± analog Σ-Δ inputs the AIN0± to AIN7± Σ-Δ inputs when the SAR is used for are available on SMB or terminal block inputs. The AUXIN± redundancy. If this function is required, solder a 0 Ω, 0402 size inputs to the auxiliary successive approximation register (SAR) resistor to the unpopulated resistor footprints (see Figure 17 for converter are available through the SMB inputs. more details), and move SL22 and SL23 to Position A. Figure 2 shows these connectors to the ADC input terminals. The default configuration of the board is as follows: Each analog input differential pair has a second-order RC filter • Connect the input signal from the input terminals through option and common-mode option to center the input signal at the second-order RC filter (do not populate) to the ADC (AVDD1 + AVSSx)/2. An option is available to place an channels. additional VCM buffer in U8 to add drive strength and also • The board accepts ac signals from −1.25 V to +1.25 V. gain, attenuation, or filtering to this VCM signal. Channel 7 has • The ADR441 2.5 V, low noise reference is used by default, the option to evaluate an external drive amplifier using an allowing a differential input range of 0 V to 2.5 V on each amplifier surfboard, to be plugged on J7/J10. The SL3, SL4, input. SL19, and SL20 solder link options select between applying the • AIN±7 analog inputs directly to the RC filter and ADC, or to No external buffers are populated. the surfboard inputs. The evaluation board includes a buffer (AD8659) connected to AIN±0 and AIN±2, and a multiplexer that can be connected to

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EVALUATION BOARD HARDWARE DEVICE DESCRIPTION Embedded analog functionality on each ADC channel eases The AD7770, AD7771, and AD7779 is an 8-channel, system design. The AD7770, AD7771, and AD7779 has a fully simultaneously sampled, 24-bit, Σ-Δ ADC with an additional buffered PGA on each channel to reduce analog input current. diagnostics 12-bit SAR. The AD7770, AD7771, and AD7779 The AD7770, AD7771, and AD7779 also has a reference buffer offers one ADC per channel with synchronized sampling. on each channel, with different operation modes to minimize both the input current from the reference and the reference To cater to application specific ADC power scaling requirements, noise. the user can select either the high resolution mode or low power mode. In high resolution mode, the AD7770 operates at 32 kSPS Full specifications for the AD7770, AD7771, or AD7779 are maximum, the AD7771 operates at 128 kSPS maximum, and the available in the AD7770, AD7771, or AD7779 data sheets and AD7779 operates at 16 kSPS maximum. In low power mode, the should be consulted in conjunction with this user guide when AD7770 operates at 8 kSPS maximum, the AD7771 operates at working with the evaluation board. Full details on the EVAL- 32 kSPS, and the AD7779 operates at 8 kSPS maximum. SDP-CH1Z are available on the Analog Devices, Inc., website at http://www.analog.com/eval-SDP-H1. The AD7770, AD7771, and AD7779 also provides a low latency, sinc3 filter for digital filtering. The notches of the digital filter HARDWARE LINK OPTIONS are automatically set to remove harmonics at the sampling The default power link options are listed in Table 1, Table 2, and frequency and the programmable gain amplifier (PGA) Table 3. The evaluation board can be powered by different chopping frequency. sources, as described in Table 1. By default, the supply required The sample rate converter allows the user to fine tune the for the evaluation board comes from the SDP-H1 controller decimation rate to maintain a number of samples per line cycle board. The supply is regulated by the on-board ADP5070 for varying input frequencies. Choosing a low output data rate switched mode power supply (SMPS), which generates the dual increases the dynamic range, reducing the noise. Decimation supply, and the ADP7118 and the ADP7182 low dropout (LDO) rates can be programmed via the AD777x evaluation software. regulators reduce noise and generate the low noise, regulated, positive and negative rails.

Table 1. Default Link and Solder Link Options for Power Supply Link No. Default Option Description MAIN_SUPPLY A Unregulated input voltage source selection. Position A: the unregulated supply to the on-board LDOs is taken from the SDP-H1 12 V supply. Position B: the unregulated external supply to the on-board LDOs is taken from the J5 9 V wall wart input or from the J6 connector. SL1 A IOVDD supply selection. Position A: IOVDD is supplied from the SDP-H1 board. Set to 3.3 V by default. Position B: IOVDD is supplied from ADP7118 3.3 V, precision LDO. Position C: EXT_IOVDD. IOVDD can be supplied from Pin 3 of the J17 terminal block (1.8 V to 3.3 V). The SDP-H1 only supports 3.3 V logic. If IOVDD is operated below 3.3 V, populate the U6 buffer to avoid electrical problems. SLP1 A AVDD1 supply selection. Position A: AVDD1 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD1 is taken from Pin 1 of J3, AVDD1 external supply. SLP2 A AVDD2 supply selection. Position A: AVDD2 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD2 is taken from Pin 1 of the J17 external source. SLP3 A AVDD4 supply selection. Position A: AVDD4 is taken from U14, the ADP7118 LDO. See SLP6 for more options. Position B: AVDD4 is taken from Pin 2 of the J17 external source. SLP6 A On-board regulated positive rail selection. Position A: 1.65 V. Use this option for dual-supply operation. Position B: 3.3 V. Use this option for single-supply operation. SL24 A Regulated negative rail selection. Position A: AVSSx is taken from U15, the ADP7182 1.65 V LDO. Use this option for dual-supply operation. Position B: AGND. Use this option for single-supply operation. Position C: AVSSx is supplied by Pin 2 of J3, the AVSSx external supply.

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Table 2. AFE Options Link No. Default Option Description SL22 B SAR AUX+ input selection. Position A: AUXIN+ is connected to the on-board multiplexer, which is controlled by the AD7770, AD7771, and AD7779 GPIO pins. If the multiplexer needs to be used, solder the unpopulated resistor that connects the multiplexer inputs to the Σ-Δ ADC inputs. The evaluation board includes an op amp connected to Channel 0 and Channel 2 of the Σ-Δ ADC. Position B: direct connection from source to AUXIN+ SMB connector. SL23 B SAR AUX− input selection. Position A: AUXIN– is connected to the on-board multiplexer which is controlled by the AD7770/AD7771/AD7779 GPIO pins. If the multiplexer needs to be used, solder the unpopulated resistor that connects the multiplexer inputs to the Σ-Δ ADC inputs. The evaluation board includes an op amp connected to Channel 0 and Channel 2 of the Σ-Δ ADC. Position B: direct connection from source to AUXIN– SMB connector. SL3, SL19 A AIN7+ input driver selection. Position A: direct connection from source to AIN7+. Position B: the J7 and J10 surfboard connection drives the analog inputs. SL4, SL20 A AIN7− input driver selection. Position A: direct connection from source to AIN7−. Position B: the J7 and J10 surfboard connection drives the analog inputs. SLP5 A ADR441 external voltage reference supply selection. Position A: the reference is powered by the ADP5070. Use this option if the board is powered by the on-board regulators. Position B: the reference is powered by the AVDD1 supply. Use this option if the board is powered by J3 and J17. SL2 A Voltage reference selection. Position A: the ADR441 is used as a voltage reference. Position B: the internal reference of the AD7770, AD7771, and AD7779 is used. Position C: the ADR441 is buffered and used as a reference. Open: an external voltage reference can be connected to the AD7779_REF SMB connector.

SL25 A Common-mode voltage output (VCM) selection.

Position A: VCM signal to analog front-end signal is AGND. Use this option for dual-supply operation. Position B: the VCM pin is buffered through the U8 output.

Position C: the VCM signal to the analog front end is taken directly from the AD7770, AD7771, and AD7779 VCM pin.

Open: an external VCM signal can be connected to the AD7779_VCM SMB connector.

Table 3. Digital Connections Link No. Default Option Description K0 to K15 Inserted Digital input/output solder links. These links are inserted by default for unbuffered digital input/output connection between the controller board and the evaluation board. Remove and insert U6 for buffered digital inputs/outputs. SL5, SL6 A Data interface format selection. The evaluation software only supports SPI control mode. The default condition is SPI configuration. See the AD7770, AD7771, and AD7779 data sheets for more information. SL7 Inserted SL7 provides a path between the SYNC_OUT and SYNC_IN pins. The user can provide an asynchronous start signal to the device. On the next MCLK falling edge, the AD7770, AD7771, and AD7779 outputs a SYNC_OUT signal, which is synchronous to the MCLK. This signal synchronizes multiple AD7770, AD7771, and AD7779 devices or resets the SD modulators when phase compensation is used. SL8 A Clock selection. Position A: the CLK_SEL pin is pulled low and selects the CMOS clock. Position B: the CLK_SEL pin is pulled high and selects the crystal oscillator placed in Y1. To select this crystal oscillator, remove the SL9 connections and insert R69 and R70. SL9 A CMOS clock input selection: Position A: the on-board CMOS clock is selected (Y2). Position B: J2 can be used to provide an external CMOS clock through the SMB input terminal. Position C: MCLK is supplied from the J1 connector. Rev. B | Page 7 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

Link No. Default Option Description SL10, SL11, SL13 A GPIO/mode pins. In SPI control mode, Pin 13 to Pin 16 act as GPIOs. See the AD7770, AD7771, and AD7779 data sheets for more information about additional functionality of these pins for hardware sample rate update source. Position A: Pin 13 to Pin 16 are connected to the GPIOx net that controls the on-board multiplexer, or can be used to update the SRC (R153 needs to be populated with a 0 Ω resistor). In pin control mode, Pin 13 to Pin 16 (along with SL12) are used to set up the configuration of the device. For more information on GPIO configuration or pin control mode, see the AD7770, AD7771, and AD7779 data sheets. Position B: Pin 13 to Pin 16 are connected to IOVDD. Position C: Pin 13 to Pin 16 are connected to DGND. SL12 A Alert/mode pin. In SPI control mode, this pin operates as an alert flag. Position A: error flag. This pin is connected to the J1 and J4 connectors. See SL21 for more details. In pin control mode, this pin becomes the Mode 3 input pin. Used in conjunction with the GPIO/mode pins to set up the device configuration. See the AD7770, AD7771, and AD7779 data sheets for more details. Position B: the pin is connected to IOVDD. Position C: the pin is connected to DGND. SL14 A CONVST_SAR selection. In SPI control mode, this link selects the conversion signal source. Position A: the SAR ADC is controlled through the J1 connector. In pin control mode, CONVST_SAR (Pin 17), along with SL5 and SL6, set up the serial interface used to read back the conversions from the Σ-Δ ADC. Position A: CONVST_SAR (Pin 17) is connected to IOVDD. Position B: CONVST_SAR (Pin 17) is connected to DGND. SL15, SL16, SL17 A SPI data interface lines. In SPI mode configuration, SCLK, SDI, and SDO are used as digital interface pins. Position A: the SPI data interface lines are connected to the FMC-LPC connector. In pin control mode, these pins define the DCLK frequency used to read back the Σ-Δ data through the DOUT interface. See the AD7770, AD7771, and AD7779 data sheets for more details. Position B: IOVDD. Position C: DGND. SL18 A SPI data interface line. In SPI mode configuration, CS (Pin 18) is used as a digital interface pin. Position A: CS (Pin 18) is connected to the FMC-LPC connector. In pin control mode, CS (Pin 18) acts as an alert pin. Position B: error flag, CS (Pin 18) is connected to the J1 and J4 connectors. See SL21 for more details. SL21 A Alert connection. Position A: SPI control mode. Position B: pin control mode.

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On-Board Connectors SERIAL CONFIGURATION INTERFACE Table 4 provides information about the external connectors The AD7770, AD7771, and AD7779 can be configured by the on the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ field programmable gate array (FPGA) via a 4-wire SPI EVAL-AD7779FMCZ. interface. Format 0 and Format 1 must be shorted to Position A for this mode to be active. Table 4. On-Board Connectors Connector Function To operate the EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ J1 General connector for debugging purpose or to EVAL-AD7779FMCZ evaluation board in standalone mode, connect an external controller 1. Connect a power supply (see Table 1 for options). J2 MCLK connector, supplies the external square 2. Connect the digital signal processor (DSP), wave clock microcontroller, or FPGA to the J1 interface connector. J3 External power supply connector J4 FMC connector J5 External power supply connector J6 External 9 V wall wart connection J7 Channel 7 surfboard evaluation header J8, J9 8-pin connector for input to Channel 0 through Channel 3 J10 Channel 7 surfboard evaluation header J13, J14 8-pin connector for input to Channel 4 through Channel 7 J15 External power supply, supplies all rails independent of LDO supplies

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EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION On a PC running Windows 8.1 or Windows 10, the following The EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/ window may appear with a prompt to install .NET Framework 3.5. EVAL-AD7779FMCZ evaluation kit includes software on a CD. If so, an Internet connection may be required to complete the Click the setup.exe file from the CD to run the installer. The installation. Click Download and install this feature to complete default installation location for the software is the installation. C:\Program Files\Analog Devices\E VA L -AD777xFMCZ. Install the evaluation software before connecting the evaluation board and SDP-H1 board to the USB port of the PC to ensure that the evaluation system is correctly recognized when it is connected to the PC. There are two sections to the installation: • AD777x evaluation software installation • SDP-H1 board drivers installation Place the software and drivers in the appropriate locations by proceeding through all of the installation steps. Connect the SDP-H1 board to the PC only after the software and drivers are installed. The installer may prompt for permission to make 13550-104 Figure 5. .NET Framework 3.5 Installation Prompt changes to the computer. Click Yes to proceed (see Figure 3). After installation is complete, connect the evaluation board to the SDP-H1 controller board. Connect the SDP-H1 controller board via the USB cable to the computer. Follow these steps to verify that the SDP-H1 controller board driver is installed and working correctly: 1. Allow the Found New Hardware Wizard to run. 2. After the drivers are installed, check that the board has connected correctly by looking at the Device Manager of the PC. The Device Manager can be found by right clicking My Computer, selecting Manage, then Device

13550-003 Manager from the list of System Tools (see Figure 6). Figure 3. User Account Control Permission Dialog Box 3. The SDP-H1 board appears under ADI Development A security warning may appear as part of the SDP-H1 controller Tools as Analog Devices SDP-H1 or similar. The board driver installation. Click Install to proceed with the installation is complete. installation of the driver (see Figure 4). Without this confirmation, the software cannot operate correctly.

13550-005 Figure 6. Device Manager

13550-004 Figure 4. EVAL-SDP-CB1Z Drivers Installation Confirmation Dialog Box

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LAUNCHING THE SOFTWARE The AD777x evaluation software can be launched when the evaluation board and the SDP-H1 controller board are correctly connected to the PC.

To launch the software, take the following steps: 13550-006 Figure 7. Select Interface Dialog Box 1. From the Start menu, click Programs, Analog Devices, and then AD777x. The main window of the software then displays (see Figure 7). 2. If the AD7770, AD7771, and AD7779 evaluation system is not connected to the USB port via the SDP-H1 board when the software is launched, the Select Interface… dialog box appears. Connect the evaluation board to the USB port of the PC, wait a few seconds, and then click the green arrows to rescan the USB ports. When the connection is established, click Work Online to proceed.

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SOFTWARE OPERATION

2 1

6 5

9 3 4 7 8

10 11

14 15

13550-007 Figure 8. Configuration Tab of the AD7779 Evaluation Software OVERVIEW OF THE MAIN WINDOW SD Input Configuration Pop-Up Buttons The main window of the software displays the significant The SD input configuration pop-up buttons (Label 4) select the control buttons and analysis indicators of the evaluation board ADC gain, enable the diagnostic mux to be the input for the software (see Figure 8). Depending on which evaluation board channel (Rx), disable the SD channel, or configure the channel is connected to the PC, the software title at the top of the to monitor the voltage reference. Clicking this button selects the window displays the corresponding device (AD7770, AD7771, SD reference as AVDD3/AVSSx for all channels and the input or AD7779). The main window is divided into five tabs. diagnostic mux as the input for this channel. CONFIGURATION TAB Reference Voltage Pop-Up Buttons General Configuration The reference voltage pop-up buttons (Label 5) set the reference The general configuration controls (Label 2 in Figure 8) define voltage used for calculating the results in the Waveform and the voltage reference, external clock, the output data rate, number Histogram tabs. The evaluation board has an external 2.5 V ADR441 reference; however, this reference can be bypassed of samples, and if the sigma delta (ΣΔ) is read continuously or using this pop-up button, and the user can change the external one time only. reference voltage value to ensure correct calculation of results in When changing the ODR (SPS) value, click away from the field the Waveform and Histogram tabs. Internal reference and to process the update. The software programs the sample rate reference buffers can be selected using these pop-up buttons. If converter (SRC) registers accordingly. AVDD3/AVSSx is selected as the reference, the REF (V) value Click SD Sample to acquire samples from the AD7770, AD7771, must be updated accordingly. and AD7779. Regulators Pop-Up Button ΣΔ ADC Diagnostic Pop-Up Button The regulators pop-up button (Label 6) allows the user to The ΣΔ ADC diagnostic pop-up button (Label 3) selects the overdrive the internal LDOs externally, and also provides internal diagnostic inputs from the multiplexer. This input is information about the error detected on the regulators. common for all eight ADCs.

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SD Errors Pop-up Buttons Error Test Pop-Up Button The SD errors pop-up buttons (Label 7) show the errors The error test pop-up button (Label 11) enables and disables the detected on the SD channel. different error checkers implemented in the AD7770, AD7771, Gain, Offset, and Phase Pop-up Buttons and AD7779. The gain, offset, and phase pop-up buttons (Label 8) allow the Data Output Interface Pop-Up Button user to calibrate the offset and gain of each specific SD channel. The data output interface pop-up button (Label 12) adjusts the After the phase compensation updates, click START to apply DOUT header and driver strength. the change. SPI Interface Pop-Up Button START Button The SPI interface pop-up button (Label 13) adjusts the various Clicking START (Label 9) generates a pulse on the START pin parameters for the SPI and shows any SPI errors. to reset the internal sinc filter, which ensures that any update on SAR Input Pop-Up Button the phase compensation register is correctly applied. The SAR input pop-up button (Label 14) allows the user to Control Configuration Pop-Up Button select the input signal for the SAR ADC. The control configuration pop-up button (Label 10) allows the SAR Power Pop-Up Button user to configure features such as the power mode (must be set The SAR power pop-up button (Label 15) enables and disables to high power mode, unless a different clock is provided), the the SAR ADC. If the SAR is disabled, the SAR input mux is common-mode voltage (VCM), the internal oscillator, and the disabled as well. mode to update the ODR (SRC registers). Status Bar It is recommended not to change the SRC load source (Bit 7 in the SRC_UPDATE register, Address 0x064), because SRC_LOAD_ The status bar (Label 16) displays the status of the board and SOURCE can only be enabled via the GUI. Setting Bit 7 of indicates if the board is busy and cannot perform any other Address 0x064 enables updating SRC via the hardware, which action. is not supported on the current evaluation board. The SRC register can be updated manually; however, the update is not reflected in the ODR (SPS) field.

Errors related to the memory map appear in this pop-up.

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18 21

20 19 22 23

13550-008 Figure 9. Waveform Tab of the AD7779 Evaluation Software WAVEFORM TAB Display Units and Axis Controls Waveform Graph and Controls Use the Display Units drop-down box (Label 22) to select The data waveform (Label 18) shows each successive sample of whether the data graph displays in units of voltages or codes. the ADC output. The control tools (Label 20) in the graph allow This affects both the waveform graph and the histogram graph. the user to zoom in on the data. Change the scales on the graph The axis controls can be switched between dynamic and fixed. by typing values into the x-axis and y-axis. When dynamic is selected, the axis automatically adjusts to show the entire range of the ADC results after each batch of Analysis Channel samples. When fixed is selected, the user can program the axis The noise/waveform analysis section (Label 24) and histogram ranges manually, and the ranges do not adjust automatically graph show the analysis of the channel selected via the Analysis after each sample batch. Ch drop-down box (Label 19). If the value is selected as hex, the x-axis of the graph shows the Channel Selection original data (twos complement). Due to the limitations of the The channel selection control (Label 21) allows the user to software, the number shows as signed 32 bits rather than signed choose which channels display on the data waveform. It also 24 bits. shows the analog inputs for that channel labeled next to the on Save Data and off controls. These controls only affect the display of the Click Save (Label 23) to save the samples to an external file. channels and do not have any effect on the channel settings in the ADC register map. Waveform Analysis The Waveform Analysis section (Label 24) displays the results of the noise analysis for the selected analysis channel. The rms noise is only applicable with a constant dc value.

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13550-009 Figure 10. Analysis Tab of the AD7779 Evaluation Software ANALYSIS TAB Channel Selection FFT Graph and Histogram Selection The Analysis Ch control (Label 30) allows the user to choose Use the FFT/histogram selection box (Label 26) to select which channels display on the data waveform. It also shows the between histogram and frequency analysis of the data. analog inputs for that channel labeled next to the on and off controls. These controls only affect the display of the channels FFT Graph and Controls and do not have any effect on the channel settings in the ADC The FFT graph (Label 27) shows the fast Fourier transform of register map. the sampled signal. Note that the windows applied is the 7-term FFT Window Selection Blackman Harris. The frequency is displayed on the x-axis and the amplitude is graphed on the y-axis. Use the control tools The FFT window control allows the user to choose which (Label 28) to zoom in on the data. Harmonic content can be external windowing method to apply to calculate the discrete selected by clicking Show Harmonic Content. Fourier transform. Analysis Channel The noise/waveform analysis section (Label 29) and the FFT graph show the analysis of the channel selected via the Analysis Ch control (Label 30).

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13550-010 Figure 11. Histogram Tab of the AD7779 Evaluation Board Software Histogram and Controls Histogram Analysis The data histogram (Label 31) shows the number of times each The Histogram Analysis section (Label 32) shows the analysis sample of the ADC output occurs. The control tools in the of the channel selected via the Analysis Ch control. graph allow the user to zoom in on the data. Change the scales on the graph by typing values into the x-axis and y-axis.

Rev. B | Page 16 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

34 37 38

13550-011 Figure 12. SAR Waveform Tab of the AD7779 Evaluation Software SAR TAB Analysis Channel When the SAR ADC is enabled through the SAR power pop-up The noise/waveform analysis section (Label 39) and histogram button (Label 15 in Figure 8), the SAR tab allows the user to graph show the analysis of the channel selected via the sample and analyze data from the SAR ADC. Analysis Ch control. FFT Graph and Waveform Selection SAR Configuration Use the FFT/waveform selection box (Label 34) to select between The SAR configuration controls (Label 37) allow the user to waveform and frequency analysis of the data. define the number of samples and the through output rate. Waveform Graph and Controls SAR Sample The data waveform (Label 35) shows each successive sample of Click SAR Sample (Label 38) to gather samples from the SAR. the ADC output. The control tools (Label 36) in the graph allow By clicking SAR Sample, the GUI configures the SPI interface the user to zoom in on the data. Change the scales on the graph to read back the data from the SAR. When the data is read back, by typing values into the x-axis and y-axis. the SPI is configured to read back data from the register map. Before clicking SAR Sample, enable the SAR using the SAR input pop-up button.

Rev. B | Page 17 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

13550-012 Figure 13. SAR FFT Tab of the AD7779 Evaluation Software

FFT Graph and Controls Analysis Channel The FFT graph (Label 40) shows the fast Fourier transform of The noise/waveform analysis section (Label 42) and FFT graph the sampled signal. The frequency is displayed on the x-axis and show the analysis of the channel selected via the Analysis Ch the amplitude is graphed on the y-axis. Use the control tools control. (Label 41) to zoom in on the data. Harmonic content can be selected by clicking Show Harmonic Content.

Rev. B | Page 18 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

44 45

48 49

13550-013 Figure 14. Register Map and Configuration REGISTER MAP TAB Documentation Register Tree The Documentation section (Label 47) contains the The register tree (Label 44) shows the full register map in a tree documentation for the register and bitfield selected in the control. Each register is shown. Click the expand button next to register tree (Label 44). each register to show all the bitfields contained within that register. Save and Load Register Control The Save and Load buttons (Label 48 and Label 49) allow the The Register control (Label 45) allows the user to change the user to save the current register map setting to a file and load individual bits of the register selected in the register tree (Label 44). the setting from the same file. Click on each bit to toggle the value, or program the register EXITING THE SOFTWARE value directly into the number control field on the right. To exit the software, click the close button at the top, right Bitfields List corner of the main window. The Bitfields list (Label 46) shows all the bitfields of the register selected in the register tree (Label 44). The values can be changed using the drop-down box or by entering a value directly into the number control on the right.

Rev. B | Page 19 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

EVALUATION BOARD SCHEMATICS AND LAYOUT 13550-014 SYNC_IN_B RESET_B SDI_BUFFERED SCLK_BUFFERED CS_BUFFERED DCLK_B DRDY_B DOUT0_B DOUT1_B DOUT2_B DOUT3_B SDO_BUFFERED SDP_MCLK SDP_CONVST START_B ALERT_B SCLK SDI SDO CS IOVDD DNI VIO ALERT_PIN IOVDD IOVDD IOVDD U6 SN74LVCH16T245-EP

23 22 24 20 19 14 13 12 11 9 8 6 5 17 16 3 2 1

GND

VCCB C62 0.1uF

4 7

A B GND

GND

2B8 2B7 VCCB 2B6 2B5 2B2 2B1 1B8 1B7 1B6 1B5 1B4 1B3 2B4 2B3 1B2 1B1

21 18 A A A B C B C B C 2DIR 1DIR SL18

GND

SL17 SL16 SL15 28

GND

VCCA

GND 0.1uF K9 K8 K6 K7 K0 K1 K2 K3 K4 K5

C61

K14 42 K13 K12 K11 K15 K10 GND VCCA

45 31

GND 10 MIGHT NOT PLACE NOT MIGHT 1A2 1A1 1OE 1A4 1A3 1A6 1A5 2A2 2A1 1A8 1A7 2A4 2A3 2A6 2A5 2A8 2A7 2OE DCLK2/SCLK 46 47 48 43 44 40 41 35 36 37 38 32 33 29 30 26 27 25 DCLK1/SDI DCLK0/SDO ALERT/CS IOVDD DOUT2

DOUT1

SDO

A DOUT0 B CS SDI SL21 SCLK CONVST SYNC_IN ALERT DCLK DRDY DOUT3 ALERT_SPI ALERT_PIN CONVST

SDP_MCLK_BUFFERED

START SL14

DNI 0Ω 0Ω A 0Ω 0Ω 0Ω 0Ω 0Ω RESET

IOVDD

B C R152 10kΩ R77 R76 R72 R71 R74 R73 R149 R150 CONV_SAR DNI R155 IOVDD MODE3 MODE2 MODE1 MODE0 36 33 29 30 28 27 26 25 18 19 20 21 17 CS SDI SDO SCLK DCLK DRDY MODE3 MODE2 MODE1 MODE0 RESET START DOUT0 DOUT1 DOUT2 DOUT3 16 34 SYNC_OUT MODE3 SYNC_OUT SL7 CONVST_SAR 15 SYNC_IN SL7 LINKS 0Ω DEFAULT IN R75 TO SYNC_OUT TO MODE2 IOVDD 35 SYNC_IN 14 IOVDD MODE1 SYNCIN 13 SL6 A MODE0 C60 B B 55 0.1uF FORMAT0 IOVDD 0Ω B

R109 56 SL5

A CLK_SEL A DEFAULT 0Ω R154 SL8 A 54 FORMAT1 IOVDD 4 1 XT1 ST VCC C58 DNI DREGCAP DNI 0.1uF Y2 23 DREGCAP 8.192MHz OUT GND C46 C47 DNI R68 3 2 31 DGND DNI 22 R66 DNI XTAL1 0.1uF 1uF R69 C51 C48 IOVDD 24

DNI AVSSX R67 DEFAULT SETTING: Y1 ADC DEFAULT SPI MODE SPI ADC DEFAULT 32 PLACE CLOCK AND XTAL AS CLOSE TO THE PART AS POSSIBLE AS PART THE TO CLOSE AS AND XTAL CLOCK PLACE 8.192MHz FORMAT0 (SL5), FORMAT1(SL6) = A, A = FORMAT1(SL6) (SL5), FORMAT0 50 AVSS2B DNI IOVDD 1uF MCLK/XTAL2 0.1uF R70 C59 DNI C45 C44 52

AVDDSB 41 SL9

REF2+ A 1uF 0.1uF

51 XT2 DNI B

0.1uF

AREG2CAP 42 C C53 C55 C43 C42 U1 REF2– AVSS3 53 AD7770 MCLK DNI AVSSX 7 0.1uF 59 DEFAULT A AREG1CAP REF– C41 1uF C40 0.1uF AVSSX 60 1uF AVSS2A 8 C54 C52 0.1uF REF+ C38 58 C39 AVDD2A VREF 6 49 SDP_MCLK_BUFFERED AVDD1A 0.1uF 1uF REF_OUT DNI 0.1uF AVDD2 C35 C37 5

C57 C56 AVSSX AVSS1A 61 AVSS4 MODE0 MODE2 MODE3 44 1uF AVSS1B MODE1 0.1uF 1uF AVSSX 0.1uF C50 C49 62 C36 C34 43 AVDD1B AD7770_REF_OUT AVDD4 A A A A B C B C B C B C 65 SL13 SL12 SL11 SL10 AVDD4 64 AUXAIN– PADDLE AVDD1 63 AUXAIN+ VCM AIN4+ AIN4– AIN5+ AIN5– AIN6– AIN6+ AIN7+ AIN7– AIN0– AIN0+ AIN1– AIN1+ AIN2+ AIN2– AIN3+ AIN3– 1 2 3 4 9 AVSSX 45 46 40 12 57 47 48 39 37 38 10 11 IOVDD IOVDD IOVDD IOVDD ALERT_SPI 0Ω R153 DNI AUX- R111 AUX+ AIN0- AIN1- AIN2- AIN3- AIN4- AIN5- AIN6- AIN7- AIN0+ AIN1+ AIN2+ AIN3+ AIN4+ AIN5+ AIN6+ AIN7+ GPIO0 GPIO1 GPIO2 DNI C89 Figure 15. Evaluation Board Schematic—Page 1 Rev. B | Page 20 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

AIN0+

R8 R3 R2 AIN0+ AIN0+ 0Ω 0Ω 0Ω AI0+ R5 1kΩ DNI C1 C4 C3 VCM_OUT DNI DNI DNI C2 R6 1kΩ AIN0– AIN0– R9 R4 R1 AIN0– 0Ω 0Ω 0Ω AI0– AIN1+

AIN1+ R16 R12 R11 AIN1+

AI1+ 0Ω 0Ω 0Ω DNI R14 1kΩ C6 C9 C8 DNI DNI VCM_OUT DNI C7

R15 1kΩ AIN1–

AIN1– R17 R13 R10 AIN1– 0Ω 0Ω 0Ω AI1– 8 8 7 7 6 6 5 5 AIN2+ AIN2+ 4 4 3 3 2 2 R24 R20 R19 1 1 AIN2+ SREWTERM–8_RA J13 J14 0Ω 0Ω 0Ω AI2+

GND9 GND R22 1kΩ DNI C10 C13 C12 VCM_OUT DNI DNI DNI C11 R23 1kΩ AGND AIN2–

AIN2– R25 R21 R18 AIN2– 0Ω 0Ω 0Ω AI2–

AIN3+ AIN3+ R32 R28 R27 AIN3+ 0Ω 0Ω 0Ω

AI3+ R30 1kΩ DNI C14 C17 C16 VCM_OUT DNI DNI DNI C15 R31 1kΩ AIN3–

AIN3– R33 R29 R26 AIN3– AI3– 0Ω 0Ω 0Ω

13550-015 Figure 16. Evaluation Board Schematic—Page 2

Rev. B | Page 21 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

R40 R36 R35 AIN4+ AIN4+ AI4+ 0Ω 0Ω 0Ω

R38 1kΩ DNI C18 C21 C20 DNI DNI VCM_OUT DNI C19 R39 1kΩ

R41 R37 R34 AIN4– AIN4– 0Ω 0Ω 0Ω AI4–

R48 R44 R43 AIN5+ AIN5+

AI5+ 0Ω 0Ω 0Ω

R46 1kΩ DNI C25 C24 C22 VCM_OUT DNI DNI

DNI C23 J8 J9 R47 1kΩ 1 1 2 2 3 3 R49 R45 R42 AIN5– 4 4 AIN5– 5 5 6 6 AI5– 0Ω 0Ω 0Ω 7 7 8 8 SREWTERM–8_RA

R56 R52 R51 AIN6+ AIN6+ GND8 GND7 DEFAULT A 0Ω 0Ω 0Ω AI6+

R54 1kΩ DNI C26 C29 C28 AGND AGND VCM_OUT DNI DNI DNI C27 R55 1kΩ

AIN6– R57 R53 R50 AIN6– 0Ω 0Ω 0Ω AI6– SURF_7_IN+

SURF_7_OUT+ B B R64 0Ω R60 R59 AIN7+ AIN7+ A A 0Ω 0Ω AI7+ SL19 SL3 R62 1kΩ DNI C30 C33 C32 VCM_OUT DNI DNI DNI C31

R63 1kΩ SL20 SL4 A AIN7– A R65 0Ω R61 R58 AIN7– B AI7– B 0Ω 0Ω

SURF_7_OUT–

SURF_7_IN–

SAR INPUT MUX AUX– AUX+ SL22 SL23 A AUX+_SW A AUX–_SW AUX+ AUX– B B

AUXIN+ AUXIN– AUXIN+ AUXIN–

1 28 AUX+_SW AVDD1 2 VDD DA 27 AUX–_SW DB VSS AVSSX 3 26 R148 DNI AIN7+ 4 NC S8A 25 AIN7– R127 DNI R156 DNI AIN6+ 5 S8B S7A 24 AIN6– R89 DNI R157 DNI AIN5+ 6 S7B S6A 23 AIN5– R110 DNI R158 DNI AIN4+ 7 S6B S5A 22 AIN4– R116 DNI R159 DNI AIN3+ 8 S5B S4A 21 AIN3– R117 DNI R160 DNI AIN2+ 9 S4B S3A 20 AIN2– R125 DNI R146 DNI AIN1+ 10 S3B S2A 19 AIN1– R126 DNI R147 DNI AIN0+ 11 S2B S1A 18 AIN0– R128 DNI AVDD1 12 S1B EN 17 GND A0 GPIO0 13 16 GPIO1 14 NC A1 15 NC A2 GPIO2 U11 ADG707BRUZ

8 12 – – 7 14 U12-C U12-D 9 11 + +

AD8659ACPZ-R7 AD8659ACPZ-R7

1 5 – – 15 6 U12-A U12-B 2 4 + +

AD8659ACPZ-R7 AD8659ACPZ-R7

13550-016 Figure 17. Evaluation Board Schematic—Page 3

Rev. B | Page 22 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

13550-017 R79 1kΩ SI2304DDS-T1-GE3 D6 GREEN Q1 10kΩ R91 REG_EN_SMPS SMPS_EN ANALOG_LDO_EN R84 10kΩ DIGITAL_LDO_EN R83 10kΩ R82 10kΩ 0Ω 0Ω 0Ω 0Ω R103 R102 R101 R100 9 8 7 6 OUT1 OUT2 OUT3 PWRGD 10 1 GND VDD VIN1 VIN2 VIN3 VIN4 U7 ADM1185ARMZ 2 3 4 5 V_5V1_DIODE 0Ω R96 0Ω 0Ω 0Ω R99 R98 R97 R87 10.2kΩ 39kΩ R92 10.2kΩ R85 R81 86k6 DNI C72 0Ω 0Ω R78 R132 V-POS DNI C74 Power Sequence Control R88 10.2kΩ R86 10.2kΩ STAR POINT GROUND R90 10.2kΩ DNI C73 DNI 39kΩ R80 C71 VREG Q2 E C V_5V1_DIODE AVDD1 R94 61.9kΩ B D2 R93 4.53kΩ VIN VIN_EXT VIN C70

10µF N/A EXT_AVDD2 EXT_IOVDD EXT_AVDD4 D1 DNI EXT_AVDD1 EXT_AVSSX B A C93 C69 0.1µF PGND 0.1µF C107 0.1µF C5 MAIN_SUPPLY C85 0.1µF 0.1µF J6 = JACK CONNECTOR JACK = J6 C91 C94 10µF 10µF 10µF C108 J5-4 J5-2 J5-1 J5-3 C63 C87 10µF 10µF +12V VIN_EXT 1 1 2 3 4 1 2 3 J3 2 3 J17 J6 POWER SUPPLY : JACK/BENCH OR FMZ CONNECTION V+ GND GND DGND IOVDD AVSSx AVDD1 AVDD2 AVDD4

EXTERNAL SUPPLY: STAND-ALONE OPERATION SUPPLY: STAND-ALONE EXTERNAL Figure 18. Evaluation Board Schematic—Page 4

Rev. B | Page 23 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

13550-018 AVDD4 AVDD2 AVDD1 AVSSX AVDD4 AVDD1 AVDD2 0Ω R181 0Ω C123 0.1µF AVSSX R182 0Ω R183 R142 2kΩ A B 0Ω B A SLP3 SLP2 C77 0.1µF D4 RED R180 C65 0.1µF C64 0.1µF A B C SL24 B A SLP1 EXT_AVDD2 DEFAULT À EXT_AVDD4

EXT_AVSSX

C96 2.2µF

17.4kΩ R169

C120 2.2µF

EXT_AVDD1 3.75kΩ R170 A B R172 3.57kΩ R171 10kΩ SLP6 R168 10kΩ AVDD1/2/4 SUPPLY SELECTION 1 2 5 3 C75 1nF 5 1 2 NC ADJ VOUT VOUT

DNI U15 R178 GND VOUT 3 R179 DNI ADP7182ACPZ GND U14 VIN VIN PADDLE EN SENSE/ADJ 7 8 9 4 VIN EN EP(GND) ADP7118ACPZN 6 4 7 C119 2.2µF AVDD1 C95 2.2µF V-POS V-NEG ANALOG_LDO_EN -3.3V IOVDD V-POS V-NEG C118 2.2µF

kΩ

17.4kΩ -3V3 10kΩ IOVDD R164 64.9

VPOS

VNEG

0Ω R174 R173 R184 5.1kΩ 1 2 5 3 R141 PGND DGND 47µF C101 NC ADJ

D5 VOUT VOUT

RED 6 14Ω DNI C116 22µF

L2 U5

R165 1µH GND R177 R163 107kΩ R162 16.2kΩ VIN VIN PADDLE EN ADP7182ACPZ PGND kΩ 7 8 9 4 A C B SL1 16.9 1µH C111 1µF +3.3V L3 R166 PGND C117 2.2µF D7 VIO kΩ C102 4.7µF 17.8 4 3 1µF EXT_IOVDD DGND C68 2.2µF PGND V-NEG 1µF A2 DGND C109 D3 R145 1 2 C110 LPD5030-682MRP ±3.3V RAIL FOR BUFFERS 1 2 5 +3.3V IOVDD SUPPLY SELECTION 12µH L1 1nF C76 SS PGND DGND VOUT 3 U3 DNI R175 GND 12 11 1 5 20 19 18 +3V3 VIN SENSE/ADJ C80 2.2µF VIN EP(GND) EN FB2 FB1 SW1 SW2 ADP7118ACPZN-3.3 INBK 21 VREF PGND 6 7 4 C82 1nF EP U10 13 5 1 2 AGND ADP5070ACPZ SS SS COMP1 EN1 EN2 COMP2 SYNC SLEW SEQ VREG PVIN1 PVIN2 PVINSYS DGND VOUT 8 6 7 9 2 4 3 C67 3 2.2µF 10 14 15 17 16 DNI R176 U13 GND SENSE/ADJ SMPS +5/+12V INPUT +5/+12V SMPS VIN EP(GND) EN ADP7118ACPZN-3.3 6 7 4 10µF C115 8.66kΩ 17.8kΩ 6.19kΩ VIN SMPS_EN C81 2.2µF R167 R143 R144 1µF AGND VREG V-POS 27nF 39pF 56pF 33nF C114 REG_EN_SMPS C66 VREG C113 C112 C100 V-POS DIGITAL_LDO_EN ANALOG_LDO_EN PGND Figure 19. Evaluation Board Schematic—Page 5

Rev. B | Page 24 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

PRECISION VOLTAGE REFERENCE

AVDD1 REFERENCE 2.5V REFERENCE EXT_REF

R104 B 2 6 EXT_REF V-POS A +VIN VOUT SLP5 C99 C98 U2 15Ω DEFAULT A ADR441BRZ C79 C78 5 10µF 0.1µF TRIM 0.1µF 22µF GND 4

AVSSX

ENSURE THIS IS ADR441 ON BOM

AD7770 REFERENCE OUT SL2 A R123 AD7770_REF_OUT B VREF 0Ω C97 C DNI AD7770_REF REFERENCE BUFFER AVSSX AVSSX

+3.3V

C84 C92 8 0.1µF 10µF V+ U8-C ADA4896-2 KEEP REFERENCE TRACK AS SHORT AS POSSIBLE 4 V–

–3.3V

R120 DNI

C86 DNI R114

R106 0Ω DNI

2 R95 IN– 1 R105 0Ω 3 OUT EXT_REF IN+ 0Ω U8-A ADA4896-2 C90

DNI DNI R124

AVSSX

VCM BUFFER R119 DNI

C88 DNI

R113 DNI VCM_OUT R112 0Ω VCM

ADA4896-2 VCM_OUT C 6 R121 R108 IN– 7 5 OUT B VCM IN+ 0Ω 0Ω A C83 AD7770_VCM SL25 DNI U8-B

AVSSX

OPTIONAL HEADER CONNECTOR (SURF BOARD FOR CH7)

R7 0Ω J7-1 SURF_7_IN+ J10-1 SURF_7_OUT+

J7-2 J10-2 AGND

0Ω R115 J10-3 J7-3 +3.3V 0Ω R118 J10-4 J7-4 VCM_OUT 0Ω R122 J10-5 J7-5 –3.3V J10-6 J7-6 R107 0Ω J10-7 SURF_7_OUT– J7-7 SURF_7_IN-

13550-019 Figure 20. Evaluation Board Schematic—Page 6

Rev. B | Page 25 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

J4-B ASP-134604-01 D1 PG_C2M J4-C D2 GND D3 GND ASP-134604-01 D4 NO CONNECT DRDY_B G1 GND J4-A D5 NO CONNECT DOUT0_B G2 CLK1_M2C_P ASP-134604-01 D6 GND G3 CLK1_M2C_N C1 D7 G4 GND GND SCLK_BUFFERED GND C2 NO CONNECT D8 AE23 LA01_P_CC G5 GND C3 D9 G6 AD23 LA00_P_CC NO CONNECT SDP_MCLK AF23 LA01_N_CC C4 GND D10 GND G7 AE24 LA00_N_CC C5 GND D11 AG22 LA05_P G8 GND C6 CS_BUFFERED D12 G9 AG20 LA03_P RESET_B NO CONNECT AH22 LA05_N SDO_BUFFERED C7 NO CONNECT D13 GND START_B G10 AH20 LA03_N C8 D14 G11 GND DOUT1_B GND SDP_CONVST AK23 LA09_P C9 GND D15 AK24 LA09_N G12 AJ22 LA08_P C10 D16 G13 AJ23 LA08_N ALERT_B AK20 LA06_P GND C11 AK21 LA06_N D17 AB24 LA13_P G14 GND C12 GND D18 AC25 LA13_N G15 AA20 LA12_P C13 GND D19 GND G16 AB20 LA12_N J15 C14 AJ24 LA10_P D20 AB27 LA17_P_CC G17 GND 1 C15 AK25 LA10_N D21 AC27 LA17_N_CC G18 AC22 LA16_P 2 C16 GND D22 GND G19 AD22 LA16_N 3 VIN C17 GND D23 AH26 LA23_P G20 GND 4 VIO C18 AD21 LA14_P D24 AH27 LA23_N G21 AF26 LA20_P C19 AE21 LA14_N D25 GND G22 AF27 LA20_N C20 GND D26 AK29 LA26_P G23 GND HEADER-4X1POL C21 GND D27 AK30 LA26_N G24 AJ27 LA22_P C22 AD27 LA18_P_CC D28 GND G25 AK28 LA22_N C23 AD28 LA18_N_CC D29 TCK G26 GND C24 GND D30 TDI G27 AC26 LA25_P C25 GND D31 TDO G28 AD26 LA25_N C26 D32 G29 GND AJ28 LA27_P 3P3VAUX 3P3VAUX C27 AJ29 LA27_N D33 TMS G30 AE28 LA29_P C28 GND D34 TRST_L G31 AF28 LA29_N C29 D35 G32 GND GND GA1 GA1 C30 SCL D36 3P3V G33 AD29 LA31_P C31 SDA D37 GND G34 AE29 LA31_N C32 GND D38 3P3V G35 GND C33 GND D39 GND G36 AC29 LA33_P C34 D40 G37 AC30 LA33_N GA0 GA0 3P3V C35 12P0V G38 GND C36 G39 VADJ +12V GND C37 12P0V G40 GND C38 GND C39 3P3V VIO C40 GND IF EVAL BOARD DOES NOT USE JTAG TDI AND TDO THEN THEY MUST BE SHORTED TOGETHER (AS SHOWN) SO AS NOT TO BREAK JTAG CHAIN

3P3VAUX 8 U9 J4-D BOARD PRESENT PIN VCC ASP-134604-01 1 H1 GA1 E0 NO CONNECT 2 5 I2C ADDRESS SET BY CONTROLLER BOARD H2 PRSNT_M2C_L GA0 3 E1 SDA H3 E2 GND DCLK_B H4 AF22 CLK0_M2C_P 6 H5 SCL AG23 CLK0_M2C_N H6 GND 7 H7 WP DOUT2_B AF20 LA02_P DOUT3_B H8 AF21 LA02_N VSS H9 GND 4 M24C02-WDW6TP H10 AH21 LA04_P SYNC_IN_B H11 SDI_BUFFERED AJ21 LA04_N H12 GND H13 AG25 LA07_P H14 AH25 LA07_N H15 GND EEPROM REQUIRED IN VITA STANDARD I2C LINE PULL-UP RESISTORS ON FPGA BOARD H16 AE25 LA11_P H17 AF25 LA11_N H18 GND H19 AC24 LA15_P H20 AD24 LA15_N H21 GND H22 AJ26 LA19_P H23 AK26 LA19_N H24 GND H25 AG27 LA21_P H26 AG28 LA21_N H27 GND H28 AG30 LA24_P H29 AH30 LA24_N HEADER-10X2 H30 GND 1 2 START H31 AE30 LA28_P DCLK 3 4 DRDY H32 AF30 LA28_N RESET 5 6 ALERT H33 GND SDP_MCLK_BUFFERED 7 8 CONVST H34 AB29 LA30_P DOUT0 9 10 DOUT1 H35 AB30 LA30_N DOUT2 11 12 DOUT3 H36 GND SYNC_IN 13 14 CS R129 H37 Y30 LA32_P SCLK 15 16 SDI H38 GPIO2 AA30 LA32_N SDO 17 18 VIO H39 GND GPIO2 19 20 +12V 0Ω H40 VIO VADJ J1

13550-020 Figure 21. Evaluation Board Schematic—Page 7

Rev. B | Page 26 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

13550-021 Figure 22. Evaluation Board Layout, Component Side (Top)

13550-022 Figure 23. Evaluation Board Layout, Component Side (Bottom)

Rev. B | Page 27 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

13550-023 Figure 24. Evaluation Board Layout, Layer 1, Component Side

13550-024 Figure 25. Evaluation Board Layout, Layer 2, GND Planes

Rev. B | Page 28 of 32 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide UG-884

13550-025 Figure 26. Evaluation Board Layout, Layer 3, Power Traces and GND Planes

13550-026 Figure 27. Evaluation Board Layout, Layer 4, Solder Side

Rev. B | Page 29 of 32 UG-884 EVAL-AD7770FMCZ/EVAL-AD7771FMCZ/EVAL-AD7779FMCZ User Guide

ORDERING INFORMATION BILL OF MATERIALS

Table 5. Reference Designator Value Description Part Number +3V3, −3V3, AIN0+, AIN0−, AIN1+, Not applicable Red test points 20-313137 AIN1−, AIN2+, AIN2−, AIN3+, AIN3−, AUX+, AUX−, AVDD1, AVDD2, AVDD4, AVSSX, CONV_SAR, DCLK0/SDO, DCLK1/SDI, EXT_REF, MODE0 to MODE3 A2 Not applicable Coupled inductors, 6.8 µH, 1.2 A, 20% LPD5030-682MRB AD7779_REF, AD7779_VCM, AI0+, Not applicable Straight PCB mount SMB jacks 1-1337482-0 AI0−, AI1+, AI1−, AI2+, AI2−, AI3+, AI3−, AI4+, AI4−, AI5+, AI5−, AI6+, AI6−, AI7+, AI7−, AUXIN+, AUXIN−, J2 ALERT/CS, DCLK2/SCLK, DREGCAP, Not applicable Black test points 20-3131 GND, GND7, GND8, GND9, PGND, XT1, XT2, SYNCIN, SYNC_OUT C1 to C4, C6 to C33, C86, C88, C89 Do not insert Ceramic capacitors, not inserted, 0603 Not applicable C5, C36 to C38, C41, C43, C45, C47, 0.1 µF Capacitors ceramic, 16 V, X7R, 0402 MC0402B104K160CT C48, C50, C52, C53, C56, C60 to C62, C64, C65, C69, C77, C79, C84, C85, C93, C98, C107, C123 C34, C35, C39, C44, C49, C51, C54, C55 1 µF Capacitors, 0402, 1 µF, 6.3 V, X5R 04026D105KAT2A C40, C42, C46 Do not insert 0402 capacitor location Not applicable C57 to C59, C71 to C74 Do not insert Ceramic capacitors, not inserted, 0402 Not applicable C63, C70, C87, C91, C92, C94, C99, C108 10 µF Capacitors, ceramic, 50 V, X5R, 1210 GRM32ER61H106K C66 33 nF SMD capacitor MC0603B333K500CT C67 C68, C80, C81, C95, C96, C117 to 2.2 µF Capacitors, 0603, 2.2 µF, 6.3 V MC0603X225K6R3CT C120 C75, C76, C82 1 nF 50 V, X7R, multilayer ceramic capacitors MC0402B102K500CT C78 22 µF 22 µF, SMD, tantalum, 0805, capacitor TACR226M010XTA C83, C90, C97 Do not insert Ceramic capacitors, 0603 Do not insert C100 56 pF SMD capacitor MC0603N560J500CT C101 47 µF SMD capacitor GRM31CR60J476ME19L C102 4.7 µF SMD capacitor C1608X5R0J475K/0.80 C109, C114 1 µF SMD capacitors C1005X5R1C105K050BC C110 1 µF SMD capacitor GRM188R61C105KA93D C111 1 µF SMD capacitor C1005X5R0J105M050BB C112 39 pF SMD capacitor MC0603N390J500CT C113 27 nF SMD capacitor C0402C273K3RACTU C115 10 µF SMD capacitor C3216X5R1C106M160AA C116 22 µF SMD capacitor GRM21BR60J226ME49L D1 Do not insert Do not insert Not applicable D2 Diode, Zener, 0.5 W, 4.7 V, SOD-123 MMSZ5230B-7-F D3, D7 20 V, 0.5 A Schottky, 0.5 A, 20 V, SOD-123FL MBR0520LT1G D4, D5 Red LED, SMD, red HSMC-C191 D6 Green LED, SMD, green LGQ971 IOVDD, S1, S3, S5, S5'2, S6'2, S7, S7'2, Do not insert Test points, not inserted, keep hole clear of solder Not applicable S8'2, VCM_OUT, VNEG, VPOS J1 Not applicable 20-pin (2 × 10), 0.1" pitch, header M20-9981046 J3 Not applicable Power socket block, 3-way, 3.81 mm MC1.5/3-G-3.81 J4 Not applicable 160-pin, 10 mm, male, VITA 57, connector ASP-134604-01 J5 Not applicable DC power connectors, 2 mm, SMT, power jack KLDX-SMT2-0202-A J6 Do not insert Socket terminal block, pitch 3.81 mm MC 1.5/3-G-3.81

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Reference Designator Value Description Part Number J7 Not applicable 7-way, SSW, 2.54 mm, vertical socket (make sure SSW-107-01-T-S that socket lines up with connector on surfboard) J8, J13 Do not insert 8-pin screw terminal, pitch 3.81 mm, vertical 1727078 J9, J14 Not applicable 8-pin terminal header, pitch 3.81 mm, vertical MC 1,5/ 8-G-3,81 J10 Not applicable 7-way, SIP, 2.54 mm, TH header (make sure that TLW-107-05-G-S header lines up with connector on surfboard) J15 1 × 4-pin Header, vertical, not inserted Not applicable J17 Not applicable Power socket block, 4-way, pitch 3.81mm MC1.5/4-G-3.81 K0 to K15 Not applicable Resistors, 0402, 1%, 0 Ω 0 Ω L1 12 µH Inductor ME3220-123KLB L2, L3 1 µH Inductors ME3220-102MLB MAIN_SUPPLY Not applicable 2-way solder link (use 0 Ω 0603 resistor) Insert in Link Position A Q1 Not applicable MOSFET, N-channel, 30 V, 3.6 A, diode, SOT-23 SI2304DDS-T1-GE3 Q2 Not applicable Transistor, NPN, SOT-23 MMBT3904LT1G R1 to R4, R8 to R13, R16 to R21, R24 to 0 Ω Resistors, 0603, 1%, 0 Ω MC0063W06030R R29, R32 to R37, R40 to R45, R48 to R53, R56 to R61, R64, R65, R111, R112, R121, R129 R5, R6, R14, R15, R22, R23, R30, R31, 1 kΩ Resistors, 1 kΩ, 0.063 W, 1%, 0603 MC0063W060311K R38, R39, R46, R47, R54, R55, R62, R63 R7, R71 to R78, R95 to R103, R105 to 0 Ω Resistors, 0402, 1%, 0 Ω MC00625W040210R R109, R115, R118, R122, R123, R132, R150 R66 to R70, R89, R110, R116, R117, Do not insert Resistors, not inserted, 0402 Not applicable R125 to R128, R146 to R148, R153, R156 to R160, R175 to R179 R79 1 kΩ Resistor, thick film, 1 kΩ, 0402, 63 mW, 1% CRCW04021K00FKED R80, R92 39 kΩ Resistors, 0402, 1%, 39 kΩ MC 0.0625W 0402 1% 39K R81 86.6 kΩ Resistor, 0402, 1%, 86.6 kΩ MC 0.0625W 0402 1% 86K6 R82 to R84, R91, R152 10 kΩ Resistors, 10 kΩ, 0.063 W, 1%, 0402 MC00625W0402110K R85 to R88, R90 10.2 kΩ SMD resistors MC 0.0625W 0402 1% 10K2 R93 4.53 kΩ Resistor, thick film, 4.53 kΩ, 63 mW, 1% CRCW04024K53FKED R94 61.9 Ω Resistor, 0402, 1%, 61.9 Ω MC 0.0625W 0402 1% 61R9 R104 15 Ω Resistor, 15 Ω, 0.063 W, 1%, 0603 MC0063W0603115R R113, R114, R119, R120, R124 Do not insert Resistors, not inserted, 0603 Not applicable R141 5.1 kΩ Resistor, 5.1 kΩ, 0.063 W, 1%, 0402 MC00625W040215K1 R142 2 kΩ Resistor, MC series, 2 kΩ, 62.5 mW, ±1%, 50 V, MC00625W040212K 0402 R143 8.66 kΩ Resistor, 8.66 kΩ, 0.063 W, 1%, 0603 MC0063W060318K66 R144 6.19 kΩ Resistor, thick film, 6.19 kΩ, 0.2 W, 1% ERJP03F6191V R145, R167 17.8 kΩ Resistors, thick film, 17.8 kΩ, 1%, 0603 MCT 0603-50 1% P5 17K8 R149, R155 Do not insert SMD, resistors, 0402 Not applicable R154 0 Ω Resistor, 0402, 1%, 0 Ω MC00625W040210R R162 107 kΩ Resistor, 0603, 107 kΩ, 1% CRCW0603107KFKEA R163 16.2 kΩ Resistor, 0603, 16.2 kΩ 1%, 0.1 W ERJ3EKF1622V R164 64.9 kΩ Resistor, 0603, 64.9 kΩ, 1% CRCW060364K9FKEA R165 14 Ω Resistor, 14 Ω, 0.063 W, 1%, 0603 MC0063W0603114R R166 16.9 Ω Resistor, 16.9 Ω, 0.063 W, 1%, 0603 MC0063W0603116R9 R168 10 kΩ Resistor, thick film, 10 kΩ, 0.1 W, 1% RC0603FR-0710KL R169 17.4 kΩ Resistor, 0603, 17.4 kΩ, 1% CRCW060317K4FKEA R170 3.74 kΩ Thick film resistor, 3. 3.74 kΩ, 100 mW, 1% CRCW06033K74FKEA R171 10 kΩ Resistor, thick film, 10 kΩ, 0.1 W, 1% RC0603FR-0710KL R172 3.57 kΩ Resistor, 0603, 3.57 kΩ, 1% CRCW06033K57FKEA R173 10 kΩ Resistor, thick film, 10 kΩ, 0.1W, 1% RC0603FR-0710KL R174 17.4 kΩ Resistor, 0603, 17.4 kΩ, 1% CRCW060317K4FKEA

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Reference Designator Value Description Part Number R180 to R184, SL7 0 Ω Resistors, 0402 1%, 0 Ω MC00625W040210R SL1, SL2, SL9 to SL17, SL24, SL25 Not applicable 3-way link option, insert 0 Ω in Position A MC 0.063W 0603 0R SL3 to SL6, SL19, SL20, SL22, SL23 Not applicable 2-way resistor link option (insert in Position A) MC 0.063W 0603 0R SL8, SL18, SL21 Not applicable 2-way resistor link option, default Position A MC 0.063W 0603 0R SLP1 to SLP6 Not applicable 2-way solder link (use 0 Ω, 0603 resistor) Insert in Link Position A U1 Not applicable 8-channel, 24-bit, simultaneous sampling ADC AD7 770ACPZ/AD7779ACPZ U2 Not applicable 2.5 V reference ADR441BRZ U3 Not applicable Linear regulator, 3.3 V, ultralow noise, CMOS ADP7118ACPZN-3.3 U5 Not applicable −28 V, −200 mA, low noise, linear regulator ADP7182ACPZ U6 Do not insert 16-channel level shifter SN74LVCH16T245 U7 Not applicable Quad voltage monitor and sequencer ADM1185ARMZ-1 U8 Not applicable IC, SM, dual low noise op amp, ADA4896, MSOP-8 ADA4896-2ARMZ U9 Not applicable IC, EEPROM, 2 kb, 400 kHz, TSSOP-8 M24C02-WDW6TP U10 Not applicable 1 A/0.6 A dc-to-dc switching regulator with ADP5070ACPZ positive and negative outputs U11 Not applicable 8-channel multiplexer ADG707BRUZ U12 Not applicable Operational amplifier AD8659ACPZ-R7 U13 Not applicable Linear regulator, 3.3 V, ultralow noise, CMOS ADP7118ACPZN-3.3 U14 Not applicable Linear regulator, adjustable voltage, ultralow ADP7118ACPZN noise, CMOS U15 Not applicable −28 V, −200 mA, low noise, linear regulator ADP7182ACPZ Y1 8.192 MHz 8.192 MHz crystal, 12 pF, SMD AA-8.192MAGE-T Y2 8.192 MHz Oscillator, SG-210 series, 8.192 MHz SG-210STF 8.1920ML

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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