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Serial Communication Interface

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Serial Communication Interface Author: Peter Flores Note: Red = not implemented Serial Communication Interface 1. General Information The Serial Communication Interface (SCI) is a universal asynchronous receiver transmitter. It uses a standard non-return-to-zero (NRZ) format which is not inherently self-synchronizing. The baud rate is programmable to synchronize capturing and sending data. Both the transmitter and receiver are double-buffered to handle back-to-back characters. The transmitter and receiver are independent, but always use same baud rate and data format. 2. Data Format The serial communication will exhibit the following format. A frame includes start bit, data bits and a stop bit. • When idle, line will be logic one. • A start bit, logic zero, indicates start of a frame. • Data (8 or 9 bits) is transferred LSB first. • A stop bit, logic one, indicates end of a frame. The above frame format pertains to transmitting and receiving. The word length is controlled by the M bit in the SCCR1 explained later. 3. Transmitting At the center of the transmitter is the transmit shift register. Data gets to this register from the write-only transmit data register (TDR). A write to the SCI Data Register (SCDR) will load the TDR. Whenever the shift register is loaded, a 0 is loaded as the LSB for the start bit and a 1 is loaded to the MSB for the stop bit. If the M-bit is set (9-bit data character format selected), the ninth data bit comes from the T8 bit in SCCR1. The TDRE and TC flags are controlled by the transmit block and can be read anytime by software. 4. Receiving The heart of the receiver is the receive shift register. After receiving 8 or 9 bits of data (determined by the M-bit) and detecting the stop bit, the data is transferred to the RDR and the RDRF flag is set. If a 0 is read where the stop bit is expected, the Framing Error (FE) flag is set. When a character is ready to be transferred to the RDR but the previous character has not yet been read, an overrun condition occurs and the Overrun (OR) Flag is set. During an overrun condition, the character in the shift register is not loaded to the RDR, and therefore it is lost. 5. SCI Registers There are seven accessible registers associated with the SCI. SCCR1, SCCR2, BAUD, CPBH, CPBL control the SCI. SCDR is the data register, and SCSR is the status register. CPBH and CPBL, which are not addressable in the HC11, allow for greater control of the baud rate. Note: The BAUD register works as it does in the HC11, and changes to the BAUD register will update the CPBH and CPBL registers. Changes to BRSH and/or CPBL will not change the BUAD register. SCCR1 - Serial Communications Control Register 1 Address: $102C Bit: 7 6 5 4 3 2 1 0 Read: R8 0 0 0 0 T8 M WAKE Write: Reset: U U 0 0 0 0 0 0 U = Unaffected R8 - Receive Data Bit 8 If M bit is set, the MSB of the receive data character is transferred here as the data is shifted in. This bit acts as a ninth bit for the RDR. T8 - Transmit Data Bit 8 If M bit is set, T8 acts as a ninth bit for the TDR. Bit 5 - Not Implemented Always read 0 M - Mode (length of character data) 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit Wake - Wakeup by Address Mark/Idle 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mask (most significant data bit set) Bits [2:0] - Not Implemented Always read 0 SCCR2 - Serial Communications Control Register 2 Address: $102D Bit: 7 6 5 4 3 2 1 0 Read: TIE TCIE RIE ILIE TE RE RWU SBK Write: Reset: 0 0 0 0 0 0 0 0 TIE — Transmit Interrupt Enable Bit 0 = TDRE interrupts disabled (software polling mode) 1 = SCI interrupt requested when TDRE is set to 1 TCIE — Transmit Complete Interrupt Enable Bit 0 = TC interrupts disabled (software polling mode) 1 = SCI interrupt requested when TC is set to 1 RIE — Receive Interrupt Enable Bit 0 = RDRF and OR interrupts disabled (software polling mode) 1 = SCI interrupt requested when either RDRF or OR is set to 1 ILIE — Idle-Line Interrupt Enable Bit 0 = IDLE interrupts disabled (software polling mode) 1 = SCI interrupt requested when IDLE is set to 1 TE — Transmit Enable Bit 0 = SCI transmitter disabled 1 = SCI transmitter enabled RE — Receive Enable Bit 0 = SCI receiver disabled 1 = SCI receiver enabled RWU — Receiver Wakeup Bit 0 = Normal SCI receiver operation (wakeup feature not enabled) 1 = Places the SCI receiver in a standby mode where receiver-related interrupts are inhibited until some hardware condition is met to wake up the sleeping receiver. BAUD - Baud Rate Register Address: $102B Bit: 7 6 5 4 3 2 1 0 Read: 0 0 SCP1 SCP0 0 SCR2 SCR1 SCR0 Write: Reset: 0 0 0 0 0 U U U U = Unaffected SCP1-SCP0 — SCI Baud Rate Prescaler Select Bits Add Tables!!! CPBH - Clocks Per Bit High Address: $1040 Bit: 7 6 5 4 3 2 1 0 Read: CPB15 CPB14 CPB13 CPB12 CPB11 CPB10 CPB09 CPB08 Write: Reset: U U U U U U U U U = Unaffected CPBL - Clocks Per Bit Low Address: $1041 Bit: 7 6 5 4 3 2 1 0 Read: CPB07 CPB06 CPB05 CPB04 CPB03 CPB02 CPB01 CPB00 Write: Reset: U U U U U U U U U = Unaffected CPB15-CPB0 — Clocks Per Bit Control Bits These bits control the number of clock cycles that a bit should be held when transmitting or read when receiving. CPB = Clock Freq/Baud Rate This register can be set directly (will not affect BAUD register) or will be updated whenever the BAUD register is loaded. SCDR - Serial Communication Data Register Address: $102F Bit: 7 6 5 4 3 2 1 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: U U U U U U U U U = Unaffected The SCDR is actually two registers. The TDR is a write-only register that is accessed with a write to the SCDR. Data in the TDR will be transferred to the shift-out register and sent out on the tx line. The RDR is a read-only register that is accessed with a read of the SCDR. When a character is read on the rx line it is transferred from the shift-in register to the RDR. SCSR - Serial Communication Status Register Address: $102E Bit: 7 6 5 4 3 2 1 0 Read: TDRE TC RDRF IDLE OR NF FE 0 Write: Reset: 1 1 0 0 0 0 0 0 TDRE — Transmit Data Register Empty 0 = Not empty; data that was previously written to the SCDR has yet to be transferred to the shift register 1 = SCDR is ready to be written to When preparing to write to the SCDR, this bit should be checked to ensure the TDR does not contain unsent data. Since the SCI is double-buffered, the TDR holds the next character to be sent while the shift register is sending the current character. The TDRE flag is cleared by a write to the SCDR and cleared when this data is transferred to the shift register. A write to the SCDR while TDRE is 0 will overwrite the SCDR and lose the previous content. RDRF — Read Data Register Full 0 = Not full; no new data since last read of SCDR 1 = A character was received and transferred from the receive shift register to the parallel RDR. This is the normal indication that a character has been received and is ready to read from the SCI. The NF, FE, and OR bits provide additional information about the character in the SCDR. Software should check RDRF, NF, FE, and OR for any error in the reception (RDRF should be set and the others cleared for valid data). The RDRF is cleared by a read to SCDR. If set, NF and FE flags will be cleared at this time also. OR — Overrun Error Bit 0 = No overrun error 1 = Indicates that another character was serially received and was ready to be transferred to the SCDR, but the previously received character was not yet read In an OR condition, the character that caused the OR is lost, and the character currently in the SCDR is not disturbed. The NF and FE status bits are associated with the normally received character in the SCDR (never the character that caused an OR). The OR flag is cleared by reading SCSR. IDLE — Idle-Line Detect Bit 0 = The RxD line is either active now or has never been active since IDLE was last cleared. 1 = The RxD line has become idle. OR — Overrun Error Bit 0 = No overrun error 1 = Indicates that another character was serially received and was ready to be transferred to the SCDR, but the previously received character was not yet read NF — Noise Flag 0 = No noise detected during reception of the character in the SCDR 1 = Data recovery logic detected noise during reception of the character in the SCDR. FE — Framing Error Bit 0 = No framing error detected 1 = A framing error was detected for the character in the SCDR..
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