Microcontroller Systems Engineering Science 2Nd Year A2 Lectures

µcontroller systems 1 / 43

Microcontroller Systems

Engineering Science 2nd year A2 Lectures

Prof David Murray

[email protected] www.robots.ox.ac.uk/∼dwm/Courses/2CO

Michaelmas 2014 µcontroller systems 2 / 43

Lecture 2 The CPU, Instruction Fetch & Execute

Introduction A Bog Standard Architecture The ﬂow of information Starting the processing: Fetching an instruction A few instructions Executing an instruction µcontroller systems 3 / 43 At the end of the ﬁrst lecture ...

... we introduced the von Neumann architecture

we suggested that special “instruction” data might be read from a memory into the data section, then passed to the control section change the transfer function of the data section.

In this lecture we see that idea realized in the architecture for a simple central processing unit (CPU).

Rather than introduce individual components one by one, we’ll dive in at the deep end and revealing our Bog Standard Architecture. µcontroller systems 4 / 43 Our Bog Standard Architecture

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU The CPU contains CPU connected to Memory registers MBR,AC,IR,MAR,PC,SP by an arithmetic logic unit (ALU) an address bus a control unit (CU) a data bus internal data pathways µcontroller systems 5 / 43 CPU Registers

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

MBR The Memory Buffer Register stores information that is being sent to, or received from, the memory along data bus. AC The Accumulator is used to store data that is being worked on by the ALU. The key register in the data section of the cpu. µcontroller systems 6 / 43 CPU Registers

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

MAR The Memory Address Register is used to store the address to access memory. PC The Program Counter holds the address in memory of the next program instruction. The PC is a register & counter. SP The Stack Pointer hold the address of part of main memory used for temporary storage µcontroller systems 7 / 43 CPU Registers CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

IR If the data read from memory is an instruction it gets moved to the Instruction Register. It has two parts: IR (opcode) The most signiﬁcant bits of the instruction tell the cpu what to do. It is decoded by the CU. IR (address) The least signiﬁcant bits are actually data. They get moved to IR (address). They usually form all or part of an address for later use in the MAR. µcontroller systems 8 / 43 Register types Registers MBR, MAR, AC, IR are just row of D-type latches sharing a common CLK input providing temporary storage on the CPU. Because these registers output onto buses they have tri-state buffers are connected to a single input OE (Output Enable). Here they are falling edge-triggered (inverter on the CLK input).

D7 D6 D0

DDQDQQ

CLK OE

O7 O6 O0

The PC can be incremented like a counter, or loaded like a register. If INCpc=1, the clock pulse increments, but if INCpc=0 it loads. The SP can be incremented, decremented, or loaded like a register. µcontroller systems 9 / 43 Units in the CPU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

CU The Control Unit is responsible for timing the register transfers required to fetch and execute each instruction.

It has a number of control lines coming out of it, which transmit CSL and CSP levels and pulses to the various registers, ALU, etc µcontroller systems 10 / 43 Units in the CPU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

ALU The Arithmetic Logic Unit is responsible for bit operations on data held in the AC and MBR. Contains full adders, logical AND-ers and OR-ers, etc. Status Collection of 1bit flags — Carry C, Overflow V, negative N, and zero Z — that indicate the outcome of operations that the ALU has just carried out. The flags are monitored by the CU. µcontroller systems 11 / 43 Data bus & data register widths

CPU MAR Address Bus PC SP Memory INCpc/LOADpc Data Bus: While PCs use CLKmem 32 or 64 bits, IR IR(opcode) IR(address) MBR Data Bus microcontrollers have data AC bus widths of 4 bits, 8-bits, CU Status 16-bits and 32-bits. ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

Let’s assume that the memory is 16 bits or 2 Bytes wide and that the data bus is also 16 bits wide.

The MBR and AC registers on the data side of the CPU will therefore be 16 bits wide µcontroller systems 12 / 43 Address bus & register widths Address Bus: n n lines can address 2 CPU MAR Address Bus locations. PC SP Memory INCpc/LOADpc Intel 8086 (1979): n = 20 CLKmem IR Pentium (2009): IR(opcode) IR(address) MBR Data Bus n = 36 − 40. AC

Microcontrollers haves CU Status ALU smaller main memories, SETalu Control Lines and n = 18 (≡ 256k to Registers, ALU, Memory, etc Outside the CPU locations) is largest. But it is convenient here (i) to have different numbers on the address and data side, and (ii) to keep things in multiple of 8

Let’s assume a 24 bit address bus

⇒The PC, SP, and MAR in our cpu will therefore be 24 bits wide. µcontroller systems 13 / 43 Width of the Instruction Register

The IR (opcode) part CPU MAR Address Bus should be wide enough to PC SP Memory INCpc/LOADpc take the largest opcode. CLKmem IR IR(opcode) IR(address) MBR We will assume the opcode Data Bus is a ﬁxed 8 bits wide, AC

allowing 256 different CU Status ALU instructions — which is SETalu Control Lines plenty. to Registers, ALU, Memory, etc Outside the CPU

The IR (address) part has to have the same width as the address bus, 24 bits. So the whole IR is 32 bits wide.

It is however fed from the internal data bus which is only 16 bits wide in our architecture. We will return to solve this conundrum later. µcontroller systems 14 / 43 Brief introduction to the Main memory The main memory does not reside in the cpu chip but is connected to 24bit Address Contents the cpu via an external 0xFFFFFF 0x3FC9 data bus address bus, and 4 0x01FF 3 0x9A76 control bus (not shown yet). 2 0x0001 1 0x0000 The memory will comprise mostly 0x000000 0x3FC9 random access memory (RAM) 16 bits wide with some additional read-only memory (ROM) to help the ma- chine start up.

The address bus has been chosen to be 24 bits wide, so the address space is from 0x0 to (224 − 1) or 0xFFFFFF in hex.

The data bus is here 16 bits ≡ 2 B wide, and so too are the contents. µcontroller systems 15 / 43 Memory Trivia ... When calculating address space sizes, remember that 210 = 1024. ⇒n = 10, 20, 30 lines ≡ 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory × Width in Bytes. ♣ What is the maximum size of our memory? ♣ What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.) ♣ Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex?

Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary 1100 0000 1010 0001 0000 0011 0x µcontroller systems 16 / 43 Memory Trivia When calculating address space sizes, remember that 210 = 1024. ⇒n = 10, 20, 30 lines ≡ 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory × Width in Bytes. ♣ What is the maximum size of our memory? 32 MB ♣ What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.)2 16 − 1 = 65535 ♣ Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex?

Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary 1100 0000 1010 0001 0000 0011 0x C 0 A 1 0 3 µcontroller systems 17 / 43 Notation for reading, writing

Memory is just a large CPU MAR Address Bus PC SP Memory collection of registers, each INCpc/LOADpc CLKmem

with its own address which IR IR(opcode) IR(address) MBR is selected by the number Data Bus in the MAR AC

CU Status Reading and writing ALU SETalu Control Lines involves register transfers. to Registers, ALU, Memory, etc Outside the CPU

To read from memory the register transfer is MBR←hMAR i read from memory into MBR To write to memory the rt is hMAR i ←MBR write into memory

hMAR i means the memory location addressed by the MAR µcontroller systems 18 / 43 OK ... What are we trying to do?

With the structure of registers, units, memory and buses wired up and assuming our program of instructions is stored in memory we remind ourselves that the overall aim is ...

to work through the program by repeatedly (until we reach a halt) Fetching the next instruction from memory Decoding it — that is, ﬁguring out which instruction it is Executing that instruction

These three will involve little more than moving words of data from memory to registers, and between registers, sometimes passing data through the ALU, and then stufﬁng it back into the memory all in some nicely ordered sequence. µcontroller systems 19 / 43 OK ... What are we trying to do?

A useful analogy is that we are “playing trains" with words of information.

The control unit issues the proper sequence of 1 Levels, to establish the route from source register to destination register 2 Pulses, to send the word to its destination µcontroller systems 20 / 43 Fetching an instruction To start processing, the cpu needs to fetch the next instruction from the main memory. At any time, the PC holds the address of the next program instruction in memory. So the very ﬁrst step is Copy the PC into the memory address register: MAR←PC (this leaves the PC unaltered)

Now read the memory MBR←hMAR i

Now copy the instruction to the IR IR←MBR At the same time, we do a touch of housekeeping. The next instruction is likely to be in the next highest memory location, so Increment the program counter! PC←PC+1 µcontroller systems 21 / 43 Summary of instruction fetch

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 1. MAR←PC 2. MBR←hMAR i 3. IR←MBR; PC←PC + 1 4. Then decode opcode µcontroller systems 21 / 43 Summary of instruction fetch

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 1. MAR←PC 2. MBR←hMAR i 3. IR←MBR; PC←PC + 1 4. Then decode opcode µcontroller systems 22 / 43 A small instruction set LDA, etc, are assembler language mnemonics.

Inst Overall RT Opcode Meaning HALT 00000000 Stop the clock LDA x AC←h x i 00000001 Load AC with contents of mem address x STA x h x i ←AC 00000010 Store AC in memory at address x ADD x AC←AC + h x i 00000011 Add mem contents at x to AC AND x AC =AC ∧ h x i 00000100 Logical and ... JMP x PC←x 00000101 Jump to instruction at address x BZ x if Z=1 PC←x 00000110 if Z-ﬂag is set then jump NOT AC←AC 00000111 Two’s complement the AC SHR AC←RShift(AC) 00001000 Shift the AC 1bit to right

There is no universal architecture ⇒there is no standard set You do not have to learn any speciﬁc assembler language, but you should feel comfortable with the interpretation of any. µcontroller systems 23 / 43 Instruction execution: LDA x

Inst Overall RT Opcode Meaning LDA x AC←h x i 00000001 Load AC with contents of mem address x

During the instruction fetch the opcode is transferred to the IR (opcode); and the operand x is transferred to IR (address).

The operand is data that is bound into the instruction — 6 instructions in the small set have operands.

The overall effect of LDA x is AC←hxi µcontroller systems 24 / 43 Instruction execution: LDA x

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 10. MAR←IR (address) 11. MBR←hMAR i 12. AC←MBR; →(Sfetch) µcontroller systems 24 / 43 Instruction execution: LDA x

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 10. MAR←IR (address) 11. MBR←hMAR i 12. AC←MBR; →(Sfetch) µcontroller systems 24 / 43 Instruction execution: LDA x

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 10. MAR←IR (address) 11. MBR←hMAR i 12. AC←MBR; →(Sfetch) µcontroller systems 25 / 43 Notes

LDA x 10. MAR←IR (address) 11. MBR←hMAR i 12. AC←MBR; →(Sfetch)

1 No computation has be been done by this instruction! Information has been moved around from memory to accumulator, but not altered. The only part of the cpu that can alter data is the ALU. 2 For reasons that become clear later, we have given the execution phase an RTL starting step of 10.

3 →(Sfetch) means goto the start of the next fetch. As the instruction fetch started at RTL step 1, →(Sfetch) could be written as →(1). µcontroller systems 26 / 43 LDA x — Fetch and Execute

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 1. MAR←PC 2. MBR←hMAR i 3. IR←MBR; PC←PC + 1 4. Then decode opcode 10. MAR←IR (address) 11. MBR←hMAR i 12. AC←MBR; →(Sfetch) µcontroller systems 26 / 43 LDA x — Fetch and Execute

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

We learned that the elemental fi in O = fi (I) are instructions We learned that instructions have 3 phases — fetch, decode and execute Instructions always have an opcode and (often) an operand That a binary opcode can be referred to by an assembler language mnemonic Inst Overall RT Opcode Meaning HALT 00000000 Stop the clock LDA x AC←h x i 00000001 Load AC with contents of mem address x STA x h x i ←AC 00000010 Store AC in memory at address x ADD x AC←AC + h x i 00000011 Add mem contents at x to AC AND x AC =AC ∧ h x i 00000100 Logical and ... JMP x PC←x 00000101 Jump to instruction at address x BZ x if Z=1 PC←x 00000110 if Z-ﬂag is set then jump NOT AC←AC 00000111 Two’s complement the AC SHR AC←RShift(AC) 00001000 Shift the AC 1bit to right The overall RT in the execute phase has to be broken down into a set of actual RTs. µcontroller systems 28 / 43 LDA x — Fetch and Execute

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

In the example, the instruction is found in memory location 2, and the instruction itself is LDA 5. Memory ? 5 00000010 00001111 MAR 4 don’t care 2 3 don’t care PC 2 00000001 00000101 1 don’t care 0 don’t care

IR(opcode) IR(address) ?? ? MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

In the example, the instruction is found in memory location 2, and the instruction itself is LDA 5. Memory 2 5 00000010 00001111 MAR 4 don’t care 2 3 don’t care PC 2 00000001 00000101 1 don’t care 0 don’t care

IR(opcode) IR(address) ?? ? MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

IR(opcode) IR(address) ?? 00000001 00000101 MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

In the example, the instruction is found in memory location 2, and the instruction itself is LDA 5. Memory 2 5 00000010 00001111 MAR 4 don’t care 3 3 don’t care PC 2 00000001 00000101 1 don’t care 0 don’t care

IR(opcode) IR(address) 00000001 00000101 00000001 00000101 MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

In the example, the instruction is found in memory location 2, and the instruction itself is LDA 5. Memory 5 5 00000010 00001111 MAR 4 don’t care 3 3 don’t care PC 2 00000001 00000101 1 don’t care 0 don’t care

IR(opcode) IR(address) 00000001 00000101 00000001 00000101 MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

IR(opcode) IR(address) 00000001 00000101 00000010 00001111 MBR LDA x So, MAR<−IR(address) MBR<−M ? AC<−MBR AC µcontroller systems 29 / 43 Example of LDA x fetch and execute

IR(opcode) IR(address) 00000001 00000101 00000010 00001111 MBR LDA x So, MAR<−IR(address) MBR<−M 0x020F (or 527 decimal) AC<−MBR AC µcontroller systems 30 / 43 STA x (Store AC in memory location x)

Every instruction fetch is the same: reminder ... CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 1. MAR←PC 2. MBR←hMAR i 3. IR←MBR; PC←PC + 1 4. Then decode opcode µcontroller systems 30 / 43 STA x (Store AC in memory location x)

Every instruction fetch is the same: reminder ... CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

Every instruction fetch is the same: reminder ... CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

Every instruction fetch is the same: reminder ... CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 1. MAR←PC 2. MBR←hMAR i 3. IR←MBR; PC←PC + 1 4. Then decode opcode µcontroller systems 31 / 43 Execute STA x (Store AC in memory location x)

Overall effect is hxi←AC the “reverse” of LDA x. CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to NoOP to Registers, ALU, Memory, etc Outside the CPU 13. MAR←IR (address); MBR←AC 14. hMAR i ←MBR; →(Sfetch) (Note: Here we can do 2 transfers at the same time ...) µcontroller systems 31 / 43 Execute STA x (Store AC in memory location x)

Overall effect is hxi←AC the “reverse” of LDA x. CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU 13. MAR←IR (address); MBR←AC 14. hMAR i ←MBR; →(Sfetch) (Note: Here we can do 2 transfers at the same time ...) µcontroller systems 32 / 43 ADD x (Add contents of location x to the AC)

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU This instruction involves the ALU. 15. MAR←IR (address) 16. MBR←hMAR i 17. AC←AC + MBR; →(Sfetch) µcontroller systems 32 / 43 ADD x (Add contents of location x to the AC)

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to ADD to Registers, ALU, Memory, etc Outside the CPU This instruction involves the ALU. 15. MAR←IR (address) 16. MBR←hMAR i 17. AC←AC + MBR; →(Sfetch) µcontroller systems 33 / 43 AND x (AND contents of location x to the AC)

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU This instruction again involves the ALU. 18. MAR←IR (address) 19. MBR←hMAR i 20. AC←AC ∧ MBR; →(Sfetch) µcontroller systems 33 / 43 AND x (AND contents of location x to the AC)

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to AND to Registers, ALU, Memory, etc Outside the CPU This instruction again involves the ALU. 18. MAR←IR (address) 19. MBR←hMAR i 20. AC←AC ∧ MBR; →(Sfetch) µcontroller systems 34 / 43 JMP x (Unconditional branch)

CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem Memory IR opcode operand x IR(opcode) IR(address) MBR Data Bus AC opcode operand Loc+1 opcode operand Loc CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU

JMP x jumps or branches unconditionally to instruction at x 21. PC←IR (address); →(Sfetch)

PC always incremented during the fetch cycle ...... but then overwritten with x µcontroller systems 35 / 43 BZ x “Branch if Zero” jumps if the Z ﬂag is 1. Yes, there are BNZ, BN, BNN, BV, BNV, BC, BNC instructions too! 22. →(Z)/(Sfetch) 23. PC←IR (address); →(Sfetch) CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

Z flag CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU µcontroller systems 35 / 43 BZ x “Branch if Zero” jumps if the Z ﬂag is 1. Yes, there are BNZ, BN, BNN, BV, BNV, BC, BNC instructions too! 22. →(Z)/(Sfetch) 23. PC←IR (address); →(Sfetch) CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU µcontroller systems 36 / 43 NOT

NOT complements (inverts) the contents of the AC. An ALU operation, so we need a level to conﬁgure the ALU. 24. AC←AC; →(Sfetch) CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to CoMPlement to Registers, ALU, Memory, etc Outside the CPU µcontroller systems 37 / 43 SHR

SHR RightShifts the contents of the AC. An ALU operation, so we need a level to conﬁgure the ALU. 25. AC←RightShiftAC; →(Sfetch) CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem

IR IR(opcode) IR(address) MBR Data Bus AC

CU Status ALU

SETalu Control Lines to RightSHift to Registers, ALU, Memory, etc Outside the CPU µcontroller systems 38 / 43 Decoding the opcode

Earlier on, when discussing the Instruction Fetch, we IR(opcode) wrote 8 4. Then decode opcode Suppose we have hardware — see the picture that outputs LDA=1 and STA=0, ADD=0, etc, when the opcode is LDA, and similarly for other opcodes. AND ADD STA LDA HALT What’s this? We could write the the decoding phase using RTL’s conditional goto: Decoding (this is RTL) 4. →(LDA,STA,ADD,AND, ..., SHR,HALT)/(10,13,15,18,...,25,99)

We’ll see all the hardware to do this soon.

But now let’s use decoding to solve a problem we had with the IR ... µcontroller systems 39 / 43 Using decoding to solve a conundrum In our standard architecture, the MBR and data bus are 16 bits wide. Hence, IR ←MBR can only supply the 8 bit opcode with an 8 bit operand, like this

MAR Memory Loc+1 Loc

IR bits (23−16) bits (15−8) bits (7−0) MBR Data Bus IR(opcode) IR(address)

If operands were only 8 bits long, we could only access 256 of our 224 addresses, which is useless!

How can we ﬁll the operand up to its full 24 bits? µcontroller systems 40 / 43 Make an additional read of memory ...

Those opcodes that require a full length operand can make an additional read of memory

MAR Memory Loc+1 Loc

IR bits (23−16) bits (15−8) bits (7−0) MBR Data Bus IR(opcode) IR(address)

This comes after the opcode is decoded (obviously!) but before the execution.

It would pull in an extra 2 Bytes. µcontroller systems 41 / 43 The RTL to make this work

In our set of opcodes, LDA, STA, ADD, AND, JMP, and BZ require an extra read to obtain their 3 Byte operands.

The Fetch and Decoding phases become ...

Instruction fetch with extra memory read after ﬁrst decode 1. MAR←PC 2. MBR←hMAR i 3. IR (opcode) and IR (bits 7...0 of address) ←MBR; PC←PC + 1 4. →(NOT,SHR,...)/(24,25,...) //Ie, all that don’t need extra 5. MAR←PC 6. MBR←hMAR i 7. IR [23:8] ←MBR; PC←PC + 1 8. →(LDA,STA,...)/(10,13,...) //Ie, all that do need extra µcontroller systems 42 / 43 Having sorted that out ...

The detail of this step is often missed out in text books, and it is assumed that the fetch (lines 1-3) provides an operand of full length.

We too will neglect the problem — unless explicitly asked to worry about it! µcontroller systems 43 / 43 Summary: In lecture 2 we have ...

... described the CPU in terms of its data registers and control unit, the alu and memory.

... learned how an instruction is fetched from memory, and how its opcode reaches the control unit

... seen the execute phases of number of different instructions

... seen how the fetch and executes are deﬁned (for the most part) by a succession of register transfers