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Microcontroller Systems Engineering Science 2Nd Year A2 Lectures

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Microcontroller Systems Engineering Science 2Nd Year A2 Lectures µcontroller systems 1 / 43 Microcontroller Systems Engineering Science 2nd year A2 Lectures Prof David Murray [email protected] www.robots.ox.ac.uk/∼dwm/Courses/2CO Michaelmas 2014 µcontroller systems 2 / 43 Lecture 2 The CPU, Instruction Fetch & Execute Introduction A Bog Standard Architecture The flow of information Starting the processing: Fetching an instruction A few instructions Executing an instruction µcontroller systems 3 / 43 At the end of the first lecture ... ... we introduced the von Neumann architecture we suggested that special “instruction” data might be read from a memory into the data section, then passed to the control section change the transfer function of the data section. In this lecture we see that idea realized in the architecture for a simple central processing unit (CPU). Rather than introduce individual components one by one, we’ll dive in at the deep end and revealing our Bog Standard Architecture. µcontroller systems 4 / 43 Our Bog Standard Architecture CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU The CPU contains CPU connected to Memory registers MBR,AC,IR,MAR,PC,SP by an arithmetic logic unit (ALU) an address bus a control unit (CU) a data bus internal data pathways µcontroller systems 5 / 43 CPU Registers CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU MBR The Memory Buffer Register stores information that is being sent to, or received from, the memory along data bus. AC The Accumulator is used to store data that is being worked on by the ALU. The key register in the data section of the cpu. µcontroller systems 6 / 43 CPU Registers CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU MAR The Memory Address Register is used to store the address to access memory. PC The Program Counter holds the address in memory of the next program instruction. The PC is a register & counter. SP The Stack Pointer hold the address of part of main memory used for temporary storage µcontroller systems 7 / 43 CPU Registers CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines to Registers, ALU, Memory, etc Outside the CPU IR If the data read from memory is an instruction it gets moved to the Instruction Register. It has two parts: IR (opcode) The most significant bits of the instruction tell the cpu what to do. It is decoded by the CU. IR (address) The least significant bits are actually data. They get moved to IR (address). They usually form all or part of an address for later use in the MAR. µcontroller systems 8 / 43 Register types Registers MBR, MAR, AC, IR are just row of D-type latches sharing a common CLK input providing temporary storage on the CPU. Because these registers output onto buses they have tri-state buffers are connected to a single input OE (Output Enable). Here they are falling edge-triggered (inverter on the CLK input). D7 D6 D0 DDQDQQ CLK OE O7 O6 O0 The PC can be incremented like a counter, or loaded like a register. If INCpc=1, the clock pulse increments, but if INCpc=0 it loads. The SP can be incremented, decremented, or loaded like a register. µcontroller systems 9 / 43 Units in the CPU CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines CU Theto Registers,Control ALU, Memory, Unit etc is responsible for timingOutside the the register CPU transfers required to fetch and execute each instruction. It has a number of control lines coming out of it, which transmit CSL and CSP levels and pulses to the various registers, ALU, etc µcontroller systems 10 / 43 Units in the CPU CPU MAR Address Bus PC SP Memory INCpc/LOADpc CLKmem IR IR(opcode) IR(address) MBR Data Bus AC CU Status ALU SETalu Control Lines ALU toThe Registers,Arithmetic ALU, Memory, etc Logic Unit is responsibleOutside forthe bitCPU operations on data held in the AC and MBR. Contains full adders, logical AND-ers and OR-ers, etc. Status Collection of 1bit flags — Carry C, Overflow V, negative N, and zero Z — that indicate the outcome of operations that the ALU has just carried out. The flags are monitored by the CU. µcontroller systems 11 / 43 Data bus & data register widths CPU MAR Address Bus PC SP Memory Data Bus: WhileINCpc/LOADpc PCs use CLKmem 32 or 64 bits, IR microcontrollersIR(opcode) have IR(address) data MBR Data Bus bus widths of 4 bits, 8-bits, AC 16-bits and 32-bits. CU Status ALU SETalu Control Lines Let’s assumeto Registers, that ALU, Memory, thememory etc is 16 bits or 2Outside Bytes the wide CPU and that the data bus is also 16 bits wide. The MBR and AC registers on the data side of the CPU will therefore be 16 bits wide µcontroller systems 12 / 43 Address bus & register widths Address Bus: n lines canCPU address 2n MAR Address Bus locations. PC SP Memory INCpc/LOADpc Intel 8086 (1979): n = 20 CLKmem Pentium (2009):IR IR(opcode) IR(address) MBR n = 36 − 40. Data Bus AC Microcontrollers haves smaller mainCU memories,Status and n = 18 (≡ 256k ALU SETalu locations)Control is largest. Lines to Registers, ALU, Memory, etc Outside the CPU But it is convenient here (i) to have different numbers on the address and data side, and (ii) to keep things in multiple of 8 Let’s assume a 24 bit address bus )The PC, SP, and MAR in our cpu will therefore be 24 bits wide. µcontroller systems 13 / 43 Width of the Instruction Register The IR (opcode)CPU part MAR should be wide enough to Address Bus PC SP Memory INCpc/LOADpc take the largest opcode. CLKmem We will assumeIR the opcode IR(opcode) IR(address) MBR is a fixed 8 bits wide, Data Bus allowing 256 different AC instructions — which is CU Status plenty. ALU SETalu Control Lines The IR (address)to Registers, ALU, part Memory, has etc to have the same widthOutside as the the CPU address bus, 24 bits. So the whole IR is 32 bits wide. It is however fed from the internal data bus which is only 16 bits wide in our architecture. We will return to solve this conundrum later. µcontroller systems 14 / 43 Brief introduction to the Main memory The main memory does not reside in the cpu chip but is connected to 24bit Address Contents the cpu via an external 0xFFFFFF 0x3FC9 data bus address bus, and 4 0x01FF 3 0x9A76 control bus (not shown yet). 2 0x0001 1 0x0000 The memory will comprise mostly 0x000000 0x3FC9 random access memory (RAM) 16 bits wide with some additional read-only memory (ROM) to help the ma- chine start up. The address bus has been chosen to be 24 bits wide, so the address space is from 0x0 to (224 − 1) or 0xFFFFFF in hex. The data bus is here 16 bits ≡ 2 B wide, and so too are the contents. µcontroller systems 15 / 43 Memory Trivia ... When calculating address space sizes, remember that 210 = 1024. )n = 10; 20; 30 lines ≡ 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory × Width in Bytes. | What is the maximum size of our memory? | What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.) | Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex? Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary 1100 0000 1010 0001 0000 0011 0x µcontroller systems 16 / 43 Memory Trivia When calculating address space sizes, remember that 210 = 1024. )n = 10; 20; 30 lines ≡ 1k,1M,1G locations NB! 1k locations does not mean that the memory has size 1kB. The memory size in Bytes is No. of locations with physical memory × Width in Bytes. | What is the maximum size of our memory? 32 MB | What is the largest +ve integer that can be held in it? (Use unsigned arithmetic.)2 16 − 1 = 65535 | Suppose all address lines are zero except A23, A22, A15, A13, A8, A1, and A0. What is the address in hex? Lines A23-A20 A19-A16 A15-A12 A11-A8 A7-A4 A3-A0 Binary 1100 0000 1010 0001 0000 0011 0x C 0 A 1 0 3 µcontroller systems 17 / 43 Notation for reading, writing Memory is just a large CPU MAR collection of registers, each Address Bus PC SP Memory with its ownINCpc/LOADpc address which is selected by the number CLKmem in the MARIR IR(opcode) IR(address) MBR Data Bus Reading and writing AC involves register transfers. CU Status To read from memory the registerALU transfer is SETalu MBR ControlhMAR Linesi read from memory into MBR to Registers, ALU, Memory, etc Outside the CPU To write to memory the rt is hMAR i MBR write into memory hMAR i means the memory location addressed by the MAR µcontroller systems 18 / 43 OK ..
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