A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization Aaron Parsons, Donald Backer, and Andrew Siemion Astronomy Department, University of California, Berkeley, CA
[email protected] Henry Chen and Dan Werthimer Space Science Laboratory, University of California, Berkeley, CA Pierre Droz, Terry Filiba, Jason Manley1, Peter McMahon1, and Arash Parsa Berkeley Wireless Research Center, University of California, Berkeley, CA David MacMahon, Melvyn Wright Radio Astronomy Laboratory, University of California, Berkeley, CA ABSTRACT A new generation of radio telescopes is achieving unprecedented levels of sensitiv- ity and resolution, as well as increased agility and field-of-view, by employing high- performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN 2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware mod- ules containing Field Programmable Gate Array (FPGA) chips. These chips are pro- grammed using open-source signal processing libraries we have developed to be flexible, arXiv:0809.2266v3 [astro-ph] 17 Mar 2009 scalable, and chip-independent. This work reduces the time and cost of implement- ing a wide range of signal processing systems, with correlators foremost among them, and facilitates upgrading to new generations of processing technology.