A Noise-Shaping Algorithm of Multi-Bit DAC Nonlinearities in Complex Bandpass ∆ΣAD Modulators

IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.4 APRIL 2004 792

PAPER Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass ∆ΣAD Modulators

Hao SAN†, Student Member, Haruo KOBAYASHI†a), Member, Shinya KAWAKAMI†, and Nobuyuki KUROIWA†, Nonmembers

SUMMARY This paper presents a technique for improving the SNR (such as sampling speed) over a pair of real bandpass ∆ΣAD and resolution of complex bandpass ∆ΣADCs which are used for wireless modulators. communication systems such as cellular phone, wireless LAN and Blue- In ∆ΣAD modulators, oversampling and noise shap- tooth. Oversampling and noise-shaping are used to achieve high accuracy of a ∆ΣAD modulator. However when a multi-bit internal DAC is used ing techniques are used to achieve high accuracy. When inside a modulator, nonlinearities of the DAC are not noise-shaped and the a single-bit modulator (i.e., internal ADC and DAC are 1- SNR of the ∆ΣADC degrades. For the conversion of complex intermedi- bit) is used to achieve high SNR, higher oversampling ra- ate frequency (IF) input signals, a complex bandpass ∆ΣAD modulator can tio (OSR) is needed which demands higher sampling rate, provide superior performance to a pair of real bandpass ∆ΣAD modulators / of the same order. This paper proposes a new noise-shaping algorithm— and or a high-order filter inside a modulator (as well as implemented by adding simple digital circuitry—to reduce the effects of a high-order digital filter following the ∆ΣAD modulator) nonlinearities in multi-bit DACs of complex bandpass ∆ΣAD modulators. is required which may cause modulator stability problems. We have performed simulation with MATLAB to verify the effectiveness of On the other hand, when a multi-bit ∆Σ modulator is used, the algorithm, and the results show that the proposed algorithm can improve higher resolution can be achieved with lower OSR, and the the SNR of a complex bandpass ∆ΣADC with nonlinear internal multi-bit DACs. stability problems are alleviated [7], [8]. key words: complex bandpass ∆ΣAD modulator, bandpass filter, noise- A multi-bit DAC cannot be made perfect linear, while shaping, ADC, DAC, element rotation, data-weighted averaging, low-IF a 1-bit DAC is inherently linear. Multi-bit DAC nonlinearity receiver is equivalent to errors added directly to the input signal - it is not reduced by noise-shaping, and hence they may degrade 1. Introduction the SNR of the ∆ΣADC. The input and output of a bandpass ∆ΣAD modulator shown in Fig. 1 are given by Recently, research into bandpass ∆ΣADCs has become pop- ular for their applications to RF receivers in wireless com- H(z) 1 1 M(z) = X(z) + E(z) + δ(z) (1) munication systems such as cellular phone, wireless LAN 1 + H(z) H(z) H(z) and Bluetooth [1]–[5]. Shifting the ADC towards the an- H(z) 1 tenna side in the receiver architecture relaxes the require- Y(z) = X(z) + E(z) − δ(z) . (2) 1 + H(z) H(z) ments placed on analog circuits at the expense of more complicated digital circuit, allowing more digital integration of Here the signal part S (z) and the noise part N(z)aredefined analog function on a single chip, and resulting in a cheaper as: system with a higher level of integration. However, ADCs H(z) with high linearity, large dynamic range, bandwidth and S (z):= X(z) 1 + H(z) strong image rejection capabilities are required, and a com- ∆Σ H(z) 1 plex bandpass ADC is one of their candidates. N(z):= E(z) − δ(z) . (3) In communication systems applications using complex 1 + H(z) H(z) intermediate frequency (IF) input signals, image signals From Eq. (3), we see that nonlinearity errors δ(z)ofDAC caused by mismatches between I and Q paths may adversely ff ∆Σ directly appears at output of the modulator without noise- a ect system performance, and a complex bandpass AD shaping, while internal quantization noise E(z)ofADCis modulator [1]–[6] can provide better suppression of image noise-shaped by 1/H(z); this makes it difficult to realize a signals and thus superior performance to a pair of real band- ∆Σ high resolution ADC. pass AD modulators of the same order. Also especially One way to overcome this multi-bit DAC nonlinearity in low-IF receivers, it is known [3] that the complex band- ∆Σ problem is (self-)calibration of the multibit DAC, and an- pass AD modulator relaxes the performance requirement other way is to use signal processing algorithms to noise- Manuscript received June 23, 2003. shape the multi-bit DAC nonlinearities. There are already Manuscript revised September 19, 2003. some algorithms for noise-shaping of multi-bit DAC non- Final manuscript received November 4, 2003. † linearities in bandpass ∆ΣAD modulators, such as dynamic The authors are with the Department of Electronic Engineer- ing, Faculty of Engineering, Gunma University, Kiryu-shi, 376- element matching (DEM) [8] and element rotation (data- 8515 Japan. weighted averaging) [9]. However either of them is for real a) E-mail: k [email protected] bandpass ∆ΣAD modulators (single-input & output only) SAN et al.: A NOISE-SHAPING ALGORITHM OF MULTI-BIT DAC NONLINEARITIES IN COMPLEX BANDPASS ∆ΣAD MODULATORS 793

Fig. 2 A current-steering segmented DAC with 9-level resolution. Here ∆Σ Fig. 1 A bandpass AD modulator and its equivalent block diagram. e0, e1,...e6 and e7 denote current source mismatches. X(z) (Ain) is an analog input, Y(z) (Dout) is a digital output, E(z) is quantization noise of an ADC, and δ(z) is nonlinearity of a DAC. shown in Fig. 1. This paper presents a new algorithm which noise-shapes nonlinearities of multi-bit DACs in a complex (a) bandpass ∆ΣAD modulator which has I, Q inputs and outputs. Adding simple digital circuitry can provide ﬁrst-order complex bandpass noise-shaping of nonlinearities of multi- bit DACs, and improve the SNR of a multi-bit complex bandpass ∆ΣADC. Our simulation results with MATLAB show the proposed method can improve the SNR and reso- (b) ∆Σ lution of complex bandpass ADCs. Fig. 3 (a) Lowpass element rotation architecture. (b) Equivalent block Section 2 reviews DAC nonlinearity noise-shaping al- diagram. gorithms (element rotation methods) for lowpass and highpass modulators with single-input & output, based on [9], [12]. Section 3 describes our proposed DAC nonlinearity Here noise-shaping algorithm for complex bandpass modulators, I := I + I + I + ...+ I /8, and Sect. 4 shows its MATLAB simulation results. Finally 0 1 2 7 + + + ...+ = , Sect. 5 provides conclusion. e0 e1 e2 e7 0 Throughout this paper, we assume, without loss of gen- ∆Σ and ek is the current mismatch part of Ik. When the digital erality, that internal DACs in AD modulators have 9-level input data is m, unit-current-cells of 0, 1, 2,...m − 1areON resolution; their digital input takes the value of 0, 1, 2, ..., in any sample time, and the output voltage V is given by 7, or 8. We also suppose that they are implemented with the out segmented current-steering DAC architecture [14]. Vout = mRI + δ. δ 2. DAC Nonlinearity Noise-Shaping Algorithms in Here is DAC nonlinearity given by Lowpass and Highpass Modulators δ := R(e0 + e1 + e2 + ...+ em−1).

In this section, we will describe element rotation (data- In this case the mismatch effects of e0, e1,...,e7 (or equiva- weighted averaging: DWA) first-order noise-shaping algo- lently DAC nonlinearity δ) to the ADC output cause almost rithms of DAC nonlinearities in (single-input & output) low- flat power spectrum in the entire band. pass and highpass modulators [9], [12], which will be used for the algorithm derivation for complex bandpass modula- 2.2 Lowpass Element Rotation tors in Sect. 3. This subsection explains a lowpass element rotation algo- 2.1 Normal Segmented DAC and Unit Cell Mismatches rithm [12]. Let us consider a circuit in Fig. 3, which consists of a digital lowpass filter (1/(1 − z−1)), a DAC with nonlin- − A normal segmented current-steering DAC with 9-level res- earity of δ(z) and an analog high pass filter (1 − z 1). Then olution in Fig. 2 consists of 8 unit-current-cells and a resis- we have the followings: tor. We denote I for the current of k-th unit-current-cell k 1 (k = 0, 1, 2,...,7). Ideally all currents I (k = 0, 1, 2,...,7) C (z) = C (z)(4) k 2 − −1 1 should be equal, however in practice they can be slightly 1 z = − −1 different due to such as process variation inside an IC chip. C4(z) (1 z ) C3(z)(5) Let C3(z) = C2(z) + δ(z). (6)

Ik := I + ek (k = 0, 1, 2,...,7). Thus the analog output of C4(z)isgivenby IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.4 APRIL 2004 794

Fig. 5 DAC nonlinearity lowpass noise-shaping by an element rotation algorithm when a segmented current-steering internal DAC with 9-level resolution is used. (a) Current-cells in ON state which are ﬁlled in black, when input data are sequentially given by 4, 3, 2, 2, 5,. . . . (b) Simulation result for output spectrum. We see that the DAC nonlinearity power is Fig. 4 A current-steering segmented DAC with 9-level resolution in a noise-shaped (“LP Noise Shaping”) with the element rotation algorithm ring form. while it is not noise-shaped (“No Shaping”) without the algorithm.

−1 C4(z) = C1(z) + (1 − z ) δ(z). (7) 1,...,a + b − 1 in the DAC are ON. However, there are only + − We see that the DAC nonlinearity δ(z) is first-order noise- 8 unit-current-cells in the actual DAC, and a b 1 can shaped by 1 − z−1. Note that Eqs. (4), (5), (6) are equivalent be larger than 7. Then for the actual implementation of the to the following: above structure in the lowpass element rotation algorithm, the unit-current-cells are arranged in a ring form, and in this + = + + C2(n 1) C2(n) C1(n 1) (8) case the unit-current-cells of mod8(a−1), mod8(a), mod8(a+ ,..., + − C4(n + 1) = C3(n + 1) − C3(n)(9)1) mod8(a b 1) are ON. The rigorous description of the lowpass element rotation algorithm is as follows: C3(n) = C2(n) + δ(n). (10) • = = ∆Σ Suppose that the input data C1(n) cn (where n If we replace a multi-bit DAC in a lowpass AD modula- , , , ... tor with the circuit in Fig. 3, its DAC nonlinearity is noise- 0 1 2 3 ). • c P n + shaped. However, in practice this structure cannot work Turn on n unit-current-cells of mod8( ( ) 1), P n + P n + ... P n + c . properly; suppose that C (n) is always a positive number, mod8( ( ) 2), mod8( ( ) 3), ,mod8( ( ) n) 1 • n + P n + = P n + say 2, then the DAC input C (n) becomes infinite (out-of- Set the pointer at time 1to ( 1) mod8( ( ) 2 c DAC-input-range) as n increases. Then the equivalent im- n). plementation (called an element rotation algorithm) has to Figure 5(a) shows the unit-current-cells in ON state which be considered. are filled in black when input data are sequentially given by First we modify the segmented current-steering DAC 4, 3, 2, 2, 5. . . When the input is 4 at time n, unit-current- as follows: cells of 0, 1, 2, 3 are ON. When it is 3 at time n + 1, those • of 4, 5, 6 are ON, and when it is 2 at time n + 2, those of Arrange unit-current-cells of the DAC in a ring form as = + showninFig.4. 7, (mod8(8) )0 are ON. Also when it is 2 at time n 3, = = • Let the DAC have a pointer to show which unit-current- those of (mod8(9) )1, (mod8(10) )2 are ON. By select- cell should be selected next sample time, and let the ing unit-current-cells in this way (i.e., always clockwise), pointer be P(n) at time n. mismatches among unit-current-cells are first-order lowpass noise-shaped [11]–[13]. Figure 5(b) shows the noise-shape Suppose that we have infinite number of unit-current-cells, effect by MATLAB simulation. The ADC output power = + = ≤ ≤ and C2(n) a, C1(n 1) b (where 0 b 8). Then the spectrum contributed by DAC nonlinearities in the signal unit-current-cells of 0, 1,...,a + b − 1intheDACareON, band is flat with a normal segmented current-steering DAC, and it follows from Eqs. (8) and (10) that however it is noise-shaped when this algorithm is incorporated. C3(n + 1) = (a + b)RI + R(e + e + e + ...+ e + − ). 0 1 2 a b 1 2.3 Highpass Element Rotation Since This subsection explains a highpass element rotation algo- C (n) = aRI + R(e + e + e + ...+ e − ), 3 0 1 2 a 1 rithm [9]. Let us consider a circuit in Fig. 6, which consists −1 the analog output C4(n + 1) is given by of a digital highpass filter (1/(1 + z )), a DAC with nonlinearity of δ(z) and an analog lowpass filter (1+z−1). Then we C (n + 1) = C (n + 1) − C (n) 4 3 3 have the followings: = bRI + R(ea−1 + ea + ea+1 + ...+ ea+b−1), 1 − , , + D (z) = D (z) (11) which corresponds that the unit-current-cells of a 1 a a 2 1 + z−1 1 SAN et al.: A NOISE-SHAPING ALGORITHM OF MULTI-BIT DAC NONLINEARITIES IN COMPLEX BANDPASS ∆ΣAD MODULATORS 795

(a)

Fig. 7 Highpass noise-shaping of DAC nonlinearities by an element rotation algorithm when a segmented current-steering internal DAC with 9- (b) level resolution is used. Current-cells in ON state which are filled in black, Fig. 6 (a) Highpass element rotation architecture. (b) Equivalent block when input data are sequentially given by 4, 3, 2, 6, 5, .... diagram. Figure 7(a) shows the unit-current-cells in ON state while −1 input data are shifted by 4, 3, 2, 6, . . . for highpass noise- D4(z) = (1 + z ) D3(z) (12) shaping in element rotation algorithm by 1 + z−1. When the D (z) = D (z) + δ(z). (13) 3 2 input is 4 at time n, unit-current-cells of 0, 1, 2, 3 are ON. + Thus the analog output of D4(z)isgivenby When it is 3 at time n 1, those of 3, 2, 1 are ON, and when it is 2 at time n + 2, those of 1, 2 are ON. Also when it is −1 D4(z) = D1(z) + (1 + z )δ(z). (14) 6 at time n + 3, those of 2, 1, 0, 7, 6, 5 are ON. In other δ words, unit-current-cells are selected clockwise or counter We see that the DAC nonlinearity (z) is first-order noise- clockwise alternately at every sample time. shaped by 1 + z−1. Note that Eqs. (11), (12), (13) are equivalent to the following: 3. Complex Bandpass Noise-Shaping Algorithm of DAC Nonlinearities D2(n + 1) = D2(n) − D1(n + 1) (15) + = + + D4(n 1) D3(n 1) D3(n) (16) In this section, we will derive an element rotation algorithm D3(n) = D2(n) + δ(n). (17) in complex bandpass modulators, based on the element rotation algorithms in lowpass and highpass modulators de- If we replace a multi-bit DAC in a highpass ∆ΣAD mod- scribed in Sect. 2. ulator with the circuit in Fig. 6, its DAC nonlinearity is noise-shaped. However, similarly to the lowpass case, this 3.1 Complex Bandpass ∆ΣAD Modulator structure cannot work properly and we have to consider its equivalent implementation (a highpass element rotation al- Figure 8 shows a complex bandpass ∆ΣAD modulator, a gorithm). first-order complex bandpass filter and its gain character- We modify the segmented current-steering DAC so that istics. We see that the complex filter has two inputs and the unit-current-cells are in a ring form and the DAC have a outputs, and it consists of a complex bandpass filter, two pointer P(n). The rigorous description of the highpass ele- internal ADCs and DACs. For example, the transfer func- ment rotation algorithm is as follows: tion of the complex bandpass filter shown in Fig. 8(b) can be • At time 2n: written as follows [6]: 1 – Suppose that the input data D1(2n) = d2n. = H(z) − + – Turn on d2n unit-current-cells of P(2n), mod8 z (d jc) + + ... + (P(2n) 1), mod8(P(2n) 2), ,mod8(P(2n) where c and d are design parameters (appropriate constants − d2n 1). In other words, d2n unit-current-cells are of real values) which characterize the complex bandpass fil- selected from P(2n) clockwise. ter. We see in Fig. 8(c) that the gain of the complex bandpass + + = – Set the pointer at time 2n 1toP(2n 1) filter is asymmetrical to the axis of ω = 0. mod8(P(2n) + d2n − 1). • At time 2n + 1: 3.2 Proposed Architecture for Complex Bandpass Noise- Shaping of DAC Nonlinearities – Suppose that the input data D1(2n + 1) = d2n+1. – Turn on d2n+1 unit-current-cells of P(2n + 1), We consider here complex bandpass ∆ΣAD modulators + − + − ... mod8(P(2n 1) 1), mod8(P(2n 1) 2), , whose center of passband is at the normalized frequency + − + mod8(P(2n 1) d2n 1). In other words, of ω = π/2(1/4 of the sampling frequency) [1]–[6]. Fig- + d2n+1 unit-current-cells are selected from P(2n 1) ure 9 shows our proposed architecture for complex bandpass counter clockwise. noise-shaping of DAC nonlinearities. It consists of a digital – Set the pointer at time 2n + 2toP(2n + 2) = complex filter at front-end, two DACs, and an analog com- + − + mod8(P(2n 1) d2n+1 1). plex filter at back-end. I1 is the digital output of the ADC in IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.4 APRIL 2004 796

By substituting Eqs. (18) and (19) to Eq. (20), we have 1 M(z) = Y(z) + (δ + jδ ). (21) F(z) 1 2 Note that Eqs. (1) and (2) hold also for the complex bandpass ∆ΣAD modulator if we consider H(z) is a complex ﬁlter and X(z), Y(z), E(z)andδ(z) are complex signals. Then by substituting Eq. (21) to Eq. (1) and sorting it, we obtain

= H(z) N(z) + 1 H(z) 1 1 · E(z) − (δ (z) + jδ (z)) . (22) H(z) F(z) 1 2 We see that by comparing Eq. (22) with Eq. (3), not only the (complex) quantization noise E(z) of 2-channel ADCs / Fig. 8 (a) Complex bandpass ∆ΣAD modulator block diagram. (b) An is noise-shaped by 1 H(z), but also the 2-channel DACs example of a complex bandpass ﬁlter. (c) Gain characteristics of Fig. 8(b). (complex) nonlinearities error (δ1 + jδ2) is noise-shaped by 1/F(z).

3.3 Realization Algorithm for Proposed Architecture

We obtain the following equations in Fig. 9:

I2(n + 1) = I1(n) − Q2(n) (23)

I4(n + 1) = I3(n + 1) + Q3(n) (24)

I3(n) = I2(n) + δ1(n) (25) Fig. 9 Proposed architecture of DAC nonlinearity noise-shaping for a + = + complex bandpass modulator, where two pointers and multiplexers are Q2(n 1) I2(n) Q1(n) (26) added to the feedback DACs. I1 is the I-channel ADC output and Q1 is Q4(n + 1) = Q3(n + 1) − I3(n) (27) the Q-channel ADC output, while I is the I-channel DAC output and Q 4 4 Q (n) = Q (n) + δ (n). (28) is the Q-channel DAC output. δ1 and δ2 denote the nonlinearities of DAC1 3 2 2 and DAC2 respectively. However, note that this architecture cannot be implemented directly. The direct realization of the proposed architecture in Fig. 9 is not possible because I2, Q2 can be out-of-input-range of the following I, Q-channel DACs. For example, suppose I-channel and Q1 is that in Q-channel. Also I4 is the analog that output of the DAC in I-channel and Q4 is that in Q-channel. π I (n) + jQ (n) = exp( j n) + 4. The transfer function of the digiltal complex filter at front- 1 1 2 end is written by This can happen because the center of the signal band in the 1 modulator is at the normalized frequency of ω = π/2, and F(z) = . z − j I1, Q1 are integer values between 0 to 8. Then it follows from Eqs. (23) and (26) that Then the transfer function of the analog complex filter at back-end is given by 1/F(z). Noting that the complex multi- I2(1) = 5 − Q2(0), I2(2) = −I2(0), bit output signal of 2-channel ADCs is given by I2(3) = −7 + Q2(0), I2(4) = I2(0) ... = + , = − , Y(z):= I1(z) + jQ1(z), Q2(1) 4 I2(0) Q2(2) 10 Q2(0) Q (3) = 4 − I (0), Q (4) = −4 + Q (0) ... and the complex output signal of 2-channel DACs which is 2 2 2 2 fedback to the complex filter is given by We see that I2 and Q2 can be out of the DAC input rage (0, 1,2,...,8). = + , M(z): I4(z) jQ4(z) Now we describe an equivalent realization of the pro- we obtain the followings in Fig. 9: posed architecture; our implementation use only a digital filter at front-end of 2-channel DACs and does not require I2(z) + jQ2(z) = F(z) · Y(z) (18) an analog filter at back-end.

I3(z) + jQ3(z) = (I2(z) + jQ2(z)) + (δ1 + jδ2) (19) [ Proposed Algorithm ] 1 We modify the two segmented current-steering DACs as fol- M(z) = (I + jQ ). (20) F(z) 3 3 lows (Fig. 10(a)): SAN et al.: A NOISE-SHAPING ALGORITHM OF MULTI-BIT DAC NONLINEARITIES IN COMPLEX BANDPASS ∆ΣAD MODULATORS 797

– Turn on the following unit-current-cells of DAC2: P2(2n+1), mod8(P2(2n+1)−1), . . . , mod8(P2(2n+ 1) − i2n+1 + 1). In other words, i2n+1 unit-current- cells are selected counter clockwise from P2(2n + 1). – Make the output of DAC2 to be the I-channel DAC output, I4(2n + 1). – Set the pointer of DAC2 at time 2n + 2to P2(2n + 2) = mod8(P2(2n + 1) − i2n+1 + 1).

Assume that the Q-channel DAC input Q1(2n + 1) = q2n+1. – Turn on the following unit-current-cells of DAC1: mod8(P1(2n + 1) + 1), mod8(P1(2n + 1) + 2), ..., mod8(P1(2n + 1) + q2n+1)Inotherwords, q2n+1 unit-current-cells are selected clockwise from mod8(P1(2n + 1) + 1). Fig. 10 (a) Proposed complex bandpass ∆ΣAD modulator. (b) Explana- – Make the output of DAC1 to be the Q-channel tion of the proposed algorithm. The unit-current-cells in ON state are filled DAC output, Q4(2n + 1). in black for a real part (I-path) and in gray for an imaginary part (Q-path), + + + + – Set the pointer of DAC1 at time n 2to when the complex input data are sequentially given by 4 3j, 2 5j, 3 j, + = + + 6+2j,.... P1(2n 2) mod8(P1(2n 1) q2n+1). Figure 10(b) explains their operation when the complex input data are sequentially given by 4+3j, 2+5j, 3+j, 6+2j, • Arrange unit-current-cells of each DAC in a ring form .... asshowninFig.4. Now we will explain how this algorithm was derived • Let each DAC have a pointer to show which unit- and why it is equivalent to the architecture in Fig. 9. current-cell should be selected next sample time, and First, we consider the I-channel. The I-channel DAC let the pointers for DAC1 and DAC2 be P1(n)andP2(n) (whose output is I4 as shown in the upper part of Fig. 9) is at time n. equivalent to Highpass digital filter + DAC + Lowpass analog filter; look at the left part of Fig. 6(b) and the upper-left Then let their operation be as follows: part of Fig. 9, and also compare Eqs. (23) and (15). If Q2(n) • At time 2n: in Eq. (23) is replaced with I2(n), Eq. (23) has the same form as Eq. (15). Similarly look at the right part of Fig. 6(b) and Suppose that the I-channel DAC input I1(2n) = i2n. the upper-right part of Fig. 9, and also compare Eqs. (24) and – Turn on the following unit-current-cells of DAC1: (16). Q3(n) in Eq. (24) is replaced with I3(n), Eq. (24) has P1(2n), mod8(P1(2n)+1),...,mod8(P1(2n)+i2n − the same form as Eq. (16). Also Eq. (25) has the same form 1). In other words, i2n unit-current-cells are se- as Eq. (17). Thus we see the following: lected clockwise from P (2n). 1 • For the I-channel DAC output I , we apply a highpass – Make the output of DAC1 to be the I-channel DAC 4 element rotation algorithm with internal interaction be- output, I (2n). 4 tween I, Q paths. – Set the pointer of DAC1 at time 2n + 1to P1(2n + 1) = mod8(P1(2n) + i2n − 1). Next, we consider the Q-channel. The Q-channel DAC (whose output is Q asshowninthelowerpartofFig.9)is = 4 Assume that the Q-channel DAC input Q1(2n) q2n. equivalent to Lowpass digital filter + DAC + Highpass ana- – Turn on the following unit-current-cells of DAC2: log filter ; look at the left part of Fig. 3(b) and the lower-left part of Fig. 9, and also compare Eqs. (26) and (8). If I (n)in mod8(P2(2n) + 1), mod8(P2(2n) + 2), ..., 2 Eq. (26) is replaced with Q (n), Eq. (26) has the same form mod8(P2(2n) + q2n). In other words, q2n unit- 2 as Eq. (8). Similarly look at the right part of Fig. 3(b) and current-cells are selected clockwise from P2(2n) + 1. the lower-right part of Fig. 9, and also compare Eqs. (27) – Make the output of DAC2 to be the Q-channel and (9). I3(n) in Eq. (27) is replaced with Q3(n), Eq. (27) has the same form as Eq. (9). Also Eq. (28) has the same DAC output, Q4(2n). – Set the pointer of DAC2 at time 2n + 1to form as Eq. (10). Thus we see the following: + = + P2(2n 1) mod8(P2(2n) q2n). • For the Q-channel DAC output Q4, we apply a lowpass element rotation algorithm with internal interaction be- • At time 2n + 1: tween I, Q paths. Suppose that the I-channel DAC input I1(2n + 1) = i2n+1. Now we consider the interactions between I-path and Q-path IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.4 APRIL 2004 798 in Fig. 9 (or equivalently in Eqs. (23), (24), (26) and (27)). • Case 3: Two DACs whose mismatches are the same as It follows from Eqs. (23) and (24) that the I-channel out- case 2 and which employ the proposed element rotation put I4 at time n + 1 is a function of the Q-channel internal algorithm were used. states (Q (n), Q (n)) at time n as well as the I-channel input 2 3 Figures 12, 13 show the simulation result comparison for I . Also we see from Eqs. (26) and (27) that the Q-channel 1 output spectrum and SNR of modulators in three cases, output Q at time n + 1 is a function of the I-channel inter- 4 where the simulation conditions are as follows: nal states (I2(n), I3(n)) at time n as well as the Q-channel input Q1. Noting that the pointers P1(n), P2(n) keep some • In cases 2 and 3, e0, e1, e2,...,e7 in DAC1 are 0.0023, information of the I, Q channels internal states, we have the −0.0015, −0.003, 0.0028, 0.0025, 0.0029, −0.001 and following observation: 0.0 (LSB) while those in DAC2 are −0.0017, 0.0015, −0.0025, 0.002, 0.0026, 0.0, −0.0019, and 0.0 (LSB). • If DAC1 with a pointer P is used for I-channel and 1 • 16 K-point FFT is used to obtain the SNR. DAC2 with a pointer P is used for Q-channel at time 2 • Input frequency ( f )/sampling frequency ( f ) = 2n, then DAC1 is used for Q-channel and DAC2 is used in s 4,095/16,384. for I-channel at time 2n + 1. We see that in case 1, SNR of the ADC increases as OSR Then the proposed algorithm is derived and the nonlinear- δ ,δ increases. However in case 2, SNR saturates as OSR in- ities of 2-channel DACs, 1 2, will be first-order complex creases; for small OSRs, quantization noise is dominant bandpass noise-shaped. but it is noise-shaped and hence SNR improves as OSR in- 4. Simulation of Proposed Algorithm

We have conducted MATLAB simulations to confirm the noise-shaping function on multi-bit DAC nonlinearities of the proposed algorithm. We used a fourth-order complex modulator [15] with internal ADCs/DACs of 9-level resolution in three cases. Figure 11 shows the complex bandpass filter used inside the modulator, where three poles are located at the normalized angular frequency of ω = π/2 while one is at ω = 3π/2; the reason that one pole is located at ω = 3π/2 is that when this complex filter is incorporated in a modulator in Fig. 8, the quantization noise of the modulator is reduced by noise-shaping at ω = 3π/2, which will appear at ω = π/2 of the modulator output as image quantization noise caused by I, Q mismatches inside the modulator. For all three cases, the same analog complex bandpass Fig. 12 The simulated results of the output power spectrum for complex filter and two ideal internal ADCs in a ∆Σ modulator were bandpass ∆Σ modulators. (a) The simulated result with ideal DACs. (b) used. However two DACs in a modulator in three cases are The simulated result with normal segmented current-steering DACs with different as follows: mismatch among unit-current-cells. (c) The simulated result with proposed algorithm of DACs with the same mismatch among unit-current-cells. The • Case 1: Two identical and ideal (linear) DACs were reason that the output power is noise-shaped at ω = 3π/2 (as well as at ω = π/ used. 2 which is the center of the signal band) is that the complex filter in Fig. 11 has a pole at ω = 3π/2 (as well as three poles at ω = π/2). • Case 2: Two normal segmented current-steering DACs with mismatches among unit-current-cells were used.

Fig. 11 A fourth-order complex bandpass ﬁlter used in a modulator in Fig. 8. Fig. 13 The simulated results of SNR versus OSR in cases 1, 2 and 3. SAN et al.: A NOISE-SHAPING ALGORITHM OF MULTI-BIT DAC NONLINEARITIES IN COMPLEX BANDPASS ∆ΣAD MODULATORS 799

−0.0015, −0.003, 0.0028, 0.0025, 0.0029, −0.001 and 0.0 (LSB) while those in DAC2 are −0.0017, 0.0015, −0.0025, 0.002, 0.0026, 0.0, −0.0019, and 0.0 (LSB). The left graph shows in case 2 while the right graph shows in case 3. We see that in case 2 SNR degrades rapidly as rms value increases while in case 3 SNR is improved. We observe in Figs. 13, 14 that in case2 SNR does not improve even if OSR increases for relatively large DAC nonlinearities (if the spectrum of the DAC nonlinearities error is white, twice of OSR leads to at least 3 dB SNR improvement, even if it is not noise-shaped); this is because there are spurious tones at the frequencies of (4,091/16,384) fs and (4,099/16,384) fs due to large DAC nonlinearityies (Fig. 15), which are the main noise (distortion) components and are not removed with this range of OSRs.

5. Concluding Remarks Fig. 14 Simulation results of the modulator SNR versus rms values of mismatches e0, e1, e2,...,e7 for OSR = 32, 64, 128 and 256. The left graph shows in case that normal segmented DACs are used while the right We have proposed a new noise-shaping algorithm of multi- graph shows in that case that our proposed algorithm is incorporated. bit DAC nonlinearities for a high resolution complex bandpass ∆ΣAD modulator. The performance of the complex bandpass ∆ΣADC can be improved by adding some simple digital circuits. The effectiveness of proposed algorithm is confirmed by MATLAB simulation. Finally we remark the followings: • In the proposed algorithm, at time 2n,DAC1isused for I-channel and DAC2 is for Q-channel, while, at time 2n + 1, DAC1 is for Q-channel and DAC2 is for I-channel; DAC1, DAC2 are used alternately for I, Q-channels, and hence the harmful influence by mismatches between 2-channel DACs is expected to be suppressed with this algorithm. • The proposed algorithm is applicable to multi-bit complex bandpass ∆Σ DA modulators as well as AD modulators. The importance of the bandpass ∆Σ DA modulator is described in [16]. Fig. 15 The simulated results of the output power spectrum focused • Our approach here is to improve the accuracy of analog around the signal band in Fig. 12, where (4,095/16,384) fs is the signal frequency component. (a) Case 1. (b) Case 2. (3) Case 3. We see that in circuits using digital signal processing techniques. We case 2, there are spurious tones at (4,091/16,384) fs and (4,099/16,384) fs believe that such an approach becomes more important, while they are removed in case 3. because as the VLSI technology progresses and the de- vice size scales down, the supply voltage goes down, which makes it difficult to achieve the high accuracy creases. However for high OSRs the noise due to DAC non- of analog circuits with only circuit technique. On the linearity becomes dominant, which is not noise-shaped and other hand, the digital circuit becomes faster, cheaper hence increasing OSR does not help much improve SNR. and lower power, which makes rather complicated dig- On the other hand, in case 3, the noise caused by nonlinear- ital signal processing algorithm feasible to utilize for ities of DAC is pushed out from the signal band, and their the analog circuit performance improvement. influence to the ADC accuracy is reduced which leads to the ADC SNR improvement. Figure 14 shows simulation results of the modulator Acknowledgement SNR versus root-mean-square (rms) values of mismatches We would like to thank STARC which is supporting this e0, e1, e2,...,e7 for OSR = 32, 64, 128 and 256. Here the value of the mismatches is defined by research. Thanks are also due to H. Wada, A. Hayakawa, H. Hagiwara, T. Matsuura, H. Okawara, M. Hoshino, rms := (e2 + e2 + e2 + ...+ e2)/8 H. Ishii, T. Komuro and K. Wilkinson for valuable discus- 0 1 2 7 sions. A part of this work was performed at Gunma Univer- and the ratios of e0, e1, e2,...,e7 in DAC1 are 0.0023, sity Satellite Venture Business Laboratory. IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.4 APRIL 2004 800

Hao San received the B.S. degree in au- References tomation engineering from Liaoning Institute of Technology, China in 1993, and the M.S. de- [1] K. Philips, “A 4.4mW 76 dB complex Σ∆ ADC for Bluetooth re- gree in electronic engineering from Gunma Uni- ceivers,” ISSCC Digest of Technical Papers, vol.46, pp.64–65, Feb. versity, Japan in 2000. Then he worked for 2003. Kawasaki Microelectronics Inc. from 2000 to [2] F. Henkel, U. Langmann, A. Hanke, S. Heinen, and E. Wanger, “A 2002. Currently he is a doctoral course graduate 1 MHz-bandwidth second-order continuous-time quadrature band- student in electronic engineering department at pass sigma-delta modulator for low-IF radio receivers,” IEEE J. Gunma University, where he has been engaged Solid-State Circuits, vol.37, pp.1628–1635, Dec. 2002. in design of bandpass sigma-delta AD convert- [3] F. Esfahari, P. Basedau, P. Ryter, and R. Beker, “A fourth order ers and charge pump circuits. continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers,” Symp. VLSI Circuits, Digest of Technical Papers, pp.75–78, June 2003. [4] R. Schreier, J. Lloyd, L. Singer, D. Paterson, M. Timko, M. Hensley, Haruo Kobayashi received the B.S. and G. Patterson, K. Behel, and J. Zhou, “A 10–300 MHz IF-digitizing M.S. degrees in information physics from Uni- IC with 90–105 dB dynamic range and 15–333 kHz bandwidth,” versity of Tokyo in 1980 and 1982 respec- IEEE J. Solid-State Circuits, vol.37, pp.1636–1644, Dec. 2002. tively, the M.S. degree in electrical engineering [5] T. Salo, T. Hollman, S. Lindfors, and K. Halonen, “A Dual-Mode from University of California at Los Angeles 80MHz bandpass ∆Σ modulator for a GSM/WCDMA IF-receiver,” （UCLA） in 1989, and the Dr. Eng. degree in ISSCC Digest of Technical Papers, vol.45, pp.218–219, Feb. 2002. electrical engineering from Waseda University [6] S.A. Jantzi, K.W. Martin, and A.S. Sedra, “Quadrature bandpass Σ∆ in 1995. He joined Yokogawa Electric Corp. To- modulator for digital radio,” IEEE J. Solid-State Circuits, vol.32, kyo, Japan in 1982, where he was engaged in the pp.1935–1949, Dec. 1997. research and development related to measuring [7] S.R. Norsworthy, R. Schreier, and G.C. Temes, eds., Deta-Sigma instruments and mini-supercomputers. From Data Converters, —Theory, Design and Simulation, IEEE Press, 1994 to 1997, he was involved in research and development of ultra-high- / 1997. speed ADCs DACs at Teratec Corp. In 1997 he joined Gunma University [8] T. Ueno, A. Yasuda, T. Yamaji, and T. Itakura, “A fourth-order and presently is a Professor in Electronic Engineering Department there. bandpass ∆-Σ modulator using second-order bandpass noise-shaping He was also an adjunct lecturer at Waseda University from 1994 to 1997. dynamic element matching,” IEEE J. Solid-State Circuits, vol.37, His research interests include mixed-signal integrated circuits design and pp.809–816, July 2002. signal processing algorithms. He received Yokoyama Award in Science [9] T. Shui, R. Screier, and F. Hudson, “Mismatch shaping for a current- and Technology in 2003 and the Best Paper Award from the Japanese Neu- mode multibit delta-sigma DAC,” IEEE J. Solid-State Circuits, ral Network Society in 1994. vol.34, pp.331–338, March 1999. [10] L.R. Carley, “A noise-shaping coder topology for 15 bit converters,” IEEE J. Solid-State Circuits, vol.24, pp.267–273, April 1989. Shinya Kawakami received the B.S. de- ff [11] E. Fogleman, I. Galton, W. Hu , and H. Jensen, “A 3.3-V single- gree and is expected to receive the M.S. degree poly CMOS audio ADC delta-sigma modulator with 53.8-dB peak in electronic engineering from Gunma Univer- SINAD and 105-dB peak SFDR,” IEEE J. Solid-State Circuits, sity in 2002 and 2004 respectively. Currently vol.35, pp.297–307, March 2000. he is a graduate student there and he has been [12] R. Shreier, J. Steensgaard, and G.C. Temes, “Speed vs. dynamic involved in research for analysis and design of ff ff range trade-o in oversampling data converters,” in Trade-O s CMOS digital-to-analog integrated circuits. in Analog Circuit Design, The Designer’s Companion, eds. C. Toumazou, G. Moschytz, and B. Gilbert, pp.644–653, Kluwer Aca- demic Publishers, 2002. [13] Y. Yang, A, Chokhawala, M. Alexander, J. Melanson, and D. Hester, “A 114 dB 68 mW chopper-stabilized stereo multi-bit audio A/D converter,” ISSCC Digest of Technical Papers, vol.46, pp.56–57, Nobuyuki Kuroiwa received the B.S. and Feb. 2003. M.S. degrees in electronic engineering from [14] B. Razavi, Principles of Data Converter Design, IEEE Press, 1995. Gunma University in 2000 and 2002 respec- [15] A. Swaminathan, A single-IF receiver architecture using a complex tively, where he was involved in research for de- SD modulator, M.Eng. Thesis, Carleton Univ. Ottawa, ON, Canada sign, analysis and measurements of level-shift 1997. circuits and charge pump circuits. In 2002 he [16] D.B. Barkin, A.C.Y. Yin, D.K. Su, and B.A. Wooley, “A CMOS joined Hitachi ULSI Systems Co., Ltd., where oversampling bandpass cascaded D/A converter with digital FIR and he is engaged in analog integrated circuit design. current-mode semi-digital filtering,” Symp. VLSI Circuits, Digest of Technical Papers, pp.79–82, June 2003.