DOCSLIB.ORG

GPU Data Structures for Graphics and Vision

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
GPU Data Structures for Graphics and Vision Gernot Ziegler GPU Data Structures for Graphics and Vision - Ph.D. Thesis - Dissertation zur Erlangung des Grades Doktoringenieur (Dr.-Ing.) der Naturwissenschaftlich-Technischen Fakultät I der Universität des Saarlandes Max-Planck-Institut für Informatik Campus E1.4 66123 Saarbrücken Germany 2 Eingereicht am / Submitted on 20. 9. 2010 in Saarbrücken. Gernot Ziegler MPI Informatik - D4 Campus E1.4 D-66123 Saarbrücken Deutschland E-mail: [email protected] Betreuender Hochschullehrer - Supervisor Prof. Dr. Christian Theobalt, Max-Planck-Institut für Informatik, Saarbrücken, Deutschland. Prüfungsvorsitzender - Chairman of Examination Committee Prof. Dr. Christoph Weidenbach, Max-Planck-Institut für Informatik, Saarbrücken, Deutschland. Gutachter - Reviewers Prof. Dr. Hans-Peter Seidel, Max-Planck-Institut für Informatik, Saarbrücken, Deutschland. Prof. Dr-Ing. Marcus Magnor, TU Braunschweig, Braunschweig, Deutschland Prof. Dr. Christian Theobalt, Max-Planck-Institut für Informatik, Saarbrücken, Deutschland. Dekan - Dean Prof. Dr. Holger Hermanns, Universität des Saarlandes, Saarbrücken, Deutschland. Promovierter akademischer Mitarbeiter - Academic Member of the Faculty having a Doctorate Dr. Robert Herzog, Max-Planck-Institut für Informatik, Saarbrücken, Deutschland. Datum des Kolloquiums - Date of Defense 6. Mai 2011 - May 6th, 2011 3 Abstract Graphics hardware has in recent years become increasingly programmable, and its programming APIs use the stream processor model to expose massive parallelization to the programmer. Unfortunately, the inherent restrictions of the stream processor model, used by the GPU in order to maintain high performance, often pose a problem in porting CPU algorithms for both video and volume processing to graphics hardware. Serial data dependencies which accelerate CPU processing are counterproductive for the data-parallel GPU. This thesis demonstrates new ways for tackling well-known problems of large scale video/volume analysis. In some instances, we enable processing on the restricted hardware model by re- introducing algorithms from early computer graphics research. On other occasions, we use newly discovered, hierarchical data structures to circumvent the random-access read/fixed write restriction that had previously kept sophisticated analysis algorithms from running solely on graphics hardware. For 3D processing, we apply known game graphics concepts such as mip-maps, projective texturing, and dependent texture lookups to show how video/volume processing can benefit algorithmically from being implemented in a graphics API. The novel GPU data structures provide drastically increased processing speed, and lift processing heavy operations to real-time performance levels, paving the way for new and interactive vision/graphics applications. Kurzfassung Graphikhardware wurde in den letzen Jahren immer weiter programmierbar. Ihre APIs verwenden das Streamprozessor-Modell, um die massive Parallelisierung auch für den Programmierer verfügbar zu machen. Leider folgen aus dem strikten Streamprozessor-Modell, welches die GPU für ihre hohe Rechenleistung benötigt, auch Hindernisse in der Portierung von CPU-Algorithmen zur Video- und Volumenverarbeitung auf die GPU. Serielle Datenabhängigkeiten beschleunigen zwar CPU-Verarbeitung, sind aber für die daten-parallele GPU kontraproduktiv . Diese Arbeit präsentiert neue Herangehensweisen für bekannte Probleme der Video- und Volumensverarbeitung. Teilweise wird die Verarbeitung mit Hilfe von modifizierten Algorithmen aus der frühen Computergraphik-Forschung an das beschränkte Hardwaremodell angepasst. Anderswo helfen neu entdeckte, hierarchische Datenstrukturen beim Umgang mit den Schreibzugriff-Restriktionen die lange die Portierung von komplexeren Bildanalyseverfahren verhindert hatten. In der 3D-Verarbeitung nutzen wir bekannte Konzepte aus der Computerspielegraphik wie Mipmaps, projektive Texturierung, oder verkettete Texturzugriffe, und zeigen auf welche Vorteile die Video- und Volumenverarbeitung aus hardwarebeschleunigter Graphik-API-Implementation ziehen kann. Die präsentierten GPU-Datenstrukturen bieten drastisch schnellere Verarbeitung und heben rechenintensive Operationen auf Echtzeit-Niveau. Damit werden neue, interaktive Bildverarbeitungs- und Graphik-Anwendungen möglich. 4 Summary This doctoral thesis details how well-known tasks in large scale video/volume analysis, previously too complex for graphics hardware, can now be implemented using our new algorithmic concepts and data structures. The content begins with an introduction to graphics hardware and the graphics processing unit (GPU). We explain how graphics hardware works internally, how it differs from the CPU, and how its high performance is achieved. Afterwards we elaborate how the high performance design choices, namely parallelization and massive data processing, impose several restrictions on the programming model. Finally, we describe how general purpose computing on the GPU (GPGPU) emerged from the increasing flexibility of the graphics hardware, as well as which hardware/driver features are pivotal for GPGPU applications. Chapter 3 first explains the use of graphics hardware in Free Viewpoint Video (FVV) processing, which requires a merger of computer graphics and image processing to generate novel viewpoints from multi-view video streams. We describe how graphics hardware can not only assist in FVV playback but also in the compression of multi view video. In Chapter 4, we introduce how the camera/projector dualism can be implemented on graphics hardware. We demonstrate its usefulness in interactive camera calibration via proxy geometry, explain how depth projection can be easier represented in the OpenGL graphics API, and provide several approaches to fast reconstruction of novel views from depth video. Chapter 5 is dedicated to hierarchical image processing, which fits graphics hardware very well due to its regular structure. We explain how depth reconstruction via a plane-sweep approach benefits from graphics hardware acceleration. Then, the chapter continues on feature clustering based on reduction, which we use in the real-time detection of connected feature regions in images. The last section addresses how histograms can be computed in a data-parallel fashion, and how camera lens compensation can be accelerated via rapid histogram analysis of feature contour angles. Chapter 6 introduces a hierarchical data structure for GPU-based data compaction, the HistoPyramid, originally only a byproduct of fast histogram computation. We demonstrate how a traversal of HistoPyramids can circumvent many architectural restrictions of graphics hardware in the compaction of large data arrays to few selected input elements. The chapter continues with first applications: Real-time point cloud extraction and Streamline visualization for volume data, and concludes with future applications of the discovered data structure and algorithms. Chapter 7 demonstrates how HistoPyramids even prove useful in data expansion, a concept for replication and modification of input elements while writing an output array. After explaining the necessary modifications, we present two key applications: Real-time iso-surface extraction from volume data via the marching cubes algorithm, and Light Wavefront Simulation via adaptive ODEs. Chapter 8 introduces QuadPyramids, a descendant of HistoPyramids, which is used to cluster common regions in input data. With the help of these data structures, compact quadtrees can be extracted directly into graphics memory. We show first results from real-time video analysis, sketch relevant applications, and discuss how different methods of feature clustering affect the outcome. Chapter 9 presents the QuadPyramid´s logical extension to 3D, the OcPyramid. Beyond the promotion of the original algorithm to three dimensions, we explain how algorithmic extensions enable pointer octree generation on graphics hardware, and can thus contribute to a renaissance for the use of octrees in real-time computer graphics. Chapter 10 summarizes the contributions of the presented research and concludes the thesis with an outlook on the future development of GPU algorithms in the wider context of hardware evolution. 5 Contents 1. Overview................................................................................................15 1.1. Motivation and Overview........................................................................................15 1.2. Supervised student theses........................................................................................17 1.3. Publications.............................................................................................................17 2. The GPU - An Introduction.................................................................18 2.1. The History of Graphics Hardware.........................................................................18 2.2. General Purpose Computing on the GPU................................................................21 2.2.1. Early Studies .................................................................................................................21 2.2.2. Data-Parallel Architecture..............................................................................................22 2.2.3. GPU vs. CPU.................................................................................................................24 2.2.4. Related Architectures.....................................................................................................25
Load more

Recommended publications
  • GPU Architecture • Display Controller • Designing for Safety • Vision Processing
    i.MX 8 GRAPHICS ARCHITECTURE FTF-DES-N1940 RAFAL MALEWSKI HEAD OF GRAPHICS TECH ENGINEERING CENTER MAY 18, 2016 PUBLIC USE AGENDA • i.MX 8 Series Scalability • GPU Architecture • Display Controller • Designing for Safety • Vision Processing 1 PUBLIC USE #NXPFTF 1 PUBLIC USE #NXPFTF i.MX is… 2 PUBLIC USE #NXPFTF SoC Scalability = Investment Re-Use Replace the Chip a Increase capability. (Pin, Software, IP compatibility among parts) 3 PUBLIC USE #NXPFTF i.MX 8 Series GPU Cores • Dual Core GPU Up to 4 displays Accelerated ARM Cores • 16 Vec4 Shaders Vision Cortex-A53 | Cortex-A72 8 • Up to 128 GFLOPS • 64 execution units 8QuadMax 8 • Tessellation/Geometry total pixels Shaders Pin Compatibility Pin • Dual Core GPU Up to 4 displays Accelerated • 8 Vec4 Shaders Vision 4 • Up to 64 GFLOPS • 32 execution units 4 total pixels 8QuadPlus • Tessellation/Geometry Compatibility Software Shaders • Dual Core GPU Up to 4 displays Accelerated • 8 Vec4 Shaders Vision 4 • Up to 64 GFLOPS 4 • 32 execution units 8Quad • Tessellation/Geometry total pixels Shaders • Single Core GPU Up to 2 displays Accelerated • 8 Vec4 Shaders 2x 1080p total Vision • Up to 64 GFLOPS pixels Compatibility Pin 8 • 32 execution units 8Dual8Solo • Tessellation/Geometry Shaders • Single Core GPU Up to 2 displays Accelerated • 4 Vec4 Shaders 2x 1080p total Vision • Up to 32 GFLOPS pixels 4 • 16 execution units 8DualLite8Solo • Tessellation/Geometry Shaders 4 PUBLIC USE #NXPFTF i.MX 8 Series – The Doubles GPU Cores • Dual Core GPU Up to 4 displays Accelerated • 16 Vec4 Shaders Vision
    [Show full text]
  • Directx and GPU (Nvidia-Centric) History Why
    10/12/09 DirectX and GPU (Nvidia-centric) History DirectX 6 DirectX 7! ! DirectX 8! DirectX 9! DirectX 9.0c! Multitexturing! T&L ! SM 1.x! SM 2.0! SM 3.0! DirectX 5! Riva TNT GeForce 256 ! ! GeForce3! GeForceFX! GeForce 6! Riva 128! (NV4) (NV10) (NV20) Cg! (NV30) (NV40) XNA and Programmable Shaders DirectX 2! 1996! 1998! 1999! 2000! 2001! 2002! 2003! 2004! DirectX 10! Prof. Hsien-Hsin Sean Lee SM 4.0! GTX200 NVidia’s Unified Shader Model! Dualx1.4 billion GeForce 8 School of Electrical and Computer 3dfx’s response 3dfx demise ! Transistors first to Voodoo2 (G80) ~1.2GHz Engineering Voodoo chip GeForce 9! Georgia Institute of Technology 2006! 2008! GT 200 2009! ! GT 300! Adapted from David Kirk’s slide Why Programmable Shaders Evolution of Graphics Processing Units • Hardwired pipeline • Pre-GPU – Video controller – Produces limited effects – Dumb frame buffer – Effects look the same • First generation GPU – PCI bus – Gamers want unique look-n-feel – Rasterization done on GPU – Multi-texturing somewhat alleviates this, but not enough – ATI Rage, Nvidia TNT2, 3dfx Voodoo3 (‘96) • Second generation GPU – Less interoperable, less portable – AGP – Include T&L into GPU (D3D 7.0) • Programmable Shaders – Nvidia GeForce 256 (NV10), ATI Radeon 7500, S3 Savage3D (’98) – Vertex Shader • Third generation GPU – Programmable vertex and fragment shaders (D3D 8.0, SM1.0) – Pixel or Fragment Shader – Nvidia GeForce3, ATI Radeon 8500, Microsoft Xbox (’01) – Starting from DX 8.0 (assembly) • Fourth generation GPU – Programmable vertex and fragment shaders
    [Show full text]
  • MSI Afterburner V4.6.4
    MSI Afterburner v4.6.4 MSI Afterburner is ultimate graphics card utility, co-developed by MSI and RivaTuner teams. Please visit https://msi.com/page/afterburner to get more information about the product and download new versions SYSTEM REQUIREMENTS: ...................................................................................................................................... 3 FEATURES: ............................................................................................................................................................. 3 KNOWN LIMITATIONS:........................................................................................................................................... 4 REVISION HISTORY: ................................................................................................................................................ 5 VERSION 4.6.4 .............................................................................................................................................................. 5 VERSION 4.6.3 (PUBLISHED ON 03.03.2021) .................................................................................................................... 5 VERSION 4.6.2 (PUBLISHED ON 29.10.2019) .................................................................................................................... 6 VERSION 4.6.1 (PUBLISHED ON 21.04.2019) .................................................................................................................... 7 VERSION 4.6.0 (PUBLISHED ON
    [Show full text]
  • Graphics Shaders Mike Hergaarden January 2011, VU Amsterdam
    Graphics shaders Mike Hergaarden January 2011, VU Amsterdam [Source: http://unity3d.com/support/documentation/Manual/Materials.html] Abstract Shaders are the key to finalizing any image rendering, be it computer games, images or movies. Shaders have greatly improved the output of computer generated media; from photo-realistic computer generated humans to more vivid cartoon movies. Furthermore shaders paved the way to general-purpose computation on GPU (GPGPU). This paper introduces shaders by discussing the theory and practice. Introduction A shader is a piece of code that is executed on the Graphics Processing Unit (GPU), usually found on a graphics card, to manipulate an image before it is drawn to the screen. Shaders allow for various kinds of rendering effect, ranging from adding an X-Ray view to adding cartoony outlines to rendering output. The history of shaders starts at LucasFilm in the early 1980’s. LucasFilm hired graphics programmers to computerize the special effects industry [1]. This proved a success for the film/ rendering industry, especially at Pixars Toy Story movie launch in 1995. RenderMan introduced the notion of Shaders; “The Renderman Shading Language allows material definitions of surfaces to be described in not only a simple manner, but also highly complex and custom manner using a C like language. Using this method as opposed to a pre-defined set of materials allows for complex procedural textures, new shading models and programmable lighting. Another thing that sets the renderers based on the RISpec apart from many other renderers, is the ability to output arbitrary variables as an image—surface normals, separate lighting passes and pretty much anything else can be output from the renderer in one pass.” [1] The term shader was first only used to refer to “pixel shaders”, but soon enough new uses of shaders such as vertex and geometry shaders were introduced, making the term shaders more general.
    [Show full text]
  • CPU-GPU Benchmark Description
    UC San Diego UC San Diego Electronic Theses and Dissertations Title Heterogeneity and Density Aware Design of Computing Systems Permalink https://escholarship.org/uc/item/9qd6w8cw Author Arora, Manish Publication Date 2018 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA, SAN DIEGO Heterogeneity and Density Aware Design of Computing Systems A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science (Computer Engineering) by Manish Arora Committee in charge: Professor Dean M. Tullsen, Chair Professor Renkun Chen Professor George Porter Professor Tajana Simunic Rosing Professor Steve Swanson 2018 Copyright Manish Arora, 2018 All rights reserved. The dissertation of Manish Arora is approved, and it is ac- ceptable in quality and form for publication on microfilm and electronically: Chair University of California, San Diego 2018 iii DEDICATION To my family and friends. iv EPIGRAPH Do not be embarrassed by your failures, learn from them and start again. —Richard Branson If something’s important enough, you should try. Even if the probable outcome is failure. —Elon Musk v TABLE OF CONTENTS Signature Page . iii Dedication . iv Epigraph . v Table of Contents . vi List of Figures . viii List of Tables . x Acknowledgements . xi Vita . xiii Abstract of the Dissertation . xvi Chapter 1 Introduction . 1 1.1 Design for Heterogeneity . 2 1.1.1 Heterogeneity Aware Design . 3 1.2 Design for Density . 6 1.2.1 Density Aware Design . 7 1.3 Overview of Dissertation . 8 Chapter 2 Background . 10 2.1 GPGPU Computing . 10 2.2 CPU-GPU Systems .
    [Show full text]
  • Model System of Zirconium Oxide An
    First-principles based treatment of charged species equilibria at electrochemical interfaces: model system of zirconium oxide and titanium oxide by Jing Yang B.S., Physics, Peking University, China Submitted to the Department of Materials Science and Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHONOLOGY February 2020 © Massachusetts Institute of Technology 2020. All rights reserved. Signature of Author: Jing Yang Department of Materials Science and Engineering January 10th, 2020 Certified by: Bilge Yildiz Professor of Materials Science and Engineering And Professor of Nuclear Science and Engineering Thesis Supervisor Accepted by: Donald R. Sadoway John F. Elliott Professor of Materials Chemistry Chair, Department Committee on Graduate Studies 2 First-principles based treatment of charged species equilibria at electrochemical interfaces: model system of zirconium oxide and titanium oxide by Jing Yang Submitted to the Department of Materials Science and Engineering on Jan. 10th, 2020 in partial fulfillment of the requirements for the degree of Doctor of Philosophy Abstract Ionic defects are known to influence the magnetic, electronic and transport properties of oxide materials. Understanding defect chemistry provides guidelines for defect engineering in various applications including energy storage and conversion, corrosion, and neuromorphic computing devices. While DFT calculations have been proven as a powerful tool for modeling point defects in bulk oxide materials, challenges remain for linking atomistic results with experimentally-measurable materials properties, where impurities and complicated microstructures exist and the materials deviate from ideal bulk behavior. This thesis aims to bridge this gap on two aspects. First, we study the coupled electro-chemo-mechanical effects of ionic impurities in bulk oxide materials.
    [Show full text]
  • ATI Radeon Driver for Plan 9 Implementing R600 Support
    Introduction Radeon Specifics Plan 9 Specifics Conclusion ATI Radeon Driver for Plan 9 Implementing R600 Support Sean Stangl ([email protected]) 15-412, Carnegie Mellon University October 23, 2009 1 Introduction Radeon Specifics Plan 9 Specifics Conclusion Introduction Chipset Schema Project Goal Radeon Specifics Available Documentation ATOMBIOS Command Processor Plan 9 Specifics Structure of Plan 9 Graphics Drivers Conclusion Figures and Estimates Questions 2 Introduction Radeon Specifics Plan 9 Specifics Conclusion Chipset Schema Radeon Numbering System I ATI has released many cards under the Radeon label. I Modern cards are prefixed with "HD". Rough Mapping from Chipset to Marketing Name R200 : Radeon {8500, 9000, 9200, 9250} R300 : Radeon {9500, 9600, 9700, 9800} R420 : Radeon {X700, X740, X800, X850} R520 : Radeon {X1300, X1600, X1800, X1900} R600 : Radeon HD {2400, 3600, 3800, 3870 X2} R700 : Radeon HD {4300, 4600, 4800, 4800 X2} 3 I R520 introduces yet another new shader model. I ATI develops ATOMBIOS, a collection of data tables and scripts stored in the ROM on each card. I R600 supports the Unified Shader Model. I The 2D engine gets unified into the 3D engine. I The register specification is completely different. I R700 is an optimized R600. Introduction Radeon Specifics Plan 9 Specifics Conclusion Chipset Schema Notable Chipset Deltas Each family roughly coincides with a DirectX version bump. I R200, R300, and R420 use a similar architecture. I Each family changes the pixel shader. 4 I R600 supports the Unified Shader Model. I The 2D engine gets unified into the 3D engine. I The register specification is completely different.
    [Show full text]
  • 04-Prog-On-Gpu-Schaber.Pdf
    Seminar - Paralleles Rechnen auf Grafikkarten Seminarvortrag: Übersicht über die Programmierung von Grafikkarten Marcus Schaber 05.05.2009 Betreuer: J. Kunkel, O. Mordvinova 05.05.2009 Marcus Schaber 1/33 Gliederung ● Allgemeine Programmierung Parallelität, Einschränkungen, Vorteile ● Grafikpipeline Programmierbare Einheiten, Hardwarefunktionalität ● Programmiersprachen Übersicht und Vergleich, Datenstrukturen, Programmieransätze ● Shader Shader Standards ● Beispiele Aus Bereich Grafik 05.05.2009 Marcus Schaber 2/33 Programmierung Einschränkungen ● Anpassung an Hardware Kernels und Streams müssen erstellt werden. Daten als „Vertizes“, Erstellung geeigneter Fragmente notwendig. ● Rahmenprogramm Programme können nicht direkt von der GPU ausgeführt werden. Stream und Kernel werden von der CPU erstellt und auf die Grafikkarte gebracht 05.05.2009 Marcus Schaber 3/33 Programmierung Parallelität ● „Sequentielle“ Sprachen Keine spezielle Syntax für parallele Programmierung. Einzelne shader sind sequentielle Programme. ● Parallelität wird durch gleichzeitiges ausführen eines Shaders auf unterschiedlichen Daten erreicht ● Hardwareunterstützung Verwaltung der Threads wird von Hardware unterstützt 05.05.2009 Marcus Schaber 4/33 Programmierung Typische Aufgaben ● Geeignet: Datenparallele Probleme Gleiche/ähnliche Operationen auf vielen Daten ausführen, wenig Kommunikation zwischen Elementen notwendig ● Arithmetische Dichte: Anzahl Rechenoperationen / Lese- und Schreibzugiffe ● Klassisch: Grafik Viele unabhängige Daten: Vertizes, Fragmente/Pixel Operationen:
    [Show full text]
  • 1 Títol: Aceleración Con CUDA De Procesos 3D Volum
    84 mm Títol: Aceleración con CUDA de Procesos 3D Volum: 1/1 Alumne: Jose Antonio Raya Vaquera Director/Ponent: Enric Xavier Martin Rull 55 mm Departament: ESAII Data: 26/01/2009 1 2 DADES DEL PROJECTE Títol del Projecte: Aceleración con CUDA de procesos 3D Nom de l'estudiant: Jose Antonio Raya Vaquera Titulació: Enginyeria en Informàtica Crèdits: 37.5 Director/Ponent: Enric Xavier Martín Rull Departament: ESAII MEMBRES DEL TRIBUNAL (nom i signatura) President: Vocal: Secretari: QUALIFICACIÓ Qualificació numèrica: Qualificació descriptiva: Data: 3 4 ÍNDICE Índice de figuras ............................................................................................................... 9 Índice de tablas ............................................................................................................... 12 1. Introducción ............................................................................................................ 13 1.1 Motivación ....................................................................................................... 13 1.2 Objetivos .......................................................................................................... 14 2. Antecedentes ........................................................................................................... 17 3. Historia .................................................................................................................... 21 3.1 Evolución de las tarjetas gráficas ....................................................................
    [Show full text]
  • HP Z800 Workstation Overview
    QuickSpecs HP Z800 Workstation Overview HP recommends Windows Vista® Business 1. 3 External 5.25" Bays 2. Power Button 3. Front I/O: 3 USB 2.0, 1 IEEE 1394a, 1 Headphone out, 1 Microphone in DA - 13278 North America — Version 2 — April 13, 2009 Page 1 QuickSpecs HP Z800 Workstation Overview 4. Choice of 850W, 85% or 1110W, 89% Power Supplies 9. Rear I/O: 1 IEEE 1394a, 6 USB 2.0, 1 serial, PS/2 keyboard/mouse 5. 12 DIMM Slots for DDR3 ECC Memory 2 RJ-45 to Integrated Gigabit LAN 1 Audio Line In, 1 Audio Line Out, 1 Microphone In 6. 3 External 5.25” Bays 10. 2 PCIe x16 Gen2 Slots 7. 4 Internal 3.5” Bays 11.. 2 PCIe x8 Gen2, 1 PCIe x4 Gen2, 1 PCIe x4 Gen1, 1 PCI Slot 8. 2 Quad Core Intel 5500 Series Processors 12 3 Internal USB 2.0 ports Form Factor Rackable Minitower Compatible Operating Genuine Windows Vista® Business 32-bit* Systems Genuine Windows Vista® Business 64-bit* Genuine Windows Vista® Business 32-bit with downgrade to Windows® XP Professional 32-bit custom installed** Genuine Windows Vista® Business 64-bit with downgrade to Windows® XP Professional x64 custom installed** HP Linux Installer Kit for Linux (includes drivers for both 32-bit & 64-bit OS versions of Red Hat Enterprise Linux WS4 and WS5 - see: http://www.hp.com/workstations/software/linux) For detailed OS/hardware support information for Linux, see: http://www.hp.com/support/linux_hardware_matrix *Certain Windows Vista product features require advanced or additional hardware.
    [Show full text]
  • Nvidia's GPU Microarchitectures
    NVidia’s GPU Microarchitectures By Stephen Lucas and Gerald Kotas Intro Discussion Points - Difference between CPU and GPU - Use s of GPUS - Brie f History - Te sla Archite cture - Fermi Architecture - Kepler Architecture - Ma xwe ll Archite cture - Future Advances CPU vs GPU Architectures ● Few Cores ● Hundreds of Cores ● Lots of Cache ● Thousands of Threads ● Handful of Threads ● Single Proce ss Exe cution ● Independent Processes Use s of GPUs Gaming ● Gra phics ● Focuses on High Frames per Second ● Low Polygon Count ● Predefined Textures Workstation ● Computation ● Focuses on Floating Point Precision ● CAD Gra p hics - Billions of Polygons Brief Timeline of NVidia GPUs 1999 - World’s First GPU: GeForce 256 2001 - First Programmable GPU: GeForce3 2004 - Sca la ble Link Inte rfa ce 2006 - CUDA Architecture Announced 2007 - Launch of Tesla Computation GPUs with Tesla Microarchitecture 2009 - Fermi Architecture Introduced 2 0 13 - Kepler Architecture Launched 2 0 16 - Pascal Architecture Tesla - First microarchitecture to implement the unified shader model, which uses the same hardware resources for all fragment processing - Consists of a number of stream processors, which are scalar and can only operate on one component at a time - Increased clock speed in GPUs - Round robin scheduling for warps - Contained local, shared, and global memory - Conta ins Spe cia l-Function Units which are specialized for interpolating points - Allowed for two instructions to execute per clock cycle per SP Fermi Peak Performance Overview: ● Each SM has 32
    [Show full text]
  • Evaluating ATTILA, a Cycle-Accurate GPU Simulator
    Evaluating ATTILA, a cycle-accurate GPU simulator Miguel Ángel Martínez del Amor Department of Computer and Information Science Norwegian University of Science and Technology (NTNU) [email protected] Project supervisor: Lasse Natvig [email protected] 26 th January 2007 Abstract. As GPUs’ technology grow more and more, new simulators are needed to help on the task of designing new architectures. Simulators have several advantages compared to an implementation directly in hardware, so they are very useful in GPU development. ATTILA is a new GPU simulator that was born to provide a framework for working with real OpenGL applications, simulating at the same time a GPU that has an architecture similar to the current designs of the major GPU vendors like NVIDIA or ATI. This architecture is highly configurable, and also ATTILA gives a lot of statistics and information about what occurred into the simulated GPU during the execution. This project will explain the main aspects of this simulator, with an evaluation of this tool that is young but powerful and helpful for researchers and developers of new GPUs. 1. Introduction The main brain of computers is the CPU (Central Processing Unit), where the instructions are executed, manipulating by this way the data stored in memory. But with the new applications that demand even more resources, the CPU is becoming a bottleneck. There is a lot of works about how to improve the CPI (Cycles per Instruction) which is a good parameter for making comparisons between uniprocessor architectures, and the search for parallelism is the best way to do it.
    [Show full text]