FPGA Bootstrapping Using Partial Reconfiguration
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Brigham Young University BYU ScholarsArchive Theses and Dissertations 2011-09-28 FPGA Bootstrapping Using Partial Reconfiguration Patrick Sutton Ostler Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Ostler, Patrick Sutton, "FPGA Bootstrapping Using Partial Reconfiguration" (2011). Theses and Dissertations. 2878. https://scholarsarchive.byu.edu/etd/2878 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. FPGA Bootstrapping Using Partial Reconfiguration Patrick S. Ostler A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science Michael J. Wirthlin, Chair Brent E. Nelson Brad L. Hutchings Department of Electrical and Computer Engineering Brigham Young University December 2011 Copyright © 2011 Patrick S. Ostler All Rights Reserved ABSTRACT FPGA Bootstrapping Using Partial Reconfiguration Patrick S. Ostler Department of Electrical and Computer Engineering, BYU Master of Science Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents a generic bootstrap framework that can be used to construct a vari- ety of bootstrap designs. This thesis also discusses necessary PR design rules and techniques for bootstrap design creation. Additionally, this thesis presents two applications that demonstrate the feasibility of bootstrapping. One application is a bootstrap loader featuring a PCI Express end- point; this loader is capable of reconfiguring a subset of the hardware on an as-need basis. The other application is a prototype designed to demonstrate the bootstrapping for nonvolatile configu- ration memory reduction in space-bound payloads. While bootstrap design is more complex than standard FPGA designs, bootstrapping increases the flexibility and capability of FPGAs. Keywords: FPGA, partial reconfiguration, bootstrapping, PCI Express ACKNOWLEDGMENTS My sincerest thanks goes to Dr. Michael J. Wirthlin, my advisor and thesis chair. I am deeply grateful for the chance I have had to work under him these past three years, first as an undergraduate and later as a Master’s student. His direction, guidance, and support made this thesis possible. I want to thank Keith S. Morgan and Michael Caffrey at Los Alamos National Laboratory. Their respective mentorships allowed me learn many useful skills and placed me on the path of FPGA related research. I want to thank the fellow students in the Configurable Computing Lab at BYU. Their friendship and support eased the stress of my graduate workload. In addition, I want to highlight the contribution of Josh Jensen to this thesis. Thank you for the time and effort you devoted to this project. I also want thank Sandia National Laboratories, under the direction of the National Nuclear Security Administration, Office of Nonproliferation Research and Development, NA-22, and the NASA Rocky Mountain Space Grant Consortium for the funding of this work. Additionally, I want to thank Parimal Patel from the Xilinx Corporation University Program who provided software licenses for the Xilinx Partial Reconfiguration flow. These licenses were essential to the work described in this thesis. Last but not least, I want thank my parents, Michael H. and Vickie M. Ostler. Their en- couragment and support made if possible for me to achieve my educational goals. TABLE OF CONTENTS LIST OF TABLES ....................................... vi LIST OF FIGURES ...................................... viii Chapter 1 Introduction ................................... 1 1.1 Thesis Contributions . 2 1.2 Thesis Organization . 3 Chapter 2 Bootstrap Loading for FPGAs ......................... 5 2.1 Bootstrap Applications . 6 2.1.1 Providing Uninterrupted Communication Services . 6 2.1.2 Increasing Design Security . 7 2.1.3 Reducing Power-Up Configuration Time . 8 2.1.4 Reducing Nonvolatile Memory for Configuration Storage . 9 2.2 Active vs. Passive Bootstrapping . 10 2.3 Generic Bootstrap Design . 10 2.3.1 Communication Interface . 12 2.3.2 Reconfiguration Control . 13 2.3.3 Reconfigurable Partition Interface . 13 2.4 Summary . 13 Chapter 3 Partial Reconfiguration Design ........................ 15 3.1 Background . 15 3.2 PR Design Flow . 17 3.2.1 Design Entry . 17 3.2.2 Synthesis . 22 3.2.3 Implementation . 23 3.2.4 Device Programming . 25 3.3 PR Design Considerations . 26 3.3.1 PR Module State Initialization . 26 3.3.2 Disabling the GLUTMASK . 29 3.3.3 Region Placement . 30 3.3.4 Reconfigurable Partition Decoupling . 31 3.4 Reconfigurable Design Cost . 32 3.5 Summary . 33 Chapter 4 Bootstrapping with PCI Express ....................... 35 4.1 Related Work . 36 4.2 Static PCI Bootstrapping Design . 36 4.2.1 PCIe Interface . 37 4.2.2 Configuration Control . 38 4.2.3 Reconfigurable Partition Interface . 39 iv 4.2.4 Device Utilization . 41 4.3 PCI Express Driver and Application Code . 43 4.4 Application Examples . 43 4.4.1 Fast Fourier Transform (FFT) . 44 4.4.2 Advanced Encryption System (AES) . 44 4.4.3 Secure Hash Algorithm-1 (SHA-1) . 45 4.4.4 Blowfish . 45 4.4.5 Ogg Vorbis . 45 4.5 Summary . 46 Chapter 5 Bootstrapping with Scrubbing for Reducing Nonvolatile Memory Stor- age on Space-bound Payloads ......................... 49 5.1 Background . 49 5.2 Device Self-Scrubbing . 53 5.3 Bitstream Compression . 55 5.4 Prototype Bootstrap Design . 55 5.4.1 Static Design . 57 5.4.2 Reconfigurable Module . 58 5.4.3 Device Utilization . 60 5.5 Summary . 60 Chapter 6 Conclusion ................................... 63 REFERENCES ......................................... 65 Appendix A Reconfiguration of Xilinx Aurora Core around Static RocketIO Transceiver 69 A.1 The Aurora Core . 69 A.2 Core Modifications . 70 A.3 The Test Design . 70 A.4 Additional Notes . 72 Appendix B Double Error Correction of Configuration Frames through Partial Re- configuration .................................. 73 B.1 The PR/Scrub/DEC Module . 73 B.1.1 Host Operation . 75 B.1.2 Design Verification . 75 B.2 Reliability Model . 76 B.3 Estimating Improvement of DEC over SECDED . 77 B.3.1 MTTF of SECDED . 77 B.3.2 MTTF of DEC . 79 B.3.3 Improvement in DEC Method . 80 v LIST OF TABLES 3.1 Resource and Performance Comparison between Global and PR Builds for the PCIe-Bootstrap Design . 33 4.1 Resource utilization of bootstrap design on V5LX110T . 41 4.2 Reconfigurable Core Parameters . 44 B.1 MTTF and Improvement Calculations for Various Upset Rates . 80 vi vii LIST OF FIGURES 2.1 Bootstrap loading with asymmetric key cryptography . 7 2.2 Passive Bootstrap Configuration . 11 2.3 Block diagram of a generic bootstrap design . 12 3.1 Module-based Partial Reconfiguration . 16 3.2 The FPGA design flow . 18 3.3 The PR design flow . 19 3.4 Before and after diagram of refactored non-PR primitives . 21 3.5 PR synthesis and implementation procedures . 24 3.6 The initialization problem that occurs with PR . 27 3.7 An SRLC32E is roughly equivalent to 32 registers. 29 3.8 Vertical frame boundaries on a Virtex 5 FX70T, as seen in Xilinx PlanAhead . 31 3.9 Decoupling logic added to static design at the output of the RP . 32 4.1 PCI Express static bootstrap design . 37 4.2 The bootstrap design is constrained to a small region of the FPGA. 38 4.3 Reconfigurable partition interface . 40 4.4 The static bootstrap design as shown in Xilinx FPGA Editor . 42 4.5 A flowchart sequence for an example host program that interacts with a reconfig- urable design module . 47 4.6 The post place-and-route design layouts for the application examples as shown in Xilinx FPGA Editor: a) Fast Fourier Transform (FFT), b) Advanced Encryption System (AES), c) Secure Hash Algorithm-1 (SHA-1), d) Blowfish Encryption, and e) Ogg Vorbis audio decoder . 48 5.1 (a) A simple circuit programmed to a small portion of an FPGA operating in an error-free state; (b) The same circuit after the occurrence of two SEUs . 51 5.2 An example configuration frame for a Xilinx Virtex 5 FPGA in hexadecimal rep- resentation; ECC bits are highlighted . 54 5.3 The process for bitstream compression through frame removal, developed by Sell- ers, et. al. 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