Data Sheet Before the Capacitor Is Used

LTC1404 Complete SO-8, 12-Bit, 600ksps ADC with Shutdown

FEATURES DESCRIPTIO U ■ Complete 12-Bit ADC in SO-8 The LTC ®1404 is a complete 600ksps, 12-bit A/D con- ■ Single Supply 5V or ±5V Operation verter which draws only 75mW from 5V or ± 5V supplies. ■ Sample Rate: 600ksps This easy-to-use device comes complete with a 160ns ■ Power Dissipation: 75mW (Typ) sample-and-hold and a precision reference. Unipolar and ■ 72dB S/(N + D) and –80dB THD at Nyquist bipolar conversion modes add to the flexibility of the ADC. ■ No Missing Codes over Temperature The LTC1404 has two power saving modes: Nap and ■ Nap Mode with Instant Wake-Up: 7.5mW Sleep. In Nap mode, it consumes only 7.5mW of power ■ Sleep Mode: 60µW and can wake up and convert immediately. In the Sleep ■ High Impedance Analog Input mode, it consumes 60µW of power typically. Upon power- ■ Input Range (1mV/LSB): 0V to 4.096V or ± 2.048V up from Sleep mode, a reference ready (REFRDY) signal ■ Internal Reference Can Be Overdriven Externally is available in the serial data word to indicate that the ■ 3-Wire Interface to DSPs and Processors (SPI and reference has settled and the chip is ready to convert. TM

MICROWIRE Compatible) The LTC1404 converts 0V to 4.096V unipolar inputs from U a single 5V supply and ±2.048V bipolar inputs from ±5V APPLICATIO S supplies. Maximum DC specs include ±1LSB INL, ±1LSB ■ High Speed Data Acquisition DNL and 45ppm/°C full-scale drift over temperature. Guaranteed AC performance includes 69dB S/(N + D) ■ Digital Signal Processing ■ Multiplexed Data Acquisition Systems and –76dB THD at an input frequency of 100kHz over ■ Audio and Telecom Processing temperature. ■ Digital Radio The 3-wire serial port allows compact and efficient data ■ Spectrum Analysis transfer to a wide range of microprocessors, microcontrollers ■ Low Power and Battery-Operated Systems and DSPs. ■ Handheld or Portable Instruments , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO U

Single 5V Supply, 600kHz, 12-Bit Sampling A/D Converter Power Consumption vs Sample Rate 100 5V NORMAL CONVERSION + VCC VSS 10 10µF* 0.1µF NAP MODE BETWEEN CONVERSION LTC1404 MPU 1 ANALOG INPUT A (0V TO 4.096V) IN CONV P1.4 REF SLEEP MODE OUT V CLK P1.3 0.1 2.43V + REF BETWEEN CONVERSION 10 F 0.1 F GND D P1.2 µ µ OUT SUPPLY CURRENT (mA) SERIAL 0.01 DATA LINK 9.6MHz CLOCK *AVX TPSD106M035R0300 LTC1404 • TA01 0.001 0.01 0.1 1 10100 1k10k 100k 1M SAMPLE RATE (Hz)

LTC1404 • TA02

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ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATIONU (Notes 1, 2) TOP VIEW Supply Voltage (VCC) ...... 7V Negative Supply Voltage (VSS) ...... –6V to GND VCC 1 8 VSS Total Supply Voltage (VCC to VSS) AIN 2 7 CONV Bipolar Operation Only ...... 12V VREF 3 6 CLK Analog Input Voltage (Note 3) GND 4 5 DOUT

Unipolar Operation ...... –0.3V to (VCC + 0.3V) S8 PACKAGE 8-LEAD PLASTIC SO Bipolar Operation...... (VSS – 0.3V) to (VCC + 0.3V) T = 125°C, θ = 130°C/W Digital Input Voltage (Note 4) JMAX JA Unipolar Operation ...... –0.3V to 12V ORDER PART NUMBER S8 PART MARKING Bipolar Operation...... (VSS – 0.3V) to 12V Digital Output Voltage LTC1404CS8 1404 LTC1404IS8 1404I Unipolar Operation ...... –0.3V to (VCC + 0.3V) Bipolar Operation...... (VSS – 0.3V) to (VCC + 0.3V) Order Options Tape and Reel: Add #TR Power Dissipation...... 300mW Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Operating Ambient Temperature Range Lead Free Part Marking: http://www.linear.com/leadfree/ LTC1404C ...... 0°C to 70°C Consult LTC Marketing for parts specified with wider operating temperature ranges. LTC1404I...... –40°C to 85°C Junction Temperature...... 125°C Storage Temperature Range ...... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...... 300°C U

POWER REQUIRE EW TS The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Positive Supply Voltage Unipolar 4.75 5.25 V Bipolar 4.75 5.25 V VSS Negative Supply Voltage Bipolar Only –2.45 –5.25 V ICC Positive Supply Current fSAMPLE = 600ksps ● 15 30 mA Nap Mode ● 1.3 3.0 mA Sleep Mode ● 8.0 20.0 µA ISS Negative Supply Current fSAMPLE = 600ksps, VSS = – 5V ● 0.2 0.6 mA Nap Mode ● 0.2 0.5 mA Sleep Mode ● 410 µA PD Power Dissipation fSAMPLE = 600ksps ● 75 160 mW

Nap Mode ● 7.5 20 mW

Sleep Mode ● 60 150 µW U

A U ALOG I PUT The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range 4.75V ≤ VCC ≤ 5.25V (Unipolar) 0 to 4.096 V 4.75V ≤ VCC ≤ 5.25V, –5.25V ≤ VSS ≤ –2.45V (Bipolar) 0 to ±2.048 V IIN Analog Input Leakage Current During Conversions (Hold Mode) ● ±1 µA CIN Analog Input Capacitance Between Conversions (Sample Mode) 45 pF During Conversions (Hold Mode) 5 pF

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CO VERTERU CCHARA TERISTICS The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. With internal reference VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified (Note 6). PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) ● 12 Bits Integral Linearity Error (Note 7) ● ±1LSB Differential Linearity Error ● ±1LSB Offset Error (Note 8) ±6LSB ● ±8LSB Full-Scale Error ±15 LSB

Full-Scale Tempco IOUT(REF) = 0 ● ±10 ±45 ppm/°C W

DY AU IC ACCURACY The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, VSS = –5V, fSAMPLE = 600kHz. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N + D) Signal-to-Noise 100kHz Input Signal ● 69 72 dB 300kHz Input Signal 72 dB THD Total Harmonic Distortion 100kHz Input Signal ● –82 –76 dB Up to 5th Harmonic 300kHz Input Signal –80 dB Peak Harmonic or 100kHz Input Signal ● –84 –76 dB Spurious Noise 300kHz Input Signal –82 dB

IMD Intermodulation Distortion fIN1 = 99.17kHz, fIN2 = 102.69kHz –82 dB fIN1 = 298.68kHz, fIN2 = 304.83kHz –70 dB Full Power Bandwidth 5 MHz

Full Linear Bandwidth (S/(N + D) ≥ 68dB) 1 MHz UU

IU TER AL REFERE CE CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 2.410 2.430 2.450 V VREF Output Tempco IOUT = 0 ● ±10 ±45 ppm/°C VREF Line Regulation 4.75V ≤ VCC ≤ 5.25V 0.5 LSB/V –5.25V ≤ VSS ≤ 0V 0.01 LSB/V VREF Load Regulation 0 ≤ ⏐IOUT⏐ ≤ 1mA 1 LSB/mA

VREF Wake-Up Time from Sleep Mode CVREF = 10µF 2.5 ms U

DIGITAL I PUTSU AND OUTPUTS The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 5.25V ● 2.0 V VIL Low Level Input Voltage VCC = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VCC ● ±10 µA CIN Digital Input Capacitance 5pF VOH High Level Output Voltage VCC = 4.75V, IO = –10µA 4.7 V VCC = 4.75V, IO = –200µA ● 4.0 V VOL Low Level Output Voltage VCC = 4.75V, IO = 160µA 0.05 V VCC = 4.75V, IO = 1.6mA ● 0.10 0.4 V 1404fa 3

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IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VCC ● ±10 µA

COZ Hi-Z Output Capacitance DOUT 15 pF

ISOURCE Output Source Current VOUT = 0V – 10 mA

ISINK Output Sink Current VOUT = VCC 10 mA W

TI IU G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, unless otherwise noted specifications are at TA = 25°C. VCC = 5V, fSAMPLE = 600kHz, tr = tf = 5ns, unless otherwise specified. See Figures 12, 13, 14. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSAMPLE(MAX) Maximum Sampling Frequency ● 600 kHz tCONV Conversion Time fCLK = 9.6MHz 1.36 µs tACQ Acquisition Time (Unipolar Mode) 200 ns (Bipolar Mode VSS = –5V) 160 ns fCLK CLK Frequency ● 0.1 9.6 MHz tCLK CLK Pulse Width (Notes 5 and 10) ● 40 ns tWK(NAP) Time to Wake Up from Nap Mode 350 ns t1 CLK Pulse Width to Return to Active Mode ● 40 ns t2 CONV↑ to CLK↑ Setup Time ● 70 ns t3 CONV↑ After Leading CLK↑ ● 0ns t4 CONV Pulse Width (Note 9) ● 40 ns t5 Time from CLK↑ to Sample Mode 60 ns t6 Aperture Delay of Sample-and-Hold Jitter < 50ps 40 ns t7 Minimum Delay Between Conversion (Unipolar Mode) (Note 5) ● 220 310 ns (Bipolar Mode VSS = –5V) ● 180 300 ns t8 Delay Time, CLK↑ to DOUT Valid CLOAD = 20pF ● 40 70 ns t9 Delay Time, CLK↑ to DOUT Hi-Z CLOAD = 20pF ● 40 70 ns t10 Time from Previous Data Remains Valid After CLK↑ CLOAD = 20pF ● 10 30 ns t11 Minimum Time Between Nap/Sleep Request to Wake Up Request (Notes 5 and 10) ● 50 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Linearity, offset and full-scale specifications apply for unipolar and may cause permanent damage to the device. Exposure to any Absolute bipolar modes. Maximum Rating condition for extended periods may affect device Note 7: Integral nonlinearity is defined as the deviation of a code from a reliability and lifetime. straight line passing through the actual endpoints of the transfer curve. Note 2: All voltage values are with respect to GND. The deviation is measured from the center of the quantization band. Note 3: When these pin voltages are taken below VSS (ground for unipolar Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when mode) or above VCC, they will be clamped by internal diodes. This product the output code flickers between 0000 0000 0000 and 1111 1111 1111. can handle input currents greater than 60mA without latch-up if the pin is Note 9: The rising edge of CONV starts a conversion. If CONV returns low driven below VSS (ground for unipolar mode) or above VCC. at a bit decision point during the conversion, it can create small errors. For Note 4: When these pin voltages are taken below VSS (ground for unipolar best performance, ensure that CONV returns low either within 100ns after mode), they will be clamped by internal diodes. This product can handle the conversion starts (i.e., before the first bit decision) or after the 14 input currents greater than 60mA without latch-up if the pin is driven clock cycles. (Figure 13 Timing Diagram). below VSS (ground for unipolar mode). These pins are not clamped to VCC. Note 10: If this timing specification is not met, the device may not respond Note 5: Guaranteed by design, not subject to test. to a request for a conversion. To recover from this condition a NAP request is required.

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TYPICAL PERFORMANU CE CHARACTERISTICS

Unipolar Mode Differential Unipolar Mode Integral Bipolar Mode Differential Nonlinearity vs Output Code Nonlinearity vs Output Code Nonlinearity vs Output Code 1.00 1.00 1.00 fSAMPLE = 600kHz fSAMPLE = 600kHz fSAMPLE = 600kHz 0.75 0.75 0.75

0.50 0.50 0.50

0.25 0.25 0.25

0 0 0

–0.25 –0.25 –0.25

–0.50 –0.50 –0.50 INTEGRAL NONLINEARITY (LSBs)

DIFFERENTIAL NONLINEARITY (LSBs) –0.75 –0.75 DIFFERENTIAL NONLINEARITY (LSBs) –0.75

–1.00 –1.00 –1.00 0 512 2048 2560 4096 0 512 1024 1536 2048 2560 3072 3584 4096 –2048 –1024 0 1024 2048 1024 1536 3072 3584 –1536 –512 512 1536 OUTPUT CODE OUTPUT CODE OUTPUT CODE

1404 G01 1404 G02 1404 G03

Bipolar Mode Integral Unipolar Mode 4096 Nonaverage Unipolar Mode 4096 Nonaverage Nonlinearity vs Output Code FFT with 100kHz Signal FFT with 300kHz Signal 1.00 0 0 f = 600kHz f = 600kHz fSAMPLE = 600kHz –10 SAMPLE –10 SAMPLE 0.75 fIN = 99.1699kHz fIN = 298.681kHz –20 SINAD = 71dB –20 SINAD = 71dB 0.50 –30 THD = –77dB –30 THD = –73dB –40 –40 0.25 –50 –50 0 –60 –60 –70 –70 –0.25 AMPLITUDE (dB) –80 AMPLITUDE (dB) –80 –0.50 –90 –90

INTEGRAL NONLINEARITY (LSBs) –100 –100 –0.75 –110 –110 –1.00 –120 –120 –2048 –1024 0 1024 2048 –1536 –512 512 1536 030 60 90 120 150 180 210 240 270 300 030 60 90 120 150 180 210 240 270 300 OUTPUT CODE FREQUENCY (kHz) FREQUENCY (kHz)

1404 G04 1404 G05 1404 G06

Unipolar Mode Unipolar Mode Bipolar Mode ENOB and Signal/(Noise + Signal-to-Noise Ratio (Without Signal-to-Noise Ratio (Without Distortion) vs Input Frequency Harmonics) vs Input Frequency Harmonics) vs Input Frequency 12 74 80 80

11 68 SIGNAL/(NOISE + DISTORTION) (dB) 70 70 10 NYQUIST 62 FREQUENCY 9 56 60 60 8 50 50 50 7 6 40 40 5 30 30 4 3 20 20 EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE RATIO (dB) 2 SIGNAL-TO-NOISE RATIO (dB) 10 10 1 fSAMPLE = 600kHz fSAMPLE = 600kHz fSAMPLE = 600kHz 0 0 0 10 100 1000 10 100 1000 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 1404 G07 1404 G08 1404 G09

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TYPICAL PERFORMANU CE CHARACTERISTICS

Unipolar Mode Unipolar Mode Intermodulation Distortion vs Input Frequency Distortion Plot at 100kHz 0 0 fa fb fSAMPLE = 600kHz –10 fSAMPLE = 600kHz –10 fa = 99.16992188kHz –20 –20 fb = 102.6855469kHz –30 –30 –40 –40 –50 –50 –60 –60 –70

AMPLITUDE (dB) –80 2fa 2fb –70 2ND HARMONIC 2fa – fb –90 –80 THD –100 –90 3RD HARMONIC –110

AMPLITUDE (dB BELOW THE FUNDAMENTAL) –100 –120 10 100 1000 030 60 90 120 150 180 210 240 270 300 INPUT FREQUENCY (kHz) FREQUENCY (kHz)

1404 G10 1404 G11

Unipolar Mode Intermodulation Distortion Plot at 300kHz 0 f = 600kHz fa –10 SAMPLE fa = 298.6816406kHz fb –20 fb = 304.8339844kHz –30 –40 2fa + fb –50 3fa –60 2fb – fa –70 2fa fa + fb 3fb

AMPLITUDE (dB) –80 2fb –90 –100 –110 –120 020 40 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (kHz) 1404 G12

Bipolar Mode Intermodulation Distortion Plot at 300kHz 0 f = 600kHz fa –10 SAMPLE fa = 298.6816406kHz fb –20 fb = 304.8339844kHz –30 2fa + fb –40 3fa –50 2fa 2fb + fa –60 fa + fb 2fb – fa –70 fb – fa

AMPLITUDE (dB) –80 2fb 3fb –90 –100 –110 –120 020 40 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (kHz) 1404 G12

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TYPICAL PERFORMANU CE CHARACTERISTICS

Unipolar Mode S/(N + D) vs Input Bipolar Mode S/(N + D) vs Input Unipolar Mode Peak Harmonic or Frequency and Amplitude Frequency and Amplitude Spurious Noise vs Input Frequency 80 80 0 V = 0dB V = 0dB f = 600kHz IN IN –10 SAMPLE 70 70 –20 60 60 VIN = –20dB VIN = –20dB –30 50 50 –40

40 40 –50 –60 30 30 –70 20 20 VIN = –60dB VIN = –60dB –80 SIGNAL/(NOISE + DISTORTION) (dB) SIGNAL/(NOISE + DISTORTION) (dB) 10 10 –90 SPURIOUS-FREE DYNAMIC RANGE (dB) fSAMPLE = 600kHz fSAMPLE = 600kHz 0 0 –100 10 100 1000 10 100 1000 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 1404 G16 1404 G14 1404 G15

Bipolar Mode Peak Harmonic or Unipolar Mode Power Supply Bipolar Mode Power Supply Spurious Noise vs Input Frequency Feedthrough vs Ripple Frequency Feedthrough vs Ripple Frequency 0 0 0 f = 600kHz AIN = 0dB AIN = 0dB –10 SAMPLE –10 –10 AIN FREQUENCY = 100kHz AIN FREQUENCY = 100kHz –20 –20 fSAMPLE = 600kHz –20 fSAMPLE = 600kHz VCC (VRIPPLE = 1mV) –30 –30 –30 –40 –40 –40 –50 –50 –50 V (VRIPPLE = 10mV) –60 –60 –60 SS –70 –70 –70 –80 –80 –80 POWER SUPPLY FEEDTHROUGH (dB) –90 POWER SUPPLY FEEDTHROUGH (dB) –90 –90 VCC (VRIPPLE = 1mV) SPURIOUS-FREE DYNAMIC RANGE (dB) –100 –100 –100 10 100 1000 1 10 100 1000 1 10 100 1000 INPUT FREQUENCY (kHz) RIPPLE FREQUENCY (kHz) RIPPLE FREQUENCY (kHz)

1404 G17 1404 G18 1404 G19

Reference Voltage vs Acquisition Time vs Reference Voltage vs Temperature Load Current Source Impedance 2.440 2.45 4.0 TA = 25°C 2.438 3.5 2.44 2.436

s) 3.0

2.434 µ 2.43 2.5 2.432 2.430 2.42 2.0

2.428 1.5 2.41 2.426 ACQUISITION TIME ( 1.0 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 2.424 2.40 0.5 2.422 2.420 2.39 0 –50 –25 0 25 50 75 100 125 –8 –7–6 –5 –4 –3–2 –1 0 1 10 100 1k 10k TEMPERATURE (°C) LOAD CURRENT (mA) SOURCE RESISTANCE (Ω) 1404 G22 1404 G20 1404 G21

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TYPICAL PERFORMANU CE CHARACTERISTICS

Unipolar Mode VCC Supply Current Bipolar Mode Supply Current vs Temperature vs Temperature 20 15.0 300

12.5 250 V VCC CURRENT SS 15 SUPPLY CURRENT ( 10.0 200

VSS CURRENT 10 7.5 150

5.0 100 µ SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) A)

CC 5 CC V V 2.5 50 f = 600kHz SAMPLE fSAMPLE = 600kHz 0 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C)

1404 G23 1404 G24

PIN FUNCTIONSUUU

VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10µF CLK (Pin 6): Clock. This clock synchronizes the serial data tantalum in parallel with 0.1µF ceramic). transfer. A minimum CLK pulse of 40ns signals the ADC to wake up from Nap or Sleep mode. AIN (Pin 2): Analog Input. 0V to 4.096V (Unipolar), ±2.048V (Bipolar). CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK V (Pin 3): 2.43V Reference Output. Bypass to GND REF low and pulsing CONV two/four times will put the ADC into (10µF tantalum in parallel with 0.1µF ceramic). Nap/Sleep mode. GND (Pin 4): Ground. GND should be tied directly to an V (Pin 8): Negative Supply. –5V for bipolar operation. analog ground plane. SS Bypass to GND with 10µF tantalum in parallel with 0.1µF DOUT (Pin 5): The A/D conversion result is shifted out from ceramic. VSS should be tied to GND for unipolar operation. this pin.

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FUNCTIONALUU BLOCK DIAGRA

CSAMPLE ZEROING SWITCH

AIN VCC GND

VSS VREF

2.43V REF

12-BIT CAPACITIVE DAC COMP

CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER 1404 BD

TEST CIRCUITS

D OUT DOUT

3k C LOAD CLOAD

Hi-Z TO V OH Hi-Z TO VOL V TO V OL OH VOH TO VOL V TO Hi-Z OH VOL TO Hi-Z

1404 TC01

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APPLICATIONS INFORMATIOWU N Conversion Details Dynamic Performance The LTC1404 uses a successive approximation algorithm The LTC1404 has excellent high speed sampling capabil- and an internal sample-and-hold circuit to convert an ity. FFT (Fast Fourier Transform) test techniques are used analog signal to a 12-bit serial output based on a precision to test the ADC’s frequency response, distortion and noise internal reference. The control logic provides easy inter- at the rated throughput. By applying a low distortion sine face to microprocessors and DSPs through 3-wire con- wave and analyzing the digital output using an FFT algo- nections. rithm, the ADC’s spectral content can be examined for A rising edge on the CONV input starts a conversion. At the frequencies outside the fundamental. Figure 2a shows a start of a conversion the successive approximation regis- typical LTC1404 FFT plot. ter (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. 0 f = 600kHz –10 SAMPLE fIN = 99.169kHz During conversion, the internal 12-bit capacitive DAC –20 SINAD = 72dB output is sequenced by the SAR from the most significant –30 THD = –88dB –40 bit (MSB) to the least significant bit (LSB). Referring to –50 Figure 1, the AIN input connects to the sample-and-hold –60 capacitor during the acquired phase and the comparator –70 offset is nulled by the feedback switch. In this acquire AMPLITUDE (dB) –80 –90 phase, it typically takes 160ns for the sample-and-hold –100 capacitor to acquire the analog signal. During the convert –110 –120 phase, the comparator feedback switch opens, putting the 030 60 90 120 150 180 210 240 270 300 comparator into the compare mode. The input switches FREQUENCY (kHz) connect CSAMPLE to ground, injecting the analog input 1404 F02a charge onto the summing junction. This input charge is successively compared with the binary-weighted charges Figure 2a. LTC1404 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency in Bipolar Mode supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the 0 DAC output balances the A input charge. The SAR f = 600kHz IN –10 SAMPLE fIN = 298.681kHz contents (a 12-bit data word) which represent the input –20 SINAD = 71dB voltage, are presented through the serial pin DOUT. –30 THD = –84dB –40 –50 SAMPLE –60 –70 S1

C AMPLITUDE (dB) –80

SAMPLE SAMPLE – –90 AIN –100

COMP –110 HOLD DAC + –120 CDAC 030 60 90 120 150 180 210 240 270 300 FREQUENCY (kHz) S VDAC A 1404 F02b R Figure 2b. LTC1404 Nonaveraged, 4096 Point FFT DOUT Plot with 300kHz Input Frequency in Bipolar Mode 1404 F01

Figure 1. AIN Input

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APPLICATIONS INFORMATIOWU N Signal-to-Noise Ratio Total Harmonic Distortion The signal-to-noise plus distortion ratio [S/(N + D)] is the Total harmonic distortion (THD) is the ratio of the RMS ratio between the RMS amplitude of the fundamental input sum of all harmonics of the input signal to the fundamental frequency to the RMS amplitude of all other frequency itself. The out-of-band harmonics alias into the frequency components at the A/D output. The output is band limited band between DC and half of the sampling frequency. THD to frequencies from DC to half the sampling frequency. is expressed as: Figure 2a shows a typical spectral content with a 600kHz sampling rate and a 100kHz input. The dynamic perfor- VVV234222+++… Vn 2 THD = 20log mance is excellent for input frequencies up to the Nyquist V1 limit of 300kHz as shown in Figure 2b. where V1 is the RMS amplitude of the fundamental fre- Effective Number of Bits quency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is The effective number of bits (ENOBs) is a measurement of shown in Figure 4. The LTC1404 has good distortion the effective resolution of an ADC and is directly related to performance up to the Nyquist frequency and beyond. the S/(N + D) by the equation: SN/–.()+ D 176 N = 0 f = 600kHz 602. –10 SAMPLE where N is the effective number of bits of resolution and –20 S/(N + D) is expressed in dB. At the maximum sampling –30 rate of 600kHz, the LTC1404 maintains very good ENOBs –40 –50 up to the Nyquist input frequency of 300kHz (refer to –60 Figure 3). –70 3RD HARMONIC THD –80 2ND HARMONIC 12 74 –90

11 68 SIGNAL/(NOISE + DISTORTION) (dB) NYQUIST AMPLITUDE (dB BELOW THE FUNDAMENTAL) –100 10 62 FREQUENCY 10k 100k 1M 9 56 INPUT FREQUENCY (Hz) 8 50 1404 F04 7 6 Figure 4. Distortion vs Input Frequency in 5 Bipolar Mode 4 3 EFFECTIVE NUMBER OF BITS 2 Intermodulation Distortion 1 fSAMPLE = 600kHz 0 If the ADC input signal consists of more than one spectral 10k 100k 1M INPUT FREQUENCY (Hz) component, the ADC transfer function nonlinearity can 1404 F03 produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by Figure 3. Effective Bits and Signal-to-Noise + Distortion vs Input Frequency in Bipolar Mode the presence of another sinusoidal input at a different frequency.

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APPLICATIONS INFORMATIOWU N If two pure sine waves of frequencies fa and fb are applied LTC1404 has been designed to optimize input bandwidth, to the ADC input, nonlinearities in the ADC transfer func- allowing the ADC to undersample input signals with fre- tion can create distortion products at sum and difference quencies above the converter’s Nyquist Frequency. The frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. noise floor stays very low at high frequencies; S/(N + D) For example, the 2nd order IMD terms include (fa + fb) and becomes dominated by distortion at frequencies far be- (fa – fb) while the 3rd order IMD terms includes (2fa + fb), yond Nyquist. (2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the Driving the Analog Input 2nd order IMD products can be expressed by the following The analog input of the LTC1404 is easy to drive. It draws formula. only one small current spike while charging the sample- Amplitude at (fa± fb ) and-hold capacitor at the end of a conversion. During IMD fa± fb = 20log () Amplitude at fa conversion, the analog input draws only a small leakage current. The only requirement is that the amplifier driving Figure 5 shows the IMD performance at a 100kHz input. the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles 0 fa fb in 160ns to small load current transient will allow maxi- –10 fSAMPLE = 600kHz fa = 99.16992188kHz mum speed operation. If a slower op amp is used, more –20 fb = 102.6855469kHz –30 settling time can be provided by increasing the time –40 between conversions. Suitable devices capable of driving –50 ® –60 the ADC’s AIN input include the LT 1360 and the LT1363 2fa + fb –70 op amps. fa + fb 3fa

AMPLITUDE (dB) –80 2fa – fb 2fb – fa 2fa 2fb 2fb + fa –90 3fb The LTC1404 comes with a built-in unipolar/bipolar detec- –100 tion circuit. If the VSS potential is forced below GND, the –110 internal circuitry will automatically switch to bipolar mode. –120 020 40 60 80 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (kHz) The following list is a summary of the op amps that are 1404 F05 suitable for driving the LTC1404, more detailed informa- Figure 5. Intermodulation Distortion Plot in Bipolar Mode tion is available in the Linear Technology databooks or the Linear Technology Web site. LT 1215/LT1216: Dual and quad 23MHz, 50V/µs single Peak Harmonic or Spurious Noise supply op amps. Single 5V to ±15V supplies, 6.6mA The peak harmonic or spurious noise is the largest spec- specifications, 90ns settling to 0.5LSB. tral component excluding the input signal and DC. This LT1223: 100MHz video current feedback amplifier. ±5V value is expressed in decibels relative to the RMS value of to ±15V supplies, 6mA supply current. Low distortion up a full-scale input signal. to and above 600kHz. Low noise. Good for AC applications. Full Power and Full Linear Bandwidth LT1227: 140MHz video current feedback amplifier. ±5V The full power bandwidth is the input frequency at which to ±15V supplies, 10mA supply current. Lowest distor- the amplitude of the reconstructed fundamental is re- tion at frequencies above 600kHz. Low noise. Best for AC duced by 3dB for a full-scale input signal. applications. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The

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APPLICATIONS INFORMATIOWU N LT1229/LT1230: Dual and quad 100MHz current feedback 5V INPUT RANGE ±4.215V amplifiers. ±2V to ±15V supplies, 6mA supply current A VCC (= ±0.843 • VREF) IN each amplifier. Low noise. Good AC specs. 10V LTC1404 LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V VIN VOUT VREF supplies. 3.8mA supply current. Good AC and DC specs. 3Ω 70ns settling to 0.5LSB. LT1019A-5 10µF GND LT1363: 50MHz, 450V/µs op amps. ±5V to ±15V supplies. GND VSS 6.3mA supply current. Good AC and DC specs. 60ns 1404 F07 –5V settling to 0.5LSB. LT1364/LT1365: Dual and quad 50MHz, 450V/ s op amps. µ Figure 7. Supplying a 5V Reference Voltage to the ±5V to ±15V supplies, 6.3mA supply current per amplifier. LTC1404 with the LT1019A-5 60ns settling to 0.5LSB.

Internal Reference drift (equal to the maximum 5ppm/°C of the LT1019A-5) The LTC1404 has an on-chip, temperature compensated, and a ±4.215V full scale. If VREF is forced lower than curvature corrected, bandgap reference, which is factory 2.43V, the REFRDY bit in the serial data output will be trimmed to 2.43V. It is internally connected to the DAC and forced to low. is available at Pin 3 to provide up to 1mA of current to an external load. For minimum code transition noise, the UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT reference output should be decoupled with a capacitor to Figure 8 shows the ideal input/output characteristics for filter wideband noise from the reference (10 F tantalum in µ the LTC1404. The code transitions occur midway between parallel with a 0.1 F ceramic). The V pin can be driven µ REF successive integer LSB values (i.e., 0.5LSB, 1.5LSB, with a DAC or other means to provide input span adjust- 2.5LSB, … FS – 1.5LSB). The output code is straight ment in bipolar mode. The V pin must be driven to at REF binary with 1LSB = 4.096V/4096 = 1mV. Figure 9 shows least 2.46V to prevent conflict with the internal reference. the input/output transfer characteristics for the bipolar The reference should not be driven to more than 5V. mode in two’s complement format. Figure 6 shows an LT1360 op amp driving the reference pin. Figure 7 shows a typical reference, the LT1019A-5 Unipolar Offset and Full-Scale Error Adjustments connected to the LTC1404. This will provide an improved In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Figure 5V 10a shows the extra components required for full-scale INPUT RANGE V AIN CC ±0.843 • VREF(OUT) error adjustment. Figure 10b shows offset and full-scale adjustment. Offset error must be adjusted before full- + LTC1404 VREF(OUT) ≥ 2.46V scale error. Zero offset is achieved by applying 0.5mV (i.e., LT1360 VREF 0.5LSB) at the input and adjusting the offset trim until the – 3Ω LTC1404 output code flickers between 0000 0000 0000 10µF and 0000 0000 0001. For zero full-scale error, apply an GND VSS analog input of 4.0945V (FS – 1.5LSB or last code transi- 1404 F06 –5V tion) at the input and adjust R5 until the LTC1404 output code flickers between 1111 1111 1110 and 1111 1111

Figure 6. Driving the VREF with the LT1360 Op Amp 1111.

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APPLICATIONS INFORMATIOWU N

R1 FS 4.096 111...111 1LSB = = ANALOG 10k 4096 4096 INPUT + 111...110 0V TO 4.096V A1 A 111...101 R2 IN 10k 111...100 10k – R4 5V 100k R9 LTC1404 20Ω R5 4.3k

OUTPUT CODE UNIPOLAR FULL-SCALE ZERO 000...011 ADJUST 000...010 R3 5V 000...001 R7 R8 100k 100k 000...000 10k 0V 1 FS – 1LSB OFFSET LSB R6 ADJUST INPUT VOLTAGE (V) 400Ω 1404 F08

1404 F10b

Figure 8. LTC1404 Unipolar Transfer Characteristics Figure 10b. LTC1404 Offset and Full-Scale Adjust Circuit

R1 ANALOG 10k 011...111 INPUT + ±2.048V R2 011...110 BIPOLAR A1 A ZERO 10k IN – R4 000...001 100k LTC1404 000...000 R5 111...111 4.3k FULL-SCALE

OUTPUT CODE 111...110 ADJUST

100...001 R3 R7 5V 100k R8 100...000 100k 20k OFFSET –FS/2 –1 0V 1 FS/2 – 1LSB R6 ADJUST LSB LSB 200Ω –5V INPUT VOLTAGE (V) 1404 F10c 1404 F09

Figure 9. LTC1404 Bipolar Transfer Characteristics Figure 10c. LTC1404 Bipolar Offset and Full-Scale Adjust Circuit

R1 50Ω VIN + Bipolar Offset and Full-Scale Error Adjustments A1 AIN Bipolar offset and full-scale errors are adjusted in a similar – R2 R4 fashion to the unipolar case. Bipolar offset error adjust- 10k 100Ω LTC1404 ment is achieved by applying an input voltage of –0.5mV R3 (–0.5LSB) to the input in Figure 10c and adjusting the op 10k FULL-SCALE amp until the ADC output code flickers between 0000 0000 ADJUST GND 0000 and 1111 1111 1111. For full-scale adjustment, an

ADDITIONAL PINS OMITTED FOR CLARITY 1404 F10a input voltage of 2.0465V (FS – 1.5LSBs) is applied to the ±20LSB TRIM RANGE input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. Figure 10a. LTC1404 Full-Scale Adjust Circuit

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LTC1404

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APPLICATIONS INFORMATIOWU N BOARD LAYOUT AND BYPASSING Figure 11 shows the recommended system ground con- To obtain the best performance from the LTC1404, a nections. All analog circuitry grounds should be termi- printed circuit board is required. Layout for the printed nated at the LTC1404 GND pin. The ground return from the circuit board should ensure that digital and analog signal LTC1404 Pin 4 to the power supply should be low imped- lines are separated as much as possible. In particular, care ance for noise free operation. Digital circuitry grounds should be taken not to run any digital traces alongside an must be connected to the digital supply common. As an analog signal trace or underneath the ADC. The analog alternative, instead of a direct short between the digital and input should be screened by GND. analog circuitry, a 10Ω or a ferrite bead jumper helps reduce the digital noise. High quality 10µF surface mount AVX capacitor with a 0.1µF ceramic should be used at the VCC, VSS and VREF pins. For better results, another 10µF AVX capacitor can be ANALOG SUPPLY DIGITAL SUPPLY added to the VCC pin. At 600ksps, the CLK frequency can –5V GND 5V GND 5V be as high as 9.6MHz. A poor quality capacitor can lose more than 80% of its capacitance at this frequency range. Therefore, it is important to consult the manufacturer’s + + + data sheet before the capacitor is used. For the LTC1404, at 600ksps, every bit decision must be determined within 104ns (9.6MHz). During this short time interval, the V GND V GND V supply disturbance due to a CLK transition needs to settle. SS CC CC The ADC must update its DAC, make a comparator deci- LTC1404 DIGITAL CIRCUITRY sion based on sub-mV overdrive, latch the new DAC 1404 F11 information and output the serial data. This ADC provides Figure 11. Power Supply Connection one power supply, VCC, which is connected to both the internal analog and digital circuitry. Any ringing due to poor supply or reference bypassing, inductive trace runs, In applications where the ADC data outputs and control CLK and CONV over- or undershoot, or unnecessary D OUT signals are connected to a continuously active micropro- loading can cause ADC errors. Therefore, the bypass cessor bus, it is possible to get errors in the conversion capacitors must be located as close to the pins as possible. results. These errors are due to feedthrough from the The traces connecting the pins and the bypass capacitors microprocessor to the successive approximation com- must be kept short and should be made as wide as parator. The problem can be eliminated by forcing the possible. In unipolar mode operation, V must be con- SS microprocessor into a Wait state during conversion or by nected to the GND pin directly. using three-state buffers to isolate the ADC data bus. Input signal leads to AIN and signal return leads from GND (Pin 4) should be kept as short as possible to minimize Power-Down Mode noise coupling. In applications where this is not possible, Upon power-up, the LTC1404 is initialized to the active a shielded cable between the analog input signal and the state and is ready for conversion. However, the chip can be ADC is recommended. Also, any potential difference in easily placed into Nap or Sleep mode by exercising the grounds between the analog signal and the ADC appears right combination of CLK and CONV signals. In Nap mode, as an error voltage in series with the analog input signal. all power is off except for the internal reference, which is Attention should be paid to reducing the ground circuit still active and provides 2.43V output voltage to the other impedance as much as possible. circuitry. In this mode, the ADC draws only 7.5mW of power instead of 75mW (for minimum power, the logic

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LTC1404

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APPLICATIONS INFORMATIOWU N inputs must be within 500mV of the supply rails). In Sleep version will result in an all-zero output code, including the mode, power consumption is reduced to 60µW by cutting REFRDY bit. If no conversion is attempted, the DOUT pin off power to all internal circuitry including the reference. remains in a high impedance state. If the ADC wakes from Figure 12 illustrates power-down modes for the LTC1404. Sleep mode, this can be determined by monitoring the The chip enters Nap mode by keeping the CLK signal low state of the REFRDY bit at the DOUT pin. and pulsing the CONV signal twice. For Sleep mode operation, the CONV signal should be pulsed four times DIGITAL INTERFACE while CLK is kept low. Nap and Sleep modes are activated on the falling edge of the CONV pulse. The digital interface requires only three digital lines. CLK and CONV are both inputs, and the DOUT output provides The LTC1404 returns to active mode easily. The rising the conversion result in serial form. edge of CLK wakes up the LTC1404. From Nap mode, wake-up occurs within 350ns. During the transition from Figure 13 shows the digital timing diagram of the LTC1404 during the A/D conversion. The CONV rising edge starts Sleep mode to active mode, the VREF voltage ramp-up time is a function of its loading conditions. With a 10µF bypass the conversion. Once initiated, it can not be restarted until capacitor, the wake-up time from Sleep mode is typically the conversion is completed. If the time from CONV signal 2.5ms. A REFRDY signal is activated once the reference to CLK rising edge is less than t2, the digital output will be has settled and is ready for an A/D conversion. This delayed by one clock cycle. REFRDY bit is sent to the DOUT pin as the first bit followed The digital output data is updated on the rising edge of the by the 12-bit data word (refer to Figure 13). To save power CLK line. The digital output data consists of a REFRDY bit during wake-up from Sleep mode, the chip is designed to followed by a valid 12-bit data word. DOUT data should be enter Nap mode automatically until the reference is ready. captured by the receiving system on the rising CLK edge. Once REFRDY goes high, the comparator powers up Data remains valid for a minimum time of t10 after the immediately and is ready for a conversion. During the Nap rising CLK edge to allow capture to occur. interval, any attempt to perform an analog-to-digital con-

t1 t1

CLK

t11 t11

CONV

NAP

SLEEP

VREF

REFRDY REFRDY = 1 REFRDY = 0 Hi-Z Hi-Z Hi-Z Hi-Z ALL ZERO 1 11 10 10 DOUT REFRDY BIT+12-BIT REFRDY BIT NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. DATA WORD +12-BIT REFRDY APPEARS AS THE FIRST BIT IN THE DOUT WORD DATA WORD

1404 F12 Figure 12. Nap Mode and Sleep Mode Waveforms 1404fa 16

LTC1404

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APPLICATIONS INFORMATIOWU N

t7 t3 1234567891011121314 15 16 1 2 CLK

t4 t5

CONV

t6 tACQ INTERNAL SAMPLE HOLDSAMPLE HOLD S/H STATUS

t8 Hi-Z Hi-Z DOUT REFRDY D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 REFRDY

REFRDY BIT + 12-BIT DATA WORD

tCONV

1404 F13 tSAMPLE

Figure 13. ADC Digital Timing Diagram

CLK VIH CLK VIH

t8 t9 t10 VOH 90%

DOUT DOUT

VOL 10%

1404 F14

Figure 14. CLK to DOUT Delay

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TYPICAL APPLICATIONU S

Hardware Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX)

7.8MHz TMS320C50-40MHZ EXTERNAL CLOCK 5V TCLKX 1 6 VCC CLK TCLKR TFSX UNIPOLAR 2 7 + A CONV TFSR INPUT IN 10µF 0.1µF LTC1404 3 5 VREF DOUT TDR

+ VSS GND 10µF 0.1µF 84 1404 TA04a

Logic Analyzer Waveforms Show 2.05µs Throughput Rate (Input Voltage = 1.606V, Output Code = 0110 0100 0110 = 160610)

NOTE: THE TMS320C50-40MHz HAS A LIMITED SERIAL PORT CLOCK SPEED OF 7.8MHz. TO ALLOW THE LTC1404 TO RUN AT 1404T A04B ITS MAXIMUM SPEED OF 9.6MHz, THE TMS320C50-57 OR TMS320C50-80MHz IS NEEDED

Data from the LTC1404 Loaded into the TMS320C50’s TRCV Register

X RDY D11 D10 D9 D8 D7 D6 D5D4 D3 D2 D1 D0 X X

1404 TA04c

Data Stored in the TMS320C50’s Memory (in Right Justified Format)

0 0 0 RDY D11 D10 D9 D8 D7D6 D5 D4 D3 D2 D1 D0

1404 TA04d

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TYPICAL APPLICATIONU S

TMS320C50 Code for Circuit

THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO THE *Start Serial Communication* TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX. SACL TDXR ; Generate frame sync pulse DATA SHIFT CLOCK IS EXTERNALLY GENERATED. SPLK #040h, IMR ; Turn on TRNT receiver interrupt *Initialization* CLRC INTM ; Enable interrupt .mmregs ; Defines global symbolic names CLRC SXM ; For Unipolar input, set for right shift ;- - Initialized data memory to zero ; with no sign extension .ds 0F00h ; Initialize data to zero MAR *, AR7 ; Load the auxiliary register pointer with seven DATA0 .word 0 ; Begin sample data location LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h DATA1 .word 0 ; . ; as the begin address for data storage DATA2 .word 0 ; Location of data WAIT: NOP ; Wait for a receive interrupt DATA3 .word 0 ; . NOP ; DATA4 .word 0 ; . NOP ; DATA5 .word 0 ; End sample data location SACL TDXR ; !! Regenerate the frame sync pulse ;- - Set up the ISR vector B WAIT ; .ps 080Ah ; Serial ports interrupts ; ------end of main program ------; rint : B RECEIVE ; 0A; *Receiver Interrupt Service Routine* xint : B TRANSMIT ; 0C; TREC: trnt : B TREC ; 0E; LAMM TRCV ; Load the data received from LTC1404 txnt : B TTRANX ; 10; SFR ; Shift right two times ;- - Setup the reset vector SFR ; .ps 0A00h AND #1FFFh, 0 ; ANDed with #1FFFh .entry ; For converting the data to right START: ; justified format *TMS320C50 Initialization* ; SETC INTM ; Temporarily disable all interrupts SACL *+, 0 ; Write to data memory pointed by AR7 and LDP #0 ; Set data page pointer to zero ; increase the memory address by one OPL #0834h, PMST ; Set up the PMST status and control register LACC AR7 ; LACC #0 SUB #0F05h,0 ; Compare to end sample address #0F05h SAMM CWSR ; Set software wait state to 0 BCND END_TRCV, GEQ ; If the end sample address has exceeded jump SAMM PDWSR ; to END_TRCV ; *Configure Serial Port* SPLK #040h, IMR ; Else Re-enable the TRNT receive interrupt SPLK #0028h, TSPC ; Set TDM Serial Port RETE ; Return to main program and enable interrupt ; TDM = 0 Stand Alone mode ; DLB=0 Not loop back *After Obtained the Data from LTC1404, Program Jump to END_TRCV* ; FO=0 16 Bits END_TRCV: ; FSM=1 Burst Mode SPLK #002h, IMR ; Enable INT2 for program to halt ; MCM=0 CLKR is generated externally CLRC INTM ; TXM=1 FSX as output pin SUCCESS: ; Put serial port into reset B SUCCESS ; (XRST=RRST=0) *Fill the Unused Interrupt with RETE, to avoid program get “lost”* SPLK #00E8h, TSPC ; Take Serial Port out of reset TTRANX: ; (XRST=RRST=1) RETE SPLK #0FFFFh, IFR ; Clear all the pending interrupts RECEIVE: RETE TRANSMIT: RETE INT2: B halt ; Halts the running CPU

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TYPICAL APPLICATIONU S

LTC1404 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0)

9.6MHz 5V EXTERNAL CLOCK ADSP2181 1 6 VCC CLK SCLKO UNIPOLAR 2 7 + A CONV RFSO INPUT IN 10µF 0.1µF LTC1404 3 5 VREF DOUT DR0

+ VSS GND 10µF 0.1µF 84 1404 TA05a

Logic Analyzer Waveforms Show 1.67µs Throughput Rate (Input Voltage = 1.604V, Output Code = 0110 0100 0100 = 160410)

NOTE: WITHOUT THE EXTERNAL CLOCKING SIGNAL, THE ADSP2181 SCLK0 CAN BE PROGRAMMED TO RUN AT 8.3MHz 1404 TA05b

Data from the LTC1404 (Normal Mode)

X RDY D11 D10 D9 D8 D7 D6 D5D4 D3 D2 D1 D0 X X

1404 TA05c

Data Stored in the ADSP2181’s Memory (Normal Mode, SLEN = D)

0 0 0 RDY D11 D10 D9 D8 D7D6 D5 D4 D3 D2 D1 D0

1404 TA05d

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TYPICAL APPLICATIONU S

ADSP2181 Code for Circuit

THIS PROGRAM DEMONSTRATES THE LTC1404 INTERFACE TO /*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/ THE ADSP-2181. FRAME SYNC PULSE IS GENERATED FROM RFS. /*Using an external clock source=9.6MHz*/ DATA SHIFT CLOCK IS EXTERNALLY GENERATED. /*Does not need to configure CLKDIV*/ /*Section 1: Initialization*/ /*to Configure RFSDIV*/ .module/ram/abs = 0 adspltc; /*define the program module*/ ax0 = 15; /*set the RFSDIV reg = 15*/ jump start; /*jump over interrupt vectors*/ /*=> the frame sync pulse for every 16 SCLK*/ nop; nop; nop; /*if frame sync pulse in every 15 SCLK, ax0=14*/ rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ dm(0x3FF4) =ax0; rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ /*to setup interrupt*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ ifc= 0x0066; /*clear any extraneous SPORT interrupts*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 TX int*/ icntl= 0; /*IRQXB = level sensitivity*/ ax0 = rx0; /*Section 5*/ /*disable nesting interrupt*/ dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ rti; /* */ /*bit 1 = SPORT1 or IRQ0B int = 0*/ /* */ /*bit 2 = SPORT1 or IRQ1B int = 0*/ /*end of SPORT0 receive interrupt*/ /*bit 3 = BDMA int = 0*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ /*bit 4 = IRQEB int = 0*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ /*bit 5 = SPORT0 receive int = 1*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 TX (IRQ1) int*/ /*bit 6 = SPORT0 transmit int = 0*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 RX (IRQ0) int*/ /*bit 7 = IRQ2B int = 0*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ /*enable SPORT0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon POWER DOWN int*/ /*Section 4: Configure System Control Register and Start Communication*/ /*Section 2: Configure SPORT0*/ /*to configure system control reg*/ start: ax0 = dm(0x3FFF); /*read the system control reg*/ /*to configure SPORT0 control reg*/ ay0 = 0xFFF0; /*SPORT0 address = 0X3FF6*/ ar = ax0 AND ay0; /*set wait state to zero*/ /*RFS is used for frame sync generation*/ ay0 = 0x1000; /*RFS is internal, TFS is not used*/ ar = ar OR ay0; /*bit 12 = 1, enable SPORT0*/ /*bit 0-3 = Slen*/ dm(0x3FFF) = ar; /*F = 15 = 1111*/ /*frame sync pulse regenerated automatically*/ /*E = 14 = 1110*/ cntr = 5000; /*D = 13 = 1101*/ do waitloop until ce; /*bit 4,5 data type right justified zero filled MSB*/ nop; /*bit 6 INVRFS = 0*/ nop; /*bit 7 INVTFS = 0*/ nop; /*bit 8 IRFS=1 receive internal frame sync*/ nop; /*bit 9,10,11 are for TFS (don’t care)*/ nop; /*bit 12 RFSW=0 receive is Normal mode*/ nop; /*bit 13 RTFS=1 receive is framed mode*/ waitloop: nop; /*bit 14 ISCLK=0 SCLK is external */ rts; /*bit 15 multichannel mode = 0*/ .endmod; ax0 = 0x2F0D; /*normal mode, bit 12=0*/ /*if alternate mode bit 12=1, ax0=0x3F0E*/ dm (0x3FF6) =ax0;

1404fa 21 LTC1404

TYPICAL APPLICATIONU S

Quick Look Circuit for Converting Data to Parallel Format

1 V V 8 5V + CC SS 10µF 0.1µF CONV LTC1404 10 7 12 SRCLR 15 ANALOG INPUT 2 CONV RCK QA D0 A 1 (0V TO 4.096V) IN QB D1 2.43V 6 11 2 3 CLK SRCK QC D2 REFERENCE VREF 3 74HC595 QD D3 OUTPUT + 4 5 14 4 10 F 0.1 F GND D SER QE D4 µ µ OUT 5 QF D5 13 6 G QG D6 7 QH D7 9 3-WIRE SERIAL QH' INTERFACE LINK 10 12 SRCLR 15 RCK QA D8 1 QB D9 11 2 CLK SRCK QC D10 3 QD D11 14 74HC595 4 SER QE REFRDY 5 QF 13 6 G QG 7 QH 9 QH' 1404 TA03

1404fa 22 LTC1404

PACKAGE DESCRIPTIONU

S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610)

.189 – .197 (4.801 – 5.004) .045 ±.005 .050 BSC NOTE 3 8 7 6 5

.245 .160 .005 MIN ± .150 – .157 .228 – .244 (3.810 – 3.988) (5.791 – 6.197) NOTE 3

.030 ±.005 TYP 1 2 3 4 RECOMMENDED SOLDER PAD LAYOUT

.010 – .020 × 45° .053 – .069 (0.254 – 0.508) (1.346 – 1.752) .004 – .010 .008 – .010 (0.101 – 0.254) (0.203 – 0.254) 0°– 8° TYP

.016 – .050 .014 – .019 .050 (0.406 – 1.270) (0.355 – 0.483) (1.270) NOTE: INCHES TYP BSC 1. DIMENSIONS IN (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303

1404fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1404

TYPICAL APPLICATIONU S

LTC1404 Interface to TMS320C50 Running at 5MHz without External Clock

TMS320C50 5V TCLKX 1 6 VCC CLK TCLKR TFSX UNIPOLAR 2 7 + A CONV TFSR INPUT IN 10µF 0.1µF LTC1404 3 5 VREF DOUT TDR

+ VSS GND 10µF 0.1µF 84 1404 TA07

LTC1404 Interface to ADSP2181 Running at 8.3MHz without External Clock

5V ADSP2181 1 6 V CLK SCLKO CC (8.3MHz) UNIPOLAR 2 7 + A CONV RFSO INPUT IN 10µF 0.1µF LTC1404 3 5 VREF DOUT DR0

+ VSS GND 10µF 0.1µF 84 1404 TA06

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS LTC1285/LTC1288 12-Bit, 3V, 7.5/6.6ksps, Micropower Serial ADCs 0.48mW, 1-/2-Channel Input, SO-8 LTC1286/LTC1298 12-Bit, 5V, 12.5/11.16ksps, Micropower Serial ADCs 1.25mW, 1-/2-Channel Input, SO-8 LTC1290 12-Bit, 50ksps 8-Channel Serial ADC 5V or ±5V Input Range, 30mW, Full-Duplex LTC1296 12-Bit, 46.5ksps 8-Channel Serial ADC 5V or ±5V Input Range, 30mW, Half-Duplex LTC1403/LTC1403A 12-/14-Bit 2.8Msps Serial ADCs 3V, 15mW, MSOP-10 Package, Unipolar Input LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADCs 3V, 15mW, MSOP-10 Package, Bipolar Input LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 3V, 14mW, 2-Channel Unipolar Differential Inputs, MSOP-10 LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 3V, 14mW, 2-Channel Bipolar Differential Inputs, MSOP-10 LTC1417 14-Bit, 400ksps Serial ADC 5V or ±5V, 20mW, Internal Reference, SSOP-16 LTC1609 16-Bit, 200ksps Serial ADC 5V, Configurable Bipolar or Unipolar Inputs to ±10V LTC1860L/LTC1861L 12-Bit, 3V, 150ksps Serial ADCs 1.22mW, 1-/2-Channel Input, MSOP-8 and SO-8 LTC1860/LTC1861 12-Bit, 5V, 250ksps Serial ADCs 4.25mW, 1-/2-Channel Input, MSOP-8 and SO-8 LTC1864L/LTC1865L 16-Bit, 3V, 150ksps Serial ADCs 1.22mW, 1-/2-Channel Input, MSOP-8 and SO-8 LTC1864/LTC1865 16-Bit, 5V, 250ksps Serial ADCs 4.25mW, 1-/2-Channel Input, MSOP-8 and SO-8

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