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Asp-Dac 2009 2D-3: Parallelizing Fundamental Algorithms such as Highlights Sorting on Multi-core Processors for EDA Acceleration Masato Edahiro (NEC Corp./Univ. of Tokyo., Japan) ASP-DAC 2009 Opening and Keynote I 3D: Tuesday, January 20, 15:55-18:00, Room 416+417 Tuesday, January 20, 8:30-10:00, Small Auditorium, 5F Invited Talks: “Hardware Dependent Software for Multi- Contents and Many-Core Embedded Systems” “Challenges to EDA System from the View Point of Processor Design and Technology Drivers” 3D-1: Introduction to Hardware-dependent Software De- sign .................... Mitsuo Saito - Chief Fellow and VP of Engineer- Highlights 2 Rainer Domer¨ (Univ. of California, Irvine, United States), ing, Toshiba Corporation Semiconductor Company, Welcome to ASP-DAC 2009 .......... 7 Andreas Gerstlauer (Univ. of Texas, Austin, United Japan States), Wolfgang M¨uller (Univ. of Paderborn, Germany) Message from Technical Program Committee 9 3D-2: Using a Dataflow abstracted Virtual Prototype for Sponsorship .................. 11 Keynote II HdS Design Wednesday, January 21, 9:00-10:00, Small Auditorium, 5F Wolfgang Ecker, Stefan Heinen (Infineon Technologies Organizing Committee ............. 12 AG, Germany) Technical Program Committee ........ 15 “Automated Synthesis and Verification of Em- 3D-3: Needs and Trends in Embedded Software Develop- bedded Systems: Wishful Thinking or Reality?” ment for Consumer Electronics . University LSI Design Contest Committee 20 Wolfgang Rosenstiel - Professor, Chair for Yasutaka Tsunakawa (Sony Corp., Japan) Industry Liaison ................. 21 Computer Engineering and Director, Wilhelm- 3D-4: Hardware-dependent Software Synthesis for Many-Core Embedded Systems Steering Committee .............. 22 Schickard-Institute for Informatics, University of Tuebingen, Germany Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, University LSI Design Contest ......... 23 Yonghyun Hwang, Lochi Yu, Daniel Gajski (Univ. of Cali- fornia, Irvine, United States) ............... Keynote III Designers’ Forum 24 4D: Wednesday, January 21, 10:15-12:20, Room 416+417 Thursday, January 22, 9:00-10:00, Small Auditorium, 5F Student Forum at ASP-DAC 2009 ...... 25 Invited Talks: “Challenges in 3D Integrated Circuit De- ASP-DAC 2009 Best Papers ......... 26 “From Restrictive to Prescriptive Design” sign” Leon Stok - Director, Electronic Design Automa- 4D-1: Three-Dimensional Integration Technology and In- .... ASP-DAC 2009 Design Contest Award 28 tion, IBM Systems and Technology Group, United tegrated Systems Invitation to ASP-DAC 2010 .......... 29 States Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka (Tohoku Univ., Japan) ............... Keynote Addresses 30 Special Sessions 4D-2: A 3D Prototyping Chip based on a Wafer-level Technical Program ............... 32 Stacking Technology 1D: Tuesday, January 20, 10:15-12:20, Room 416+417 Nobuaki Miyakawa (Honda Research Institute, Japan) Tutorials ..................... 57 Presentation + Poster Discussion: “University LSI De- 4D-3: Design and CAD Challenges for 3D ICs ASP-DAC 2009 at a Glance .......... 63 sign Contest” (See page 23 for more details.) David Kung, Ruchir Puri (IBM Corp., United States) 4D-4: Addressing Thermal and Power Delivery Bottle- ................... 2D: Tuesday, January 20, 13:30-15:35, Room 416+417 Information 67 Invited Talks: “EDA Acceleration Using New Architec- necks in 3D Circuits Access to Pacifico Yokohama ......... 70 tures” Sachin S. Sapatnekar (Univ. of Minnesota, United States) 2D-1: Aspects of GPU for General Purpose High Perfor- Venue Map/Room Assignment ........ 72 4D-5: The Road to 3D EDA Tool Readiness mance Computing Charles Chiang, Subarna Sinha (Synopsys, United Electronic Design and Solution Fair 2009 . 74 Reiji Suda (Univ. of Tokyo/JST CREST, Japan), Takayuki States) System Design Forum 2009 at EDS Fair . 75 Aoki (Tokyo Inst. of Tech./JST, CREST, Japan) Shoichi Hirasawa (Univ. of Electro-Comm./JST CREST, Japan) 9D: Thursday, January 22, 15:55-18:00, Room 416+417 Akira Nukada (Tokyo Inst. of Tech./JST CREST, Japan) Invited Talks + Panel Discussion: “Dependable VLSI: De- Hiroki Honda (Univ. of Electro-Comm./JST CREST, vice, Design and Architecture – How should they coop- Japan) Satoshi Matsuoka (Tokyo Inst. of Tech./JST erate ? –” CREST/NII, Japan) 2D-2: Designing and Optimizing Compute Kernels on Nvidia GPUs Damir A. Jamsek (IBM Research, United States) 1 2 3 Organizer: Shuichi Sakai (Univ. of Tokyo, Japan) Moderator: Takashi Hasegawa (Fujitsu Microelectronics Monday, January 19, 2009, 9:30-12:30 and 14:00-17:00 Panelists: Hidetoshi Onodera (Kyoto Univ., Japan) Ltd., Japan) Hiroto Yasuura (Kyushu Univ., Japan) Panelists: Simon Bloch (Mentor Graphics Corporation, 4, 5 Circuit Reliability: Modeling, Simulation, and Re- James C. Hoe (Carnegie Mellon Univ., United United States) silient Design Solutions States) Ahmed Jerraya (CEA-LETI, France) Section I (morning): Reliability Mechanisms and Gabriela Nicolescu (Ecole Polytechnique de the Impact on IC Design Designers’ Forum Montreal, Canada) Section II (afternoon): Circuit Aging Prediction and 5D: Wednesday, January 21, 13:30-15:35, Room 416+417 Shigeru Oho (Hitachi, Ltd., Japan) Koichiro Yamashita (Fujitsu Labs. Ltd., Japan) Resilient Design Invited Talks: “Consumer SoCs” Thursday, January 22, 13:30-15:35, Room 416+417 Organizer: Yu (Kevin) Cao - Arizona State Univ., 5D-1: Development of Full-HD Multi-standard Video 8D: CODEC IP Based on Heterogeneous Multiprocessor Ar- Panel Discussion: “Near-Future SoC Architectures – United States chitecture Can Dynamically Reconfigurable Processors be a Key Speakers (Section I): Yu (Kevin) Cao - Arizona State Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Taka- Technology?” Univ., United States Kaushik Roy - Purdue Univ., fumi Yuasa, Toru Fujihira (Hitachi, Ltd., Japan), Kenichi Moderator: Hideharu Amano (Keio Univ., Japan) United States Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Panelists: Toru Awashima (NEC Corp., Japan) Speakers (Section II): Marek Patyra - Intel, United Masaki Nobori (Renesas Technology Corp., Japan) Hisanori Fujisawa (Fujitsu Labs. Ltd., Japan) States - Stanford Univ., United 5D-2: A 65nm Dual-Mode Baseband and Multimedia Ap- Naohiko Irie (Hitachi, Ltd., Japan) Subhasish Mitra plication Processor SoC with Advanced Power and Mem- Takashi Miyamori (Toshiba Corp., Japan) States ory Management Tony Stansfield (Panasonic Europe Ltd., Great Monday, January 19, 2009, 14:00-17:00 Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Britain) Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro 6 Recent Advances in Low-Leakage VLSI Design Hattori, Shinichi Yoshioka (Renesas Technology Corp., One Full-Day and Six Half-Day Tutorials Organizer: Youngsoo Shin - KAIST, Korea Japan) FULL-DAY Tutorial: 5D-3: UniPhier: Series Development and SoC Manage- Monday, January 19, 2009, 9:30-17:00 Speaker: Youngsoo Shin - KAIST, Korea Kaushik ment Roy - Purdue Univ., United States Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji 1 Software Development and Programming of Multi- Horii, Hisato Yoshida (Panasonic Corp., Japan) core LSI 7 Memory Architectures and Software Transforma- 7D: Thursday, January 22, 10:15-12:20, Room 416+417 Organizer: Ahmed Amine Jerraya - TIMA, France tions for System Level Design Invited Talks: “Analog/RF Circuit Designs” Speakers: Wayne Wolf - Georgia Institute of Tech- Organizer: Nikil Dutt - Univ. of California, Irvine, 7D-1: Design Methods for Pipeline & Delta-Sigma A-to-D nology, United States Damir Jamsek - IBM, United United States Converters with Convex Optimization States Hiroyuki Tomiyama - Nagoya Univ., Japan Fa- Speaker: Stylianos Mamagkakis - IMEC, Belgium Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, bien Clermidy - CEA-LETI, France Preeti Panda - Indian Institute of Technology, Delhi, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji India Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho (Pana- HALF-DAY Tutorials: sonic Corp., Japan) Monday, January 19, 2009, 9:30-12:30 7D-2: A Low-Jitter 1.5-GHz and Large-EMI reduction 10- dBm Spread-Spectrum Clock Generator for Serial-ATA 2 Formal Methods for C-Based Embedded System Takashi Kawamoto, Masaru Kokubo (Hitachi, Ltd., Design Verification — Technical Trends and Practi- Japan) cal Aspects — 7D-3: RF-Analog Circuit Design in Scaled SoC Organizer: Masahiro Fujita - Univ. of Tokyo, Japan Nobuyuki Itoh, Mototsugu Hamada (Toshiba Corp., Speakers: Masahiro Fujita - Univ. of Tokyo, Japan Japan) Alan J. Hu - Univ. of British Columbia, Canada Andy 7D-4: An Approach to the RF-LSI Design for Ubiquitous Chou - Coverity Inc., United States Communication Appliances Yuichi Kado, Mitsuru Harada (NTT, Japan) 3 Statistical Design on the Verge of Maturity: Revis- 6D: Wednesday, January 21, 15:55-18:00, Room 416+417 iting the Foundation Panel Discussion: “ESL Design Methods” Organizer: Michael Orshansky - Univ. of Texas, Austin, United States Speakers: Sani Nassif - IBM, United States Michael Orshansky - Univ. of Texas, Austin, United States 4 5 6 Welcome to ASP-DAC 2009 An event like ASP-DAC doesn’t just happen. I wish to ex- Message from Technical Program Committee press my appreciation to all authors, speakers, reviewers, On behalf of the Organizing Committee, I would like to session organizers, session chairs, panelists, keynote speak- On behalf of the Technical Program Committee of the invite you to attend the Asia and South Pacific Design Au- ers and tutors. Also, I sincerely thank the members of the Or- Asia and South Pacific Design Automation Conference (ASP- tomation Conference
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