2D-3: Parallelizing Fundamental Algorithms such as Highlights Sorting on Multi-core Processors for EDA Acceleration Masato Edahiro (NEC Corp./Univ. of Tokyo., Japan) ASP-DAC 2009 Opening and Keynote I 3D: Tuesday, January 20, 15:55-18:00, Room 416+417 Tuesday, January 20, 8:30-10:00, Small Auditorium, 5F Invited Talks: “Hardware Dependent Software for Multi- Contents and Many-Core Embedded Systems” “Challenges to EDA System from the View Point of Processor Design and Technology Drivers” 3D-1: Introduction to Hardware-dependent Software De- sign ...... Mitsuo Saito - Chief Fellow and VP of Engineer- Highlights 2 Rainer Domer¨ (Univ. of California, Irvine, United States), ing, Toshiba Corporation Semiconductor Company, Welcome to ASP-DAC 2009 ...... 7 Andreas Gerstlauer (Univ. of Texas, Austin, United Japan States), Wolfgang M¨uller (Univ. of Paderborn, Germany) Message from Technical Program Committee 9 3D-2: Using a Dataflow abstracted Virtual Prototype for Sponsorship ...... 11 Keynote II HdS Design Wednesday, January 21, 9:00-10:00, Small Auditorium, 5F Wolfgang Ecker, Stefan Heinen (Infineon Technologies Organizing Committee ...... 12 AG, Germany) Technical Program Committee ...... 15 “Automated Synthesis and Verification of Em- 3D-3: Needs and Trends in Embedded Software Develop- bedded Systems: Wishful Thinking or Reality?” ment for Consumer Electronics . . University LSI Design Contest Committee 20 Wolfgang Rosenstiel - Professor, Chair for Yasutaka Tsunakawa (Sony Corp., Japan) Industry Liaison ...... 21 Computer Engineering and Director, Wilhelm- 3D-4: Hardware-dependent Software Synthesis for Many-Core Embedded Systems Steering Committee ...... 22 Schickard-Institute for Informatics, University of Tuebingen, Germany Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, University LSI Design Contest ...... 23 Yonghyun Hwang, Lochi Yu, Daniel Gajski (Univ. of Cali- fornia, Irvine, United States) ...... Keynote III Designers’ Forum 24 4D: Wednesday, January 21, 10:15-12:20, Room 416+417 Thursday, January 22, 9:00-10:00, Small Auditorium, 5F Student Forum at ASP-DAC 2009 ...... 25 Invited Talks: “Challenges in 3D Integrated Circuit De- ASP-DAC 2009 Best Papers ...... 26 “From Restrictive to Prescriptive Design” sign” Leon Stok - Director, Electronic Design Automa- 4D-1: Three-Dimensional Integration Technology and In- .... ASP-DAC 2009 Design Contest Award 28 tion, IBM Systems and Technology Group, United tegrated Systems Invitation to ASP-DAC 2010 ...... 29 States Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka (Tohoku Univ., Japan) ...... Keynote Addresses 30 Special Sessions 4D-2: A 3D Prototyping Chip based on a Wafer-level Technical Program ...... 32 Stacking Technology 1D: Tuesday, January 20, 10:15-12:20, Room 416+417 Nobuaki Miyakawa (Honda Research Institute, Japan) Tutorials ...... 57 Presentation + Poster Discussion: “University LSI De- 4D-3: Design and CAD Challenges for 3D ICs ASP-DAC 2009 at a Glance ...... 63 sign Contest” (See page 23 for more details.) David Kung, Ruchir Puri (IBM Corp., United States) 4D-4: Addressing Thermal and Power Delivery Bottle- ...... 2D: Tuesday, January 20, 13:30-15:35, Room 416+417 Information 67 Invited Talks: “EDA Acceleration Using New Architec- necks in 3D Circuits Access to Pacifico Yokohama ...... 70 tures” Sachin S. Sapatnekar (Univ. of Minnesota, United States) 2D-1: Aspects of GPU for General Purpose High Perfor- Venue Map/Room Assignment ...... 72 4D-5: The Road to 3D EDA Tool Readiness mance Computing Charles Chiang, Subarna Sinha (Synopsys, United Electronic Design and Solution Fair 2009 . . 74 Reiji Suda (Univ. of Tokyo/JST CREST, Japan), Takayuki States) System Design Forum 2009 at EDS Fair . . . 75 Aoki (Tokyo Inst. of Tech./JST, CREST, Japan) Shoichi Hirasawa (Univ. of Electro-Comm./JST CREST, Japan) 9D: Thursday, January 22, 15:55-18:00, Room 416+417 Akira Nukada (Tokyo Inst. of Tech./JST CREST, Japan) Invited Talks + Panel Discussion: “Dependable VLSI: De- Hiroki Honda (Univ. of Electro-Comm./JST CREST, vice, Design and Architecture – How should they coop- Japan) Satoshi Matsuoka (Tokyo Inst. of Tech./JST erate ? –” CREST/NII, Japan) 2D-2: Designing and Optimizing Compute Kernels on Nvidia GPUs Damir A. Jamsek (IBM Research, United States) 1 2 3 Organizer: Shuichi Sakai (Univ. of Tokyo, Japan) Moderator: Takashi Hasegawa (Fujitsu Microelectronics Monday, January 19, 2009, 9:30-12:30 and 14:00-17:00 Panelists: Hidetoshi Onodera (Kyoto Univ., Japan) Ltd., Japan) Hiroto Yasuura (Kyushu Univ., Japan) Panelists: Simon Bloch (Mentor Graphics Corporation, 4, 5 Circuit Reliability: Modeling, Simulation, and Re- James C. Hoe (Carnegie Mellon Univ., United United States) silient Design Solutions States) Ahmed Jerraya (CEA-LETI, France) Section I (morning): Reliability Mechanisms and Gabriela Nicolescu (Ecole Polytechnique de the Impact on IC Design Designers’ Forum Montreal, Canada) Section II (afternoon): Circuit Aging Prediction and 5D: Wednesday, January 21, 13:30-15:35, Room 416+417 Shigeru Oho (Hitachi, Ltd., Japan) Koichiro Yamashita (Fujitsu Labs. Ltd., Japan) Resilient Design Invited Talks: “Consumer SoCs” Thursday, January 22, 13:30-15:35, Room 416+417 Organizer: Yu (Kevin) Cao - Arizona State Univ., 5D-1: Development of Full-HD Multi-standard Video 8D: CODEC IP Based on Heterogeneous Multiprocessor Ar- Panel Discussion: “Near-Future SoC Architectures – United States chitecture Can Dynamically Reconfigurable Processors be a Key Speakers (Section I): Yu (Kevin) Cao - Arizona State Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Taka- Technology?” Univ., United States Kaushik Roy - Purdue Univ., fumi Yuasa, Toru Fujihira (Hitachi, Ltd., Japan), Kenichi Moderator: Hideharu Amano (Keio Univ., Japan) United States Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Panelists: Toru Awashima (NEC Corp., Japan) Speakers (Section II): Marek Patyra - Intel, United Masaki Nobori (Renesas Technology Corp., Japan) Hisanori Fujisawa (Fujitsu Labs. Ltd., Japan) States - Stanford Univ., United 5D-2: A 65nm Dual-Mode Baseband and Multimedia Ap- Naohiko Irie (Hitachi, Ltd., Japan) Subhasish Mitra plication Processor SoC with Advanced Power and Mem- Takashi Miyamori (Toshiba Corp., Japan) States ory Management Tony Stansfield (Panasonic Europe Ltd., Great Monday, January 19, 2009, 14:00-17:00 Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Britain) Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro 6 Recent Advances in Low-Leakage VLSI Design Hattori, Shinichi Yoshioka (Renesas Technology Corp., One Full-Day and Six Half-Day Tutorials Organizer: Youngsoo Shin - KAIST, Korea Japan) FULL-DAY Tutorial: 5D-3: UniPhier: Series Development and SoC Manage- Monday, January 19, 2009, 9:30-17:00 Speaker: Youngsoo Shin - KAIST, Korea Kaushik ment Roy - Purdue Univ., United States Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji 1 Software Development and Programming of Multi- Horii, Hisato Yoshida (Panasonic Corp., Japan) core LSI 7 Memory Architectures and Software Transforma- 7D: Thursday, January 22, 10:15-12:20, Room 416+417 Organizer: Ahmed Amine Jerraya - TIMA, France tions for System Level Design Invited Talks: “Analog/RF Circuit Designs” Speakers: Wayne Wolf - Georgia Institute of Tech- Organizer: Nikil Dutt - Univ. of California, Irvine, 7D-1: Design Methods for Pipeline & Delta-Sigma A-to-D nology, United States Damir Jamsek - IBM, United United States Converters with Convex Optimization States Hiroyuki Tomiyama - Nagoya Univ., Japan Fa- Speaker: Stylianos Mamagkakis - IMEC, Belgium Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, bien Clermidy - CEA-LETI, France Preeti Panda - Indian Institute of Technology, Delhi, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji India Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho (Pana- HALF-DAY Tutorials: sonic Corp., Japan) Monday, January 19, 2009, 9:30-12:30 7D-2: A Low-Jitter 1.5-GHz and Large-EMI reduction 10- dBm Spread-Spectrum Clock Generator for Serial-ATA 2 Formal Methods for C-Based Embedded System Takashi Kawamoto, Masaru Kokubo (Hitachi, Ltd., Design Verification — Technical Trends and Practi- Japan) cal Aspects — 7D-3: RF-Analog Circuit Design in Scaled SoC Organizer: Masahiro Fujita - Univ. of Tokyo, Japan Nobuyuki Itoh, Mototsugu Hamada (Toshiba Corp., Speakers: Masahiro Fujita - Univ. of Tokyo, Japan Japan) Alan J. Hu - Univ. of British Columbia, Canada Andy 7D-4: An Approach to the RF-LSI Design for Ubiquitous Chou - Coverity Inc., United States Communication Appliances Yuichi Kado, Mitsuru Harada (NTT, Japan) 3 Statistical Design on the Verge of Maturity: Revis- 6D: Wednesday, January 21, 15:55-18:00, Room 416+417 iting the Foundation Panel Discussion: “ESL Design Methods” Organizer: Michael Orshansky - Univ. of Texas, Austin, United States Speakers: Sani Nassif - IBM, United States Michael Orshansky - Univ. of Texas, Austin, United States 4 5 6 Welcome to ASP-DAC 2009 An event like ASP-DAC doesn’t just happen. I wish to ex- Message from Technical Program Committee press my appreciation to all authors, speakers, reviewers, On behalf of the Organizing Committee, I would like to session organizers, session chairs, panelists, keynote speak- On behalf of the Technical Program Committee of the invite you to attend the Asia and South Pacific Design Au- ers and tutors. Also, I sincerely thank the members of the Or- Asia and South Pacific Design Automation Conference (ASP- tomation Conference 2009 (ASP-DAC 2009), being held here ganizing Committee, the Technical Program Committee, the DAC) 2009, we would like to welcome all of you to the con- at Pacifico Yokohama, Japan, from January 19 through 22, University Design Contest Committee, the Technical Liaison ference held from January 19 through 22, 2009 at Pacifico 2009, jointly with the Electronic Design and Solution Fair and the Steering Committee. Yokohama Conference Center in Yokohama, Japan. 2009. ASP-DAC 2009 offers an ideal place for all these peo- Finally, special thanks to the all ASP-DAC attendees — we This year, ASPDAC received 355 paper submissions, ple to meet and exchange ideas about the challenges and are sure you will have a productive and exciting experience which is about the same as last year. The submissions span solutions for the future. I hope you visit the conference to at ASP-DAC 2009. close to 30 countries/regions in Asia, North America, South learn about all the latest advances in electronic design tech- America, Europe, Oceania, Australia and Africa. The Tech- nology and automation. nical Program Committee was composed of 95 profession- Kazutoshi Wakabayashi The heart of conference is the technical program. als who are experts on EDA, IC design, and system design, General Chair ASP-DAC 2009 received 355 submissions from 33 coun- and was organized into 13 subcommittees. All committee ASP-DAC 2009 tries/regions. Based on the result of a rigorous and thorough members contributed to in-depth, rigorous and thorough re- review followed by a full day face-to-face discussion, 116 pa- views and most of them attended the paper selection meet- pers were selected and compiled into an exciting program. ing. Through a full day face-to-face discussion, 116 quality Each day, the technical program starts with a keynote papers have been selected and compiled into 24 technical address. This year, ASP-DAC is proud to present three sessions in a three-day, three parallel tracks program. The keynote presentations from leading-edge company’s leaders program is further enriched by three keynote addresses, an and academia. On Tuesday, Mr. Mitsuo Saito, Chief Fel- additional track of special sessions and panels, and excel- low and VP of Engineering, Toshiba Corporation Semicon- lent tutorial sessions. We sincerely hope you will enjoy and ductor Company, will present some examples of the relation- benefit from the program. ship between the design methodology revolution and the mi- Each day, technical session starts with a keynote address croprocessor evolution and the special requirements to the which is organized under the leadership of Dr. Kazutoshi EDA industry for the next generation of SoCs and multi core Wakabayashi, General Chair. We have 9 special sessions processors. On Wednesday, Professor Wolfgang Rosenstiel, on Track D (1D - 9D). On Tuesday, we have University LSI University of Tuebingen, will discuss possibilities and limita- Design Contest session (1D), and sessions (2D and 3D) for tions of system level automated synthesis and verification of recent advances on EDA area using novel hightly parallel ar- embedded systems. On Thursday, Dr. Leon Stok, Director, chitectures. On Wednesday, we have a session 3D for three Electronic Design Automation, IBM Systems and Technology dimensional integrated circuit design isuues and two design- Group, will discuss if design rules can still be described in ers’ forum sessions (5D and 6D) for consumer SoCs and a terms of restrictions for the coming technologies or if new ap- panel discussion on ESL design methods. On Thursday, we proaches are needed. have two designers’ forum session on analog/RF circuits and The Designers’ Forum is our unique program that will share on near-future SoC architectures, and an attracting special design experience and solutions of actual product designs of panel on Dependable VLSI device, design and architecture. the industries. This year’s program will include invited talks These special sessions covers novel and exciting topics and of up-to-date consumer SoCs and analog technologies, pan- we hope that you can find some hint to the futher research els of upstream design methods and dynamic reconfigurable and development on LSI. processors. Finally, we would like to thank all people contributed to the The University Design Contest is also an important annual 2009 event. At first, we should thank to all the authors who event of ASP-DAC where 23 designs were selected for pre- submitted excellent quality papers, since their contributions sentation. form the basis of our technical excellence. We also would like On Monday, one full-day and six half-day tutorials are to thank to members of Organizing and Technical Program scheduled to provide introductions to hot topics such as de- Commiiteees, the members of Industry Liaison, organizers of sign for variability, reliable circuit design, low leakage design, special sessions and the conference secretariat (JESA). multi-core software development, embedded system design, and functional verification.
7 8 9 Looking forward to meeting with you at ASP-DAC 2009. Sponsorship Organizing Committee
Ren-Song Tsay Sponsored by: TPC Chair General Chair ASP-DAC 2009 IEEE Circuits and Systems Society Shinji Kimura http://www.ieee-cas.org Kazutoshi Wakabayashi TPC Vice Chair NEC Corporation ASP-DAC 2009 ACM/SIGDA 1753, Shimonumabe, Nakahara-ku, Kawasaki, http://www.sigda.org Kanagawa 211-8666, Japan [email protected] IEICE ESS (Institute of Electronics, Infor- mation and Communication Engineers – Past Chair Engineering Sciences Society) Chong-Min Kyung http://www.ieice.org KAIST [email protected] IPSJ SIGSLDM (Information Processing Society of Japan – SIG System LSI Design Secretaries Methodology) Yoshinori Takeuchi Kiyoharu Hamaguchi http://www.ipsj.or.jp Osaka University Osaka University [email protected] [email protected] Technical Co-Sponsor: Takashi Takenaka IEEE Council on Electronic Design NEC Corporation Automation [email protected] http://www.c-eda.org Supported by: SC Chair University LSI Design JEITA (Japan Electronics and Information Hiroto Yasuura Contest Co-Chairs Technology Industries Association) Kyushu Univ. Kazutoshi Kobayashi http://www.jeita.or.jp SC Vice Chair Kyoto Univ. Hidetoshi Onodera Kenichi Okada STARC (Semiconductor Technology Aca- Kyoto Univ. Tokyo Inst. of Tech. demic Research Center) Technical Program Chair Designers’ Forum http://www.starc.jp Ren-Song Tsay Co-Chairs National Tsing Hua Univ. Kunihiro Asada City of Yokohama Univ. of Tokyo http://www.city.yokohama.jp/en/ Technical Program Vice Chair Kunio Uchiyama Hitachi, Ltd. Industrial/Academic Contributors: Shinji Kimura Waseda Univ. Designers’ Forum Vice NEC System Technologies, Ltd. Technical Program Co-Chairs http://www.necst.co.jp/english/index.htm Secretary Makoto Ikeda Jing-Jia Liou Univ. of Tokyo Cadence Design Systems, Inc. National Tsing Hua Univ. Sumio Morioka http://www.cadence.com NEC Corp.
10 11 12 Technical Program Committee Tutorial Chair ASP-DAC Japan Council Secretariat Nagisa Ishiura Rep. Jiro Irie Kwansei Gakuin Univ. Tokinori Kozawa Japan Electronics Show Asso- Chair Tutorial Vice Chair ciation Masanori Hashimoto Kenji Yoshida Yoshinori Ishizaki Ren-Song Tsay National Tsing Hua University Osaka Univ. D2S KK Japan Electronics Show Asso- Finance Chair ASP-DAC Liaison at ciation [email protected] Yutaka Tamiya JEITA/EDA TC Mieko Mori Fujitsu Labs. Ltd. Kazutoshi Wakabayashi Japan Electronics Show Asso- Vice Chair Publicity Chair NEC Corp. ciation Shinji Kimura Hiroyuki Ochi Masaharu Imai Fumiaki Yoshinaga Waseda University Kyoto Univ. Osaka Univ. Japan Electronics Show Asso- shinji [email protected] ciation Publication Co-Chairs ASP-DAC Rep. at DAC Tohru Ishihara Kazutoshi Wakabayashi Secretary Kyushu Univ. NEC Corp. Jing-Jia Liou Nozomu Togawa ASP-DAC Rep. at DATE National Tsing Hua University Waseda Univ. Tohru Ishihara [email protected] Promotion Chair Kyushu Univ. Naoya Tohyama ASP-DAC Rep. at ICCAD Liquid Design Systems Yao-Wen Chang Web Publicity National Taiwan Univ. Masashi Imai IEICE/CAS Rep. Univ. of Tokyo Hiroshi Tamura Entertainment Chair Niigata Inst. of Tech. Koji Inoue IEICE/ICD Rep. Kyushu Univ. Akira Matsuzawa ASP-DAC Liaison at Tokyo Inst. of Tech. IEICE/VLD Student Forum IEICE/VLD Rep. Yasuhiro Takashima Univ. of Kitakyushu Kazutoshi Wakabayashi NEC Corp. EDSF Chair Kaoru Kawamura IPSJ/SLDM Rep. Fujitsu Microelectronics Ltd. Shinji Kimura JEITA/EDA TC Rep. Waseda Univ. ASP-DAC 2009 SECRETARIAT c/o Japan Electronics Show Association Takashi Yamada Sumitomo Shibadaimon Bldg. 2-gokan, 5F Sanyo Electric Co., Ltd. 1-12-16 Shibadaimon, Minato-ku, Tokyo 105-0012 Japan Tel: +81-3-5402-7601 Fax: +81-3-5402-7605 E-mail: [email protected]
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13 14 15 TPC Subcommittees [4] High-Level/Behavioral/Logic Synthesis and Op- [8] Timing, Power, Thermal Analysis and Optimiza- (∗ indicates the subcommittee chair.) timization tion ∗Deming Chen Taewhan Kim ∗Youngsoo Shin Matthew Guthaus [1] System-Level Design Methodology Univ. of Illinois, Urbana- Seoul National Univ. KAIST Univ. of California, Santa ∗Ing-Jer Huang Nozomu Togawa Champaign Yuan Xie Emrah Acar Cruz National Sun-Yat Sen Univ. Waseda Univ. Ki-Seok Chung Pennsylvania State Univ. IBM Corp. Masanori Hashimoto Xu Cheng Chia-Lin Yang Hanyang Univ. Shigeru Yamashita Shabbir Batterywala Osaka Univ. Peking Univ. National Taiwan Univ. Soheil Ghiasi NAIST Synopsys, Inc. Shih-Hsu Huang Eui-Young Chung Qiang Xu Univ. of California, Davis Farzan Fallah Chung Yuan Christian Univ. Yonsei Univ. Chinese Univ. of Hong Kong Hiroyuki Higuchi Fujitsu Laboratories of Tsuneo Nakata Danella Zhao Fujitsu Microelectronics Ltd. America Fujitsu Labs. Ltd. Univ. of Louisiana, [5] Validation and Verification for Behavioral/Logic [9] Signal/power Integrity, Interconnect/Device/ Lafayette Design Circuit Modeling and Simulation [2] System Architecture and Optimization ∗Shin’ichi Minato Yuichi Nakamura ∗Hideki Asai Zuying Luo ∗Sri Parameswaran Tulika Mitra Hokkaido Univ. NEC Corp. Shizuoka Univ. Beijing Normal Univ. Univ. of New South Wales National Univ. of Singapore Chung-Yang Huang Farn Wang Yungseon Eo Parthasarathy Ramaswamy Samar Abdi Preeti Ranjan Panda National Taiwan Univ. National Taiwan Univ. Hanyang Univ. Intel Corp. Univ. of California, Irvine Indian Inst. of Tech., Delhi Igor Markov Yoshinori Watanabe Yu-Min (Roger) Lee Takashi Sato Karam Chatha Li Shang Univ. of Michigan Cadence Design Systems, National Chiao Tung Univ. Tokyo Inst. of Tech. Arizona State Univ. Univ. of Colorado, Boulder Inc. En-Xiao Liu Sheldon Tan Inst. of High Performance Univ. of California, Robert Dick [6] Physical Design (Routing) Northwestern Univ. Computing Riverside ∗Hyunchul Shin Ting-Chi Wang [10] Design for Manufacturability/Yield and Statisti- [3] Embedded and Real-Time Systems Hanyang Univ. National Tsing Hua Univ. cal Design ∗Samarji Chakraborty Gang Quan Jeong-Tyng Li Martin D.F. Wong ∗ National Univ. of Singapore Univ. of South Carolina SpringSoft Univ. of Illinois, Urbana David Pan Puneet Gupta Naehyuck Chang Chi-Sheng Shih Atsushi Takahashi -Champaign Univ. of Texas, Austin Univ. of California, Los Ange- Seoul National Univ. National Taiwan Univ. Tokyo Inst. of Tech. Keh-Jeng Chang les National Tsing Hua Univ. Toshiyuki Shibuya Pai Chou Hiroyuki Tomiyama [7] Physical Design (Placement) Univ. of California, Irvine Nagoya Univ. Charles Chiang Fujitsu Labs. Ltd. Zonghua Gu Sungjoo Yoo ∗Wai-Kei Mak Gi-Joon Nam Synopsys, Inc. Hua Xiang HKUST Samsung Corp. National Tsing Hua Univ. IBM Corp. IBM T.J. Watson Ameya Agnihotri Sherief Reda Paul Pop [11] Test and Design for Testability Technical Univ. of Denmark Magma Design Automation, Brown Univ. Co., Ltd. Evangeline F.Y. Young ∗Seiji Kajihara Satoshi Ohtake Hung Ming Chen Chinese Univ. of Hong Kong Kyushu Inst. of Tech. NAIST National Chiao Tung Univ. Wu-Tung Cheng Ming-Der Shieh Shigetoshi Nakatake Menter Graphics Cheng-Kung Univ. Univ. of Kitakyushu Shi-Yu Huang National Tsing Hua Univ.
16 17 18 [12] Analog, RF and Mixed Signal Design and CAD University LSI Design Contest Committee Industry Liaison ∗Jaijeet Roychowdhury Tomohisa Kimura Univ. of California, Berkeley Toshiba Corp. Chin-Fong Chiu Alper Demir Co-Chairs Chair National Chip Implementa- Koc Univ. Kazutoshi Kobayashi tion Center Eric Keiter Kyoto University Kunihiro Asada Seongwhan Cho Sandia National Labs. [email protected] University of Tokyo KAIST [email protected] Kenichi Okada [13] Emerging Technologies and Applications Tokyo Institute of Technology Kunio Uchiyama [email protected] Hitachi, Ltd. ∗Chin-Long Wey Shorin Kyo National Central Univ. NEC Corp. Jiun-In Guo Chih-Wei Liu Chris Dwyer In-Cheol Park National Chung-Cheng Univ. National Chiao Tung Univ. Design Sunao Torii Duke Univ. KAIST Masanori Hariyama In-Cheol Park Masaru Kakimoto NEC Corp. Chun-Ming Huang Mehdi Baradaran Tahoori Tohoku Univ. KAIST Sony Corp. National Chip Implementa- Northeastern Univ. Hiroshi Kawaguchi Chi-Ying Tsui Hideki Yoshizawa tion Center Kobe Univ. HKUST Yoshio Masubuchi Fujitsu Labs. Ltd. Jri Lee Toshiba Corp. JEITA National Taiwan Univ. Sumio Morioka Tsutomu Eda NEC Corp. Rohm Co., Ltd. Masaitsu Nakajima Takeshi Nishimoto Panasonic Corp. Sharp Corp. Academia Osamu Nishii Makoto Ikeda Renesas Tech. Corp. Univ. of Tokyo
19 20 21 Steering Committee University LSI Design Contest Designers’ Forum Designers’ Forum is conceived as a unique program that shares The University LSI Design Contest was conceived as a unique the design experience and solutions of real product developments Chair program of ASP-DAC Conference. The purpose of the Contest is to among LSI designers and EDA academia/developers. It consists of encourage education and research in LSI design, and its realization these four special sessions: Hiroto Yasuura on chips at universities, and other educational organizations by pro- Kyushu University viding opportunities to present and discuss innovative and stateof- Oral Sessions: 5D Consumer SoCs [email protected] the-art designs at the conference. Application areas and types of 7D Analog/RF Circuit Designs circuits include (1) Analog, RF and Mixed-Signal Circuits, (2) Digital Panel Discussions: 6D ESL Design Methods Vice Chair Signal processing, (3) Microprocessors, and (4) Custom Application 8D Near-Future SoC Architectures Specific Circuits and Memories. Methods or technology used for im- Hidetoshi Onodera plementation include (a) Full Custom and Cell-Based LSIs, (b) Gate Designs will be presented focusing mainly on the design styles, problems and ways to tackle these. Panel discussions will also be Kyoto University Arrays, and (c) Field Programmable Devices, including FPGA/PLDs. [email protected] held concerning the latest design problems. The following gives de- This year, 23 selected designs from five countries/areas will be dis- tailed information of each session: closed in Session 1D with a short presentations followed by live dis- Session 5D (13:30-15:35, Jan 21st) [Consumer SoCs] — This Secretaries cussions in front of posters with light meals. Submitted designs were session deals with real SoC design for consumer electronics devices. Toshihiro Hattori Atsushi Takahashi reviewed by the members of the University Design Contest Commit- Three presentations will be given from Hitachi, Renesas and Pana- sonic. Hitachi will introduce a video codec design on heterogeneous Renesas Technology Corp. Tokyo Institute of Technology tee. As a result, the 23 designs were selected. Also, we have insti- multi-processor architecture. Renesas will show a dual-mode base- [email protected] [email protected] tuted one outstanding design award and one special feature award. band processor on a 65nm process and Panasonic will present their It is with great pleasure that we acknowledge the contributions to SoC development strategy using the common SoC platform Uniphier. PAST SC Chair Chong-Min Kyung the Design Contest, and it is our earnest belief that it will promote and Session 7D (10:15-12:20, Jan 22nd) [Analog/RF Circuit Designs] Tatsuo Ohtsuki KAIST enhance research and education in LSI design in academic organi- — Four presentations on practical design of analog circuits will be Waseda Univ. Youn-Long Lin zations. It is also our hope that many people not only in academia given by Hitachi, Toshiba, Panasonic and NTT. Hitachi will introduce ASP-DAC 2009 General Chair Tsing Hua Univ. a spread spectrum clock generator for the serial ATA interface. To- but in industry will attend the contest and enjoy the stimulating dis- Kazutoshi Wakabayashi Sri Parameswaran shiba will show an RF circuit design in scaled SoC. Panasonic will in- NEC Corp. The Univ. of New South Wales cussions. troduce a strategic optimization method for pipeline and delta-sigma ASP-DAC 2008 General Chair Sunil D. Sherlekar ADC. NTT will show a body area network. Date, Time and Locations: Chong-Min Kyung Tata Consultancy Services Session 6D (15:55-18:00, Jan 21st) [ESL Design Methods] — KAIST Qianling Zhang Oral Presentation 10:15-12:20, January 20, 2009, Room Panelists from LSI design companies, tool venders and academic ACM SIGDA Representative Fudan Univ., Beijing 416+417 institute will discuss about the latest ESL (Electronic System Level) Patrick Madden Advisory Members Poster Presentation 12:20-13:30, January 20, 2009, Room design methodologies/tools and their use in practical SoC designs. Binghamton Univ. Panelists will introduce tool flow and LSI design experiences using 418 (Food will be served.) IEEE CAS Representative Satoshi Goto UML, MATLAB, SystemC and other high abstraction level modeling Waseda Univ. languages and tools. Takao Onoye Fumiyasu Hirose Osaka Univ. University LSI Design Contest Committee Session 8D (13:30-15:35, Jan 22nd) [Near-Future SoC Architec- Cadence Design Systems, Japan Co-Chairs DAC Representative Masaharu Imai tures — Can Dynamically Reconfigurable Processors be a Key Andrew B. Kahng Osaka Univ. Kazutoshi Kobayashi Technology?] — Panelists from Hitachi, Toshiba, Panasonic Eu- Univ. of California at San Diego Takashi Kambe Kyoto University rope, Fujitsu and NEC will discuss the latest dynamic reconfigurable DATE Representative Kinki Univ. processor technologies, their practical use in consumer electronics Wolfgang Nebel Tokinori Kozawa Kenichi Okada Carl von Ossietzky Univ. Oldenburg Tokyo Institute of Tech- devices, and their future expansion. Isao Shirakawa Designers’ Forum Chair ICCAD Representative nology Yao-Wen Chang Univ. of Hyogo Kunihiro Asada National Taiwan Univ. TingAo Tang University of Tokyo Fudan Univ. EDSF Chair Designers’ Forum Chair Kaoru Kawamura Kenji Yoshida Kunio Uchiyama D2S KK Fujitsu Microelectronics Ltd. Hitachi, Ltd. Designers’ Forum Vice Chair International Members Makoto Ikeda Richard M M Chen University of Tokyo City Univ. of Hong Kong Designers’ Forum Vice Chair Xian-Long Hong Sumio Morioka Tsinghua Univ. NEC Corporation 22 23 24 Student Forum at ASP-DAC 2009 ASP-DAC 2009 Best Papers 7B-1 Dependent Latch Identification in the Reachable State Space A poster session for graduate students to present their re- Best Paper Candidates Chen-Hsuan Lin, Chun-Yao Wang (National Tsing search work is held during ASP-DAC 2009. This is a great Hua Univ., Taiwan) 1A-1 Adaptive Inter-router Links for Low-Power, Area- opportunity for students to get feedback and have discussion 8A-1 Improving Scalability of Model-Checking for Min- Efficient and Reliable Network-on-Chip (NoC) Ar- with people from academia and industry. imizing Buffer Requirements of Synchronous chitectures Dataflow Graphs Date and Time: 12:20-13:30, January 21, 2009 Avinash Karanth Kodi (Ohio Univ., United States), Nan Guan (Northeastern Univ., China), Zonghua Gu Ashwini Sarathy, Ahmed Louri, Janet Wang (Univ. of Location: Room 418 (Food will be served.) (HKUST, China), Wang Yi (Uppsala Univ., Sweden), Arizona, United States) Ge Yu (Northeastern Univ., China) We would like to thank the following poster selection com- 1C-1 FastYield: Variation-Aware, Layout-Driven Simul- 8B-1 A Novel Toffoli Network Synthesis Algorithm for mittee members that evaluated the submissions, taneous Binding and Module Selection for Perfor- Reversible Logic • Koji Hashimoto (Fukuoka University, Japan) mance Yield Optimization Yexin Zheng, Chao Huang (Virginia Tech, United Gregory Lucas, Scott Cromar, Deming Chen (Univ. of • Tohru Ishihara (Kyushu University, Japan) States) Illinois, Urbana-Champaign, United States) • Kazuhito Ito (Saitama University, Japan) 8C-4 Design for Burn-In Test: A Technique for Burn-In 3A-1 System-Level Cost Analysis and Design Explo- Thermal Stability under Die-to-Die Parameter Vari- • Yih-Lang Li (National Chiao Tung University, Taiwan) ration for Three-Dimensional Integrated Circuits ations • Chien-Nan Jimmy Liu (National Central University, Taiwan) (3D ICs) Mesut Meterelliyoz, Kaushik Roy (Purdue Univ., • Yung-Hsiang Lu (Perdue University, United States) Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., United States) United States) • Nozomu Togawa (Waseda University, Japan) 4B-3 Analog Placement with Common Centroid and 1- Best Paper Award • Chun-Yao Wang (National Tsing Hua University, Taiwan) D Symmetry Constraints 1C-1 FastYield: Variation-Aware, Layout-Driven Simul- • David Wu (Chinese University of Hong Kong, Hong Kong) Linfu Xiao, Evangeline Young (Chinese Univ. of Hong taneous Binding and Module Selection for Perfor- • Chia-Lin Yang (National Taiwan University, Taiwan) Kong, Hong Kong) mance Yield Optimization 4C-1 Stochastic Current Prediction Enabled Frequency The sponser of this forum is Technical Group on VLSI De- Gregory Lucas, Scott Cromar, Deming Chen (Univ. of Actuator for Runtime Resonance Noise Reduc- sign Technologies (TGVLD) of the Institute of Electronics, In- Illinois, Urbana-Champaign, United States) tion formation and Communication Engineers (IEICE). We would Yiyu Shi (Univ. of California, Los Angeles, United 5C-1 Efficiently Finding the ’Best’ Solution with Multi- also like to thank ASP-DAC 2009 for sponsoring the event. States), Jinjun Xiong, Howard Chen (IBM, United Objectives from Multiple Topologies in Topology Special thanks to Dr. Farzan Fallah and Professor Atsushi States), Lei He (Univ. of California, Los Angeles, Library of Analog Circuit Takahashi for supporting and contributing to the Student Fo- United States) Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki rum. Shibuya (Fujitsu Laboratories Ltd., Japan) 5B-1 Efficient Analytical Determination of the SEU- induced Pulse Shape Co-Chairs Yasuhiro Takashima Rajesh Garg, Sunil P Khatri (Texas A&M Univ., United University of Kitakyushu States) Ting-Chi Wang 5C-1 Efficiently Finding the ’Best’ Solution with Multi- National Tsing Hua Objectives from Multiple Topologies in Topology University Library of Analog Circuit Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Laboratories Ltd., Japan) 6B-1 Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3- D Global Routing Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
25 26 27 ASP-DAC 2009 Design Contest Award Invitation to ASP-DAC 2010 Keynote Addresses
Best Design Award On behalf of the Organizing Committee, I would like to in- Opening & Keynote I vite you to the 2010 Asia and South-Pacific Design Automa- Tuesday, January 20, 8:30-10:00, 1D-1 A Wireless Real-Time On-Chip Bus Trace System tion Conference (ASP-DAC 2010) to be held on January 18- Small Auditorium, 5F Shusuke Kawai, Takayuki Ikari (Keio Univ., Japan), 21, 2010 in Taipei, Taiwan. This is the first time that ASP-DAC “Challenges to EDA System from the Yutaka Takikawa (Renesas Design Corp, Japan), Hi- comes to Taiwan. Taiwan is the place where many electronics View Point of Processor Design and roki Ishikuro, Tadahiro Kuroda (Keio Univ., Japan) systems and semiconductor devices are designed and man- Technology Drivers” Special Feature Award ufactured. We have a very large community of academic re- Mitsuo Saito searchers and industrial practitioners who are eager to inter- Chief Fellow and VP of Engineering 1D-13 Ultra Low-Power ANSI S1.11 Filter Bank for Digital Toshiba Corporation Semiconductor Hearing Aids act with the world EDA community. In other words, Taiwan is a very good market for EDA ideas. Company, Japan Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li (National Chiao Historically, many microprocessors have been developed, since it was in- Tung Univ., Taiwan), Chou-Kun Lin (ITRI, STC, Tai- Taipei is the capital city of Taiwan. It is easily accessible vented in early 1970’s. Microprocessor design was always under the hardest wan), Chih-Wei Liu (National Chiao Tung Univ., Tai- by direct flight from major cities around the world. You will competition, so they had been the technology driver for the semiconductor find many interesting places to visit. In addition to regular technology and the design methodology until recently. wan) By discussing the relationship between the design methodology (EDA) rev- conference activity, the Organizing Committee will organize olution and the technology driver products transition, based upon famous Maki- several social activities to enrich your trip. moto’s wave hypothesis, what happened to the microprocessor world is high- lighted by showing typical examples. Since 2006, in order to maintain quality and consistency As a recent example, the positioning of the Cell Broadband Engine as a high of its technical program, ASP-DAC has established a rota- performance computing processor and as a flexible HW, is discussed mainly, tion rule that includes the separation of the Technical Pro- also the performance result, and the future trend of the microprocessors to- wards multi-core are discussed. Then it is explained, why SpursEngine derived gram Committee from the Organizing Committee. The 2010 from Cell Broadband Engine had to be developed. Technical Program Committee will be under the leadership of SoC (combination of microprocessor and HW functional unit) for custom applications should be the technology driver, for the next decade, which is the Professor Shinji Kimura of Waseda University, Japan. I solicit first experience after microprocessor was born. The special requirements to your support to the conference by submitting your research the EDA system to realize next wave, are predicted. work to the ASP-DAC 2010. Finally, when the next wave comes, maybe after 2017, software centric era, what happens to the world, is briefly mentioned. I hope you will have a successful ASP-DAC 2009 in Yoko- hama and look forward to seeing you all in Taipei in 2010. Keynote II Wednesday, January 21, 9:00-10:00, Small Auditorium, 5F Youn-Long Lin “Automated Synthesis and Verification General Chair of Embedded Systems: ASP-DAC 2010 Wishful Thinking or Reality?” Wolfgang Rosenstiel Professor, Chair for Computer Engineering and Director About ASP-DAC Wilhelm-Schickard-Institute for Informatics, The ASP-DAC, is a premier Design Automation and Design University of Tuebingen, Germany conference, especially for Asian and South Pacific Electronic More complex embedded hardware/software systems have to be developed Design Automation and Design community, providing a forum with shorter design time and reduced cost. One solution for this problem is increasing design automation starting from higher levels of abstraction. Auto- to present and exchange ideas in order to promote the re- matic synthesis and verification has been around in research for a quite a while. search, and accelerating cooperation between the IC Design This talk will show examples for state-of-the art tools for system-level synthesis and verification of embedded systems and demonstrate their possibilities and and Design methodologies. The conference attendees are limitations by some automotive applications. primarily developers of the EDA/CAD Tools and designers of VLSI circuits & systems (IP & SoC).
28 29 30 Keynote III Technical Program Tuesday, January 20, 10:15 - 12:20 Room 413 Thursday, January 22, 9:00-10:00, Session 1B: Dealing with Thermal Issues Small Auditorium, 5F Chairs: Youngsoo Shin – KAIST, Republic of Ko- “From Restrictive to Prescriptive Tuesday, January 20, 8:30 - 10:00 rea Design” Tuesday, January 20, 8:30 - 10:00 Small Auditorium, 5F Li Shang – Univ. of Colorado, Boulder, Leon Stok Session 1K: Opening and Keynote Session I United States Director, Electronic Design Automation Chair: Kazutoshi Wakabayashi – NEC Corp., 1B-1 Stochastic Thermal Simulation Considering Spa- IBM Systems and Technology Group, Japan tial Correlated Within-Die Process Variations United States Challenges to EDA System from the View Point of Pro- For many generations the hand-off between design and manufacturing has Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee (National been done by a set of design rules. However, design rule manuals have grown cessor Design and Technology Drivers Chiao Tung Univ., Taiwan) in size from several tens of pages a few generations back to hundreds of pages Mitsuo Saito (Toshiba Corp. Semiconductor Company, 1B-2 A Control Theory Approach for Thermal Balanc- now. Many more design rules have been added since the end of traditional Japan) scaling. Even with all these additional rules, corner cases are found late in the ing of MPSoC process that can become significant yield or functionality detractors. Restricted Design Rules (RDRs) have been created to simplify the design rules and come Tuesday, January 20, 10:15 - 12:20 Francesco Zanini, David Atienza, Giovanni De Micheli up with more manufacturable designs. IBM has practiced RDRs in the last few Tuesday, January 20, 10:15 - 12:20 Room 411+412 (EPFL, Switzerland) process generations but is this enough? For the next technology nodes no 1B-3 Thermal Optimization in Multi-Granularity Multi- new exposure tools will be available for mass production and optical scaling is Session 1A: On-Chip Communication Architectures coming to a halt. Computational scaling will be required to extend Moore’s law. Chair: Sri Parameswaran – Univ. of New South Core Floorplanning In this new era, can we keep on describing design rules in terms of restrictions Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, or do we need another approach? Wales, Australia Sung Kyu Lim (Georgia Inst. of Tech., United States) 1A-1 Adaptive Inter-router Links for Low-Power, Area- Efficient and Reliable Network-on-Chip (NoC) Ar- 1B-4 Temperature-Aware Dynamic Frequency and Volt- chitectures age Scaling for Reliability and Yield Enhancement Avinash Karanth Kodi (Ohio Univ., United States), Yu-Wei Yang, Katherine Shu-Min Li (National Sun Yat- Ashwini Sarathy, Ahmed Louri, Janet Wang (Univ. of Sen Univ., Taiwan) Arizona, United States) 1B-5 A Multiple Supply Voltage Based Power Reduc- 1A-2 Analysis of Communication Delay Bounds for tion Method in 3-D ICs Considering Process Vari- Network on Chips ations and Thermal Effects Yue Qian (National Univ. of Defense Tech., China), Shih-An Yu, Pei-Yu Huang, Yu-Min Lee (National Zhonghai Lu (Royal Inst. of Tech., Sweden), Wenhua Chiao Tung Univ., Taiwan) Dou (National Univ. of Defense Tech., China) Tuesday, January 20, 10:15 - 12:20 Room 414+415 1A-3 Frequent Value Compression in Packet-based Session 1C: Advances in Behavioral Synthesis NoC Architectures Chairs: Shigeru Yamashita – NAIST, Japan Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Kiyoung Choi – Seoul National Univ., Re- Jun Yang (Univ. of Pittsburgh, United States), Li Zhao public of Korea (Intel, United States) 1C-1 FastYield: Variation-Aware, Layout-Driven Simul- 1A-4 Simultaneous Data Transfer Routing and taneous Binding and Module Selection for Perfor- Scheduling for Interconnect Minimization in mance Yield Optimization Multicycle Communication Architecture Gregory Lucas, Scott Cromar, Deming Chen (Univ. of Yu-Ju Hong (Purdue Univ., United States), Ya-Shih Illinois, Urbana-Champaign, United States) Huang, Juinn-Dar Huang (National Chiao Tung Univ., 1C-2 CriAS: A Performance-Driven Criticality-Aware Taiwan) Synthesis Flow for On-Chip Multicycle Communi- 1A-5 Dynamically Reconfigurable On-Chip Communi- cation Architecture cation Architectures for Multi Use-Case Chip Mul- Chia-I Chen, Juinn-Dar Huang (National Chiao Tung tiprocessor Applications Univ., Taiwan) Sudeep Pasricha, Nikil Dutt, Fadi Kurdahi (Univ. of California, Irvine, United States)
31 32 33 1C-3 Tolerating Process Variations in High-Level Syn- 1D-6 An Inductor-less MPPT Design for Light Energy 1D-16 A 52-mW 8.29mm2 19-mode LDPC Decoder Chip thesis Using Transparent Latches Harvesting Systems for Mobile WiMAX Applications Yibo Chen, Yuan Xie (Pennsylvania State Univ., Hui Shao, Chi-Ying Tsui, Wing-Hung Ki (HKUST, Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, United States) Hong Kong) An-Yeu (Andy) Wu (National Taiwan Univ., Taiwan) 1C-4 Variation-Aware Resource Sharing and Binding in 1D-7 A 1 GHz CMOS Comparator with Dynamic Offset 1D-17 A Full-Synthesizable High-Precision Built-In De- Behavioral Synthesis Control Technique lay Time Measurement Circuit Feng Wang (Qualcomm Inc., United States), Yuan Xiaolei Zhu (Keio Univ., Japan), Sanroku Tsukamoto Ming-Chien Tsai, Ching-Hwa Cheng (Feng Chia Xie (Pennsylvania State Univ., United States), Andres (Fujitsu Laboratories Ltd., Japan), Tadahiro Kuroda Univ., Taiwan) Takach (Mentor Graphics Corp., United States) (Keio Univ., Japan) 1D-18 A Dynamic Quality-Scalable H.264 Video Encoder 1C-5 Peak Temperature Control in Thermal-aware Be- 1D-8 Circuit Design Using Stripe-Shaped PMELA TFTs Chip havioral Synthesis through Allocating the Num- on Glass Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen ber of Resources Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro (National Chung Cheng Univ., Taiwan), Ching-Lung Junbo Yu, Qiang Zhou, Jinian Bian (Tsinghua Univ., Asada (Univ. of Tokyo, Japan) Su (National Yunlin Univ. of Science and Tech., Tai- China) 1D-9 Low Energy Level Converter Design for Sub-Vth wan), Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Tuesday, January 20, 10:15 - 12:20 Room 416+417 Logics Wang (National Chung Cheng Univ., Taiwan) Session 1D: University LSI Design Contest Hui Shao, Chi-Ying Tsui (HKUST, Hong Kong) 1D-19 A High Performance LDPC Decoder for Chairs: Jiun-In Guo – National Chung Cheng 1D-10 A Time-to-Digital Converter with Small Circuitry IEEE802.11n Standard Univ., Taiwan Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto Hiroki Ishikuro – Keio Univ., Japan Kobayashi, Nobukazu Takai (Gunma Univ., Japan), (Waseda Univ., Japan) 1D-1 A Wireless Real-Time On-Chip Bus Trace System Masao Hotta (Musashi Inst. of Tech., Japan) 1D-20 Design and Chip Implementation of the Ubiqui- Shusuke Kawai, Takayuki Ikari (Keio Univ., Japan), 1D-11 A VDD Independent Temperature Sensor Circuit tous Processor HCgorilla Yutaka Takikawa (Renesas Design Corp, Japan), Hi- with Scaled CMOS Process Masa-aki Fukase, Kazunori Noda, Atsuko Yokoyama, roki Ishikuro, Tadahiro Kuroda (Keio Univ., Japan) Hiroki Oshiyama, Toshihiro Matsuda, Kei-ichi Suzuki, Tomoaki Sato (Hirosaki Univ., Japan) 1D-2 CKVdd: A Self-Stabilization Ramp-Vdd Technique Hideyuki Iwata (Toyama Prefectural Univ., Japan), 1D-21 An 8.69 Mvertices/s 278 Mpixels/s Tile-based for Dynamic Power Reduction Takashi Ohzone (Dawn Enterprise Co. Ltd., Japan) 3D Graphics SoC HW/SW Development for Con- Chin-Hsien Wang, Ching-Hwa Cheng (Feng Chia 1D-12 A Current-mode DC-DC Converter using a sumer Electronics Univ., Taiwan), Jiun-In Guo (National Chung Cheng Quadratic Slope Compensation Scheme Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Univ., Taiwan) Chihiro Kawabata, Yasuhiro Sugimoto (Chuo Univ., Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, ◦ Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, 1D-3 A300nW,7ppm/ C CMOS Voltage Reference Cir- Japan) Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan) cuit based on Subthreshold MOSFETs 1D-13 Ultra Low-Power ANSI S1.11 Filter Bank for Digital Ken Ueno (Hokkaido Univ., Japan), Tetsuya Hi- Hearing Aids 1D-22 A Multi-Task-Oriented Security Processing Archi- rose (Kobe Univ., Japan), Tetsuya Asai, Yoshihito Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li (National Chiao tecture with Powerful Extensibility Amemiya (Hokkaido Univ., Japan) Tung Univ., Taiwan), Chou-Kun Lin (ITRI, STC, Tai- Dan Cao, Jun Han, Xiao-yang Zeng, Shi-ting Lu (Fu- dan Univ., China) 1D-4 A 100Mbps, 0.19mW Asynchronous Threshold wan), Chih-Wei Liu (National Chiao Tung Univ., Tai- Detector with DC Power-Free Pulse Discrimina- wan) 1D-23 A Delay-Optimized Universal FPGA Routing Ar- tion for Impulse UWB Receiver 1D-14 An 11,424 Gate-Count Dynamic Optically Recon- chitecture Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke figurable Gate Array with a Photodiode Memory Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Architecture Wang, Jiarong Tong (Fudan Univ., China) Takayasu Sakurai (Univ. of Tokyo, Japan) Daisaku Seto, Minoru Watanabe (Shizuoka Univ., 1D-5 Low-Power CMOS Transceiver Circuits for 60GHz Japan) Band Millimeter-wave Impulse Radio 1D-15 A Low-Power FPGA Based on Autonomous Fine- Ahmet Oncu, Minoru Fujishima (Univ. of Tokyo, Grain Power-Gating Japan) Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ., Japan)
34 35 36 Tuesday, January 20, 13:30 - 15:35 2B-5 Incremental and On-demand Random Walk for It- Tuesday, January 20, 13:30 - 15:35 Room 416+417 erative Power Distribution Network Analysis Session 2D: Special Session: EDA Acceleration Us- Tuesday, January 20, 13:30 - 15:35 Room 411+412 Yiyu Shi, Wei Yao (Univ. of California, Los Angeles, ing New Architectures Session 2A: MPSoC and IP Integration United States), Jinjun Xiong (IBM, United States), Lei Organizer: Damir A. Jamsek – IBM Corp., United Chairs: Nozomu Togawa – Waseda Univ., Japan He (Univ. of California, Los Angeles, United States) States Marcello Lajolo – NEC Laboratories Tuesday, January 20, 13:30 - 15:35 Room 414+415 2D-1 Aspects of GPU for General Purpose High Perfor- America, United States Session 2C: Logic and Arithmetic Optimization mance Computing 2A-1 Timing Variation-Aware Task Scheduling and Chairs: Dale Edwards – Semiconductor Research Reiji Suda (Univ. of Tokyo/JST CREST, Japan), Binding for MPSoC Corp., United States Takayuki Aoki (Tokyo Inst. of Tech./JST CREST, HaNeul Chon, Taewhan Kim (Seoul National Univ., Hiroyuki Higuchi – Fujitsu Microelectron- Japan), Shoichi Hirasawa (Univ. of Electro- Republic of Korea) ics Ltd., Japan Communications/JST CREST, Japan), Akira Nukada 2A-2 Flexible and Abstract Communication and Inter- 2C-1 SAT-Controlled Redundancy Addition and Re- (Tokyo Inst. of Tech./JST CREST, Japan), Hi- connect Modeling for MPSoC moval — A Novel Circuit Restructuring Technique roki Honda (Univ. of Electro-Communications/JST Katalin Popovici (TIMA Lab., France), Ahmed Jerraya Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung- CREST, Japan), Satoshi Matsuoka (Tokyo Inst. of (CEA-LETI, Minatec, France) Yang (Ric) Huang (National Taiwan Univ., Taiwan) Tech./JST CREST/NII, Japan) 2A-3 Partial Order Method for Timed Simulation of 2C-2 On Improved Scheme for Digital Circuit Rewiring 2D-2 Designing and Optimizing Compute Kernels on System-Level MPSoC Designs and Application on Further Improving FPGA Nvidia GPUs Eric Cheung, Harry Hsieh (Univ. of California, River- Technology Mapping Damir A. Jamsek (IBM Research, United States) side, United States), Felice Balarin (Cadence Design Fu Shing Chim, Tak Kei Lam, Yu Liang Wu (Chinese 2D-3 Parallelizing Fundamental Algorithms such as Systems, United States) Univ. of Hong Kong, Hong Kong) Sorting on Multi-core Processors for EDA Accel- 2A-4 A UML-Based Approach for Heterogeneous IP In- 2C-3 Hybrid LZA: A Near Optimal Implementation of eration tegration the Leading Zero Anticipator Masato Edahiro (NEC Corp./Univ. of Tokyo, Japan) Zhenxin Sun, Weng-Fai Wong (National Univ. of Sin- Amit Verma (National Inst. of Tech., Rourkela, In- gapore, Singapore) Tuesday, January 20, 15:55 - 18:00 dia), Ajay K. Verma, Philip Brisk, Paolo Ienne (EPFL, Tuesday, January 20, 13:30 - 15:35 Room 413 Switzerland) Tuesday, January 20, 15:55 - 18:00 Room 411+412 Session 2B: Power Analysis and Optimization Session 3A: System-Level Design of 3D Chips and 2C-4 An Optimized Design for Serial-Parallel Finite m Configurable Systems Chair: Masanori Hashimoto – Osaka Univ., Field Multiplication over GF(2 ) Based on All-One Japan Polynomials Chairs: Eui-Young Chung – Yonsei Univ., Repub- 2B-1 Statistical Modeling and Analysis of Chip-Level Pramod Kumar Meher (Nanyang Technological Univ., lic of Korea Leakage Power by Spectral Stochastic Method Singapore), Yajun Ha (National Univ. of Singapore, Steve Haga – National Sun Yat-Sen Univ. Ruijing Shen, Ning Mi, Sheldon Tan (Univ. of Cali- Singapore), Chiou-Yng Lee (Lunghwa Univ. of Sci- 3A-1 System-Level Cost Analysis and Design Explo- fornia, Riverside, United States), Yici Cai, Xianlong ence and Tech., Taiwan) ration for Three-Dimensional Integrated Circuits Hong (Tsinghua Univ., China) (3D ICs) 2B-2 On the Futility of Statistical Power Optimization Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., Jason Cong, Puneet Gupta, John Lee (Univ. of Cali- United States) fornia, Los Angeles, United States) 3A-2 Synthesis of Networks on Chips for 3D Systems 2B-3 Timing Driven Power Gating in High-Level Syn- on Chips thesis Srinivasan Murali, Ciprian Seiculescu (EPFL, Shih-Hsu Huang, Chun-Hua Cheng (Chung Yuan Switzerland), Luca Benini (Univ. of Bologna, Italy), Christian Univ., Taiwan) Giovanni De Micheli (EPFL, Switzerland) 2B-4 Congestion-Aware Power Grid Optimization for 3A-3 An Application-centered Design Flow for Self Re- 3D Circuits Using MIM and CMOS Decoupling Ca- configurable Systems Implementation pacitors Fabio Cancare, Marco Domenico Santambrogio, Do- Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sap- natella Sciuto (Politecnico di Milano, Italy) atnekar (Univ. of Minnesota, United States) 37 38 39 3A-4 System-Level Process Variability Compensation Tuesday, January 20, 15:55 - 18:00 Room 416+417 Wednesday, January 21, 9:00 - 10:00 on Memory Organizations. On the Scalability of Session 3D: Special Session: Hardware Dependent Multi-Mode Memories Software for Multi- and Many-Core Embed- Wednesday, January 21, 9:00 - 10:00 Small Auditorium, 5F Concepcion´ Sanz, Manuel Prieto, Jose´ Ignacio ded Systems Session 2K: Keynote Session II Chair: Kazutoshi Wakabayashi – NEC Corp., Gomez´ (Univ. Complutense de Madrid, Spain), An- Organizers: Rainer Doemer – Univ. of California, Japan tonis Papanikolaou, Francky Catthoor (Inter-Univ. Mi- Irvine, United States croelectronics Center, Belgium) Andreas Gerstlauer – Univ. of Texas, Automated Synthesis and Verification of Embedded Tuesday, January 20, 15:55 - 18:00 Room 413 Austin, United States Systems: Wishful Thinking or Reality? Session 3B: Advances in Timing Analysis and Model- Wolfgang Mueller – Univ. of Paderborn, Wolfgang Rosenstiel (Wilhelm-Schickard-Institute for Infor- ing Germany matics, Univ. of Tuebingen, Germany) Chairs: Shih-Hsu Huang – Chung Yuan Christian 3D-1 Introduction to Hardware-dependentSoftware De- Wednesday, January 21, 10:15 - 12:20 Univ., Taiwan sign Wednesday, January 21, 10:15 - 12:20 Room 411+412 Atsushi Takahashi – Tokyo Inst. of Tech., Rainer Domer¨ (Univ. of California, Irvine, United Session 4A: System Level Architectures Japan States), Andreas Gerstlauer (Univ. of Texas, Austin, Chair: Samar Abdi – Univ. of California, Irvine, United States), Wolfgang M¨uller (Univ. of Paderborn, 3B-1 Accelerating Statistical Static Timing Analysis United States Using Graphics Processing Units Germany) 4A-1 Computation and Data Transfer Co-Scheduling Kanupriya Gulati, Sunil P. Khatri (Texas A&M Univ., 3D-2 Using a Dataflow abstracted Virtual Prototype for for Interconnection Bus Minimization United States) HdS-Design Cathy Qun Xu (Univ. of Texas, Dallas, United States), Wolfgang Ecker, Stefan Heinen, Michael Velten (Infi- 3B-2 Trade-off Analysis between Timing Error Rate and Chun Jason Xue, Bessie C Hu (City Univ. of Hong neon Technologies AG, Germany) Power Dissipation for Adaptive Speed Control Kong, Hong Kong), Edwin H.M. Sha (Univ. of Texas, with Timing Error Prediction 3D-3 Needs and Trends in Embedded Software Devel- Dallas, United States) Hiroshi Fuketa, Masanori Hashimoto, Yukio Mit- opment for Consumer Electronics 4A-2 Prototyping Pipelined Applications on a Hetero- suyama, Takao Onoye (Osaka Univ., Japan) Yasutaka Tsunakawa (Sony Corp., Japan) geneous FPGA Multiprocessor Virtual Platform 3B-3 Statistical Analysis of On-Chip Power Grid Net- 3D-4 Hardware-dependent Software Synthesis for Antonino Tumeo, Marco Branca, Lorenzo Camerini, works by Variational Extended Truncated Bal- Many-Core Embedded Systems Marco Ceriani (Politecnico di Milano, Italy), Mat- anced Realization Method Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, teo Monchiero (HP Labs, United States), Gianluca Duo Li, Sheldon Tan (Univ. of California, Riverside, Yonghyun Hwang, Lochi Yu, Daniel Gajski (Univ. of Palermo, Fabrizio Ferrandi, Donatella Sciuto (Politec- United States), Gengsheng Chen, Xuan Zeng (Fudan California, Irvine, United States) nico di Milano, Italy) Univ., China) 4A-3 Variability-Aware Robust Design Space Explo- 3B-4 Bound-Based Identification of Timing-Violating ration of Chip Multiprocessor Architectures Paths Under Variability Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria Lin Xie, Azadeh Davoodi (Univ. of Wisconsin at Madi- (Politecnico di Milano, DEI, Italy) son, United States) 4A-4 Partial Conflict-Relieving Programmable Address 3B-5 Adaptive Techniques for Overcoming Perfor- Shuffler for Parallel Memories in Multi-Core Pro- mance Degradation due to Aging in Digital Cir- cessor cuits Young-Su Kwon, Bon-Tae Koo, Nak-Woong Eum Sanjay Kumar, Chris Kim, Sachin S. Sapatnekar (ETRI, Republic of Korea) (Univ. of Minnesota, United States) 4A-5 HitME: Low Power Hit MEmory Buffer for Embed- ded Systems Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic (Univ. of New South Wales, Australia)
40 41 42 Wednesday, January 21, 10:15 - 12:20 Room 413 4C-3 High Performance On-Chip Differential Signaling 4D-4 Addressing Thermal and Power Delivery Bottle- Session 4B: Beyond Traditional Floorplanning and Using Passive Compensation for Global Commu- necks in 3D Circuits Placement nication Sachin S. Sapatnekar (Univ. of Minnesota, United Chair: Shigetoshi Nakatake – Univ. of Ki- Ling Zhang, Yulei Zhang (Univ. of California, San States) takyushu, Japan Diego, United States), Akira Tsuchiya (Kyoto Univ., 4D-5 The Road to 3D EDA Tool Readiness 4B-1 Signal Skew Aware Floorplanning and Bumper Japan), Masanori Hashimoto (Osaka Univ., Japan), Charles Chiang, Subarna Sinha (Synopsys, United Signal Assignment Technique for Flip-Chip Ernest Kuh (Univ. of California, Berkeley, United States) Cheng-Yu Wang, Wai-Kei Mak (National Tsing Hua States), Chung-Kuan Cheng (Univ. of California, San Wednesday, January 21, 13:30 - 15:35 Univ., Taiwan) Diego, United States) Wednesday, January 21, 13:30 - 15:35 Room 411+412 4B-2 A Novel Thermal Optimization Flow Using Incre- 4C-4 Noise Minimization During Power-Up Stage for a Session 5A: Energy-Aware System Level Design mental Floorplanning for 3D ICs Multi-Domain Power Network Methodology Xin Li, Yuchun Ma, Xianlong Hong (Tsinghua Univ., Wanping Zhang (Qualcomm Inc./Univ. of California, Chairs: Chia-Lin Yang – National Taiwan Univ., China) San Diego, United States), Yi Zhu (Univ. of Cali- fornia, San Diego, United States), Wenjian Yu (Ts- Taiwan 4B-3 Analog Placement with Common Centroid and 1- inghua Univ., China), Amirali Shayan, Renshen Wang Juinn-Dar Huang – National Chiao Tung D Symmetry Constraints (Univ. of California, San Diego, United States), Zhi Univ. Linfu Xiao, Evangeline Young (Chinese Univ. of Hong Zhu (Qualcomm Inc., United States), Chung-Kuan 5A-1 Energy-aware HW/SW Co-synthesis Algorithm for Kong, Hong Kong) Cheng (Univ. of California, San Diego, United States) Heterogeneous NoC 4B-4 A Multilevel Analytical Placement for 3D ICs 4C-5s Parallel Transistor Level Circuit Simulation using Qingli Zhang, Mingyan Yu, Fangfa Fu, Peng Yun, Jun- Jason Cong, Guojie Luo (Univ. of California, Los An- Domain Decomposition Methods jie Song, Min Fan (Harbin Inst. of Tech., China) geles, United States) He Peng, Chung-Kuan Cheng (Univ. of California, 5A-2 System-Level Exploration Tool for Energy-Aware 4B-5 Exploring Adjacency in Floorplanning San Diego, United States) Memory Management in the Design of Multidi- Jia Wang, Hai Zhou (Northwestern Univ., United 4C-6s Fast Circuit Simulation on Graphics Processing mensional Signal Processing Systems States) Units Florin Balasa (Southern Utah Univ., United States), Wednesday, January 21, 10:15 - 12:20 Room 414+415 Kanupriya Gulati (Texas A&M Univ., United States), Ilie I. Luican (Univ. of Illinois, Chicago, United States), Session 4C: Signal/Power Integrity and Simulation John F. Croix (Nascentric, Inc., United States), Sunil Hongwei Zhu (ARM, Inc., United States), Doru Chairs: Hideki Asai – Shizuoka Univ., Japan P. Khatri (Texas A&M Univ., United States), Rahm V. Nasui (American International Radio, Inc., United Sheldon Tan – Univ. of California, River- Shastry (Nascentric, Inc., United States) States) side, United States Wednesday, January 21, 10:15 - 12:20 Room 416+417 5A-3 Systematic Architecture Exploration based on 4C-1 Stochastic Current Prediction Enabled Frequency Session 4D: Special Session: Challenges in 3D Inte- Optimistic Cycle Estimation for Low Energy Em- Actuator for Runtime Resonance Noise Reduc- grated Circuit Design bedded Processors tion Organizer: Sachin Sapatnekar – Univ. of Minnesota, Ittetsu Taniguchi (Osaka Univ., Japan), Murali Jaya- Yiyu Shi (Univ. of California, Los Angeles, United United States pala (IMEC vzw., Belgium), Praveen Raghavan, States), Jinjun Xiong, Howard Chen (IBM, United Francky Catthoor (IMEC vzw./K.U.Leuven, Belgium), 4D-1 Three-Dimensional Integration Technology and States), Lei He (Univ. of California, Los Angeles, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai Integrated Systems United States) (Osaka Univ., Japan) Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu 4C-2 Fast Analysis of Nontree-Clock Network Consid- Tanaka (Tohoku Univ., Japan) 5A-4 A Framework for Estimating NBTI Degradation of ering Environmental Uncertainty by Parameter- Microarchitectural Components 4D-2 A 3D Prototyping Chip based on a Wafer-level ized and Incremental Macromodeling Michael DeBole, Ramakrishnan Krishnan (Pennsyl- Stacking Technology Hai Wang (Univ. of California, Riverside, United vania State Univ., United States), Varsha Balakrish- Nobuaki Miyakawa (Honda Research Institute, States), Hao Yu (Berkeley Design Automation, United nan, Wenping Wang (Arizona State Univ., United Japan) States), Sheldon X.D. Tan (Univ. of California, River- States), Hong Luo, Yu Wang (Tsinghua Univ., China), 4D-3 CAD Challenges for 3D ICs side, United States) Yuan Xie (Pennsylvania State Univ., United States), David Kung, Ruchir Puri (IBM Corp., United States) Yu Cao (Arizona State Univ., United States), N. Vi- jaykrishnan (Pennsylvania State Univ., United States)
43 44 45 Wednesday, January 21, 13:30 - 15:35 Room 413 5C-2 Automated Design and Optimization of Circuits in Wednesday, January 21, 15:55 - 18:00 Session 5B: Design for Manufacturing and Reliability Emerging Technologies Rajesh A. Thakker, Chaitanya Sathe, Angada Wednesday, January 21, 15:55 - 18:00 Room 411+412 Chair: Charles Chiang – Synopsys, United Session 6A: System Level Simulation and Modeling States B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil (IIT Bombay, India) Chairs: Vincent J Mooney – Georgia Inst. of 5B-1 Efficient Analytical Determination of the SEU- Tech., United States induced Pulse Shape 5C-3 An Automated Design Approach for CMOS LDO Regulators Tsuneo Nakata – Fujitsu Laboratories Ltd., Rajesh Garg, Sunil P.Khatri (Texas A&M Univ., United Japan States) Samiran DasGupta, Pradip Mandal (IIT Kharagpur, India) 6A-1 Automatic Instrumentation of Embedded Soft- 5B-2 Post-Routing Redundant Via Insertion with Wire ware for High Level Hardware/Software Co- Spreading Capability 5C-4 A SCORE Macromodel for PLL Designs to An- alyze Supply Noise Interaction Issues at Behav- Simulation Cheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee (National Aimen Bouchhima, Patrice Gerin, Fred´ eric´ Petrot´ Chiao Tung Univ., Taiwan) ioral Level Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu (TIMA Lab., France) 5B-3 Accounting for Non-linear Dependence Using (National Central Univ., Taiwan) 6A-2 Fast and Accurate PerformanceSimulation of Em- Function Driven Component Analysis 5C-5 Gen-Adler: The Generalized Adler’s Equation for bedded Software for MPSoC Lerong Cheng, Puneet Gupta, Lei He (Univ. of Cali- Eric Cheung, Harry Hsieh (Univ. of California, River- fornia, Los Angeles, United States) Injection Locking Analysis in Oscillators Prateek Bhansali, Jaijeet Roychowdhury (Univ. of side, United States), Felice Balarin (Cadence Design 5B-4 Risk Aversion Min-Period Retiming under Pro- Minnesota, United States) Systems, United States) cess Variations 6A-3 Automatic Generation of Cycle Accurate and Cy- Jia Wang, Hai Zhou (Northwestern Univ., United Wednesday, January 21, 13:30 - 15:35 Room 416+417 Session 5D: Designers’ Forum: Consumer SoC cle Count Accurate Transaction Level Bus Models States) from a Formal Model 5B-5s Timing Analysis and Optimization Implications Chair: Yoshio Masubuchi – Toshiba Corp., Chen Kang Lo, Ren Song Tsay (National Tsing Hua of Bimodal CD Distribution in Double Patterning Japan Univ., Taiwan) Lithography 5D-1 Development of Full-HD Multi-standard Video 6A-4 A Combined Analytical and Simulation-Based Kwangok Jeong, Andrew B. Kahng (Univ. of Califor- CODEC IP Based on Heterogeneous Multiproces- Model for Performance Evaluation of a Reconfig- nia, San Diego, United States) sor Architecture urable Instruction Set Processor 5B-6s Scheduled Voltage Scaling for Increasing Lifetime Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Taka- Farhad Mehdipour (Kyushu Univ., Japan), Hamid in the Presence of NBTI fumi Yuasa, Toru Fujihira (Hitachi, Ltd., Japan), Noori (ISIT, Japan), Bahman Javadi (Amirkabir Lide Zhang, Robert Dick (Northwestern Univ., United Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Univ. of Tech., Iran), Hiroaki Honda (ISIT, Japan), Koji States) Seiji Mochizuki, Masaki Nobori (Renesas Technology Inoue, Kazuaki Murakami (Kyushu Univ., Japan) Corp., Japan) Wednesday, January 21, 13:30 - 15:35 Room 414+415 Wednesday, January 21, 15:55 - 18:00 Room 413 5D-2 A 65nm Dual-mode Baseband and Multimedia Ap- Session 5C: Analog, RF and Mixed-Signal CAD Session 6B: Chip and Package Routing Techniques plication Processor SoC with Advanced Power Chairs: Eric Keiter – Sandia National Laborato- and Memory Management Chairs: Ting-Chi Wang – National Tsing Hua ries, United States Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Univ., Taiwan Chin-Fong Chiu – National Chip Imple- Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshi- Yasuhiro Takashima – Univ. of Ki- mentation Center, Taiwan hiro Hattori, Shinichi Yoshioka (Renesas Technology takyushu, Japan 5C-1 Efficiently Finding the ’Best’ Solution with Multi- Corp., Japan) 6B-1 Efficient Simulated Evolution Based Rerouting Objectives from Multiple Topologies in Topology 5D-3 UniPhier: Series Development and SoC Manage- and Congestion-Relaxed Layer Assignment on 3- Library of Analog Circuit ment D Global Routing Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li (National Shibuya (Fujitsu Laboratories Ltd., Japan) Seiji Horii, Hisato Yoshida (Panasonic Corp., Japan) Chiao Tung Univ., Taiwan) 6B-2 FastRoute 4.0: Global Router with Efficient Via Minimization Yue Xu, Yanheng Zhang, Chris Chu (Iowa State Univ., United States)
46 47 48 6B-3s High-Performance Global Routing with Fast Over- Thursday, January 22, 9:00 - 10:00 7B-2 Complete-k-Distinguishability for Retiming and flow Reduction Resynthesis Equivalence Checking without Re- Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang Thursday, January 22, 9:00 - 10:00 Small Auditorium, 5F stricting Synthesis (National Taiwan Univ., Taiwan) Session 3K: Keynote Session III Nikolaos Liveris, Hai Zhou (Northwestern Univ., 6B-4s IO Connection Assignment and RDL Routing for Chair: Kazutoshi Wakabayashi – NEC Corp., United States), Prithviraj Banerjee (HP Labs, United Flip-Chip Designs Japan States) Jin-Tai Yan, Zhi-Wei Chen (Chung Hua Univ., Taiwan) From Restrictive to Prescriptive Design 7B-3 Disjunctive Transition Relation Decompositions 6B-5 On Using SAT to Ordered Escape Problems Leon Stok (IBM, United States) for Multithreaded Image Computation Lijuan Luo, Martin D.F.Wong (Univ. of Illinois, Urbana- Thursday, January 22, 10:15 - 12:20 Stergios Stergiou, Jawahar Jain (Fujitsu Laboratories Champaign, United States) of America, United States) Thursday, January 22, 10:15 - 12:20 Room 411+412 7B-4 Multi-Clock SVA Synthesis without Re-writing 6B-6 A Fast Longer Path Algorithm for Routing Session 7A: Compilation Techniques for Embedded Grid with Obstacles using Biconnectivity based Jiang Long, Andrew Seawright, Paparao Kavalipati Systems Length Upper Bound (Mentor Graphics Corp., United States) Chairs: Hiroyuki Tomiyama – Nagoya Univ., Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi 7B-5 Automatic Formal Verification of Clock Domain Japan (Tokyo Inst. of Tech., Japan) Crossing Signals Maziar Goudarzi – Kyushu Univ., Japan Wednesday, January 21, 15:55 - 18:00 Room 416+417 Bing Li, Chris Ka-Kei Kwok (Mentor Graphics Corp., 7A-1 Thermal-aware Post Compilation for VLIW Archi- Session 6D: Designers’ Forum: ESL Design Methods United States) tectures Thursday, January 22, 10:15 - 12:20 Room 414+415 Wen-Wen Hsieh, TingTing Hwang (National Tsing ESL Design Methods Session 7C: Scan Test Generation Moderator: Takashi Hasegawa – Fujitsu Microelec- Hua Univ., Taiwan) tronics Ltd., Japan 7A-2 A Software Solution for Dynamic Stack Manage- Chair: Satoshi Ohtake – NAIST, Japan Panelists: Simon Bloch – Mentor Graphics Corp., ment on Scratch Pad Memory 7C-1 Fast False Path Identification Based on Func- United States Arun Kannan, Aviral Shrivastava, Amit Pabalkar, tional Unsensitizability Using RTL Information Ahmed Jerraya – CEA-LETI, France Jong-eun Lee (Arizona State Univ., United States) Yuki Yoshikawa (Hiroshima City Univ., Japan), Gabriela Nicolescu – Ecole Polytechnique 7A-3 Compiler-Managed Register File Protection for Satoshi Ohtake (NAIST, Japan), Tomoo Inoue (Hi- de Montreal, Canada Energy-Efficient Soft Error Reduction roshima City Univ., Japan), Hideo Fujiwara (NAIST, Shigeru Oho – Hitachi, Ltd., Japan Jongeun Lee, Aviral Shrivastava (Arizona State Univ., Japan) Koichiro Yamashita – Fujitsu Labs. Ltd., United States) 7C-2 Conflict Driven Scan Chain Configurationfor High Japan 7A-4 Code Decomposition and Recomposition for En- Transition Fault Coverage and Low Test Power hancing Embedded Software Performance Zhen Chen, Boxue Yin, Dong Xiang (Tsinghua Univ., Youngchul Cho (SAIT, Samsung Electoronics, Re- China) public of Korea), Kiyoung Choi (Seoul National Univ., 7C-3 Dynamic Test Compaction for a Random Test Republic of Korea) Generation Procedure with Input Cube Avoidance Thursday, January 22, 10:15 - 12:20 Room 413 Irith Pomeranz (Purdue Univ., United States), Sud- Session 7B: Sequential Design Verification hakar Reddy (Univ. of Iowa, United States) Chairs: Yosinori Watanabe – Cadence, United 7C-4 Detectability of Internal Bridging Faults in Scan States Chains Chung-Yang Huang – National Taiwan Fan Yang (Univ. of Iowa, United States), Sreejit Univ., Taiwan Chakravarty, Narendra Devta-Prasanna (LSI Corp., United States), Sudhakar M. Reddy (Univ. of Iowa, 7B-1 Dependent Latch Identification in the Reachable United States), Irith Pomeranz (Purdue Univ., United State Space States) Chen-Hsuan Lin, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
49 50 51 7C-5 Fault Modeling and Testing of Retention Flip- 8A-3 Analyzing and Optimizing Energy Efficiency of Al- Thursday, January 22, 13:30 - 15:35 Room 414+415 Flops in Low Power Designs gorithms on DVS Systems: a First Step towards Session 8C: Verification, Test, and Yield Bing-Chuan Bai (National Taiwan Univ., Taiwan), Au- Algorithmic Energy Minimization Chairs: Yasuo Sato – Hitachi, Ltd., Japan gusli Kifli (Faraday Technology Corp., Taiwan), Chien- Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Sudhakar M. Reddy – Univ. of Iowa, Mo Li (National Taiwan Univ., Taiwan), Kun-Cheng Hiroaki Takada (Nagoya Univ., Japan) United States Wu (Faraday Technology Corp., Taiwan) 8A-4 Novel Task Migration Framework on Configurable 8C-1 Self-Adjusting Constrained Random Stimulus Thursday, January 22, 10:15 - 12:20 Room 416+417 Heterogeneous MPSoC Platforms Generation Using Splitting Evenness Evaluation Session 7D: Designers’ Forum: Analog/RF Circuit De- Hao Shen, Fred´ eric´ Petrot´ (TIMA Lab., France) and XOR Constraints signs Thursday, January 22, 13:30 - 15:35 Room 413 Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao Chair: Makoto Ikeda – Univ. of Tokyo, Japan Session 8B: Emerging Design Methodologies and Ap- (Tsinghua Univ., China) plications 7D-1 Design Methods for Pipeline & Delta-Sigma A-to- 8C-2 Diagnosing Integrator Leakage of Single-Bit First- D Converters with Convex Optimization Chair: Chin-Long Wey – National Central Univ., Order Delta-Sigma Modulator Using DC Input Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Taiwan Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Shiro Sakiyama, Yosuke Mitani, Masao Takayama, 8B-1 A Novel Toffoli Network Synthesis Algorithm for Huang (National Taiwan Univ., Taiwan) Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Reversible Logic 8C-3 Path Selection for Monitoring Unexpected Sys- Dosho (Panasonic Corp., Japan) Yexin Zheng, Chao Huang (Virginia Tech, United tematic Timing Effects 7D-2 A Low-Jitter 1.5-GHz and Large-EMI reduction States) Nicholas Callegari, Pouria Bastani, Li-C. Wang 10-dBm Spread-Spectrum Clock Generator for 8B-2 A Cycle-Based Synthesis Algorithm for Re- (Univ. of California, Santa Barbara, United States), Serial-ATA versible Logic Sreejit Chakravarty, Alexander Tetelbaum (LSI Corp., Takashi Kawamoto, Masaru Kokubo (Hitachi, Ltd., Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, United States) Japan) Morteza Saheb Zamani (Amirkabir Univ. of Tech., 8C-4 Design for Burn-In Test: A Technique for Burn-In 7D-3 RF-Analog Circuit Design in Scaled SoC Iran) Thermal Stability under Die-to-Die Parameter Vari- Nobuyuki Itoh, Mototsugu Hamada (Toshiba Corp., 8B-3 Array Like Runtime Reconfigurable MIMO Detec- ations Japan) tors for 802.11n WLAN: A Design Case Study Mesut Meterelliyoz, Kaushik Roy (Purdue Univ., 7D-4 An Approach to the RF-LSI Design for Ubiquitous Pankaj Bhagawat, Rajballav Dash, Gwan Choi (Texas United States) Communication Appliances A&M Univ., United States) 8C-5 Test Infrastructure Design for Core-Based Yuichi Kado, Mitsuru Harada (NTT, Japan) 8B-4 Mapping method for Dynamically Reconfigurable System-on-Chip Under Cycle-Accurate Thermal Architecture Constraints Thursday, January 22, 13:30 - 15:35 Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Thomas Edison Yu, Tomokazu Yoneda (NAIST, Thursday, January 22, 13:30 - 15:35 Room 411+412 Takashi Yoshikawa, Shigehiro Asano (Toshiba Corp., Japan), Krishnendu Chakrabarty (Duke Univ., United Session 8A: High-Level Design and Scheduling Japan) States), Hideo Fujiwara (NAIST, Japan) Chairs: Yuichi Nakamura – NEC Corp., Japan 8B-5 A Criticality-Driven Microarchitectural Three Di- Keishi Sakanushi – Osaka Univ., Japan mensional (3D) Floorplanner 8A-1 Improving Scalability of Model-Checking for Min- Srinath Sridharan, Michael DeBole, Guangyu Sun, imizing Buffer Requirements of Synchronous Yuan Xie, Vijaykrishnan Narayanan (Pennsylvania Dataflow Graphs State Univ., United States) Nan Guan (Northeastern Univ., China), Zonghua Gu (HKUST, China), Wang Yi (Uppsala Univ., Sweden), Ge Yu (Northeastern Univ., China) 8A-2 A Reverse-Encoding-based on-chip AHB Bus Tracer for Efficient Circular Buffer Utilization Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang (National Sun Yat-Sen Univ., Taiwan)
52 53 54 Thursday, January 22, 13:30 - 15:35 Room 416+417 Thursday, January 22, 15:55 - 18:00 Room 413 Tutorials Session 8D: Designers’ Forum: Near-Future SoC Session 9B: Emerging Technologies Architectures – Can Dynamically Reconfig- Chair: Mehdi Baradaran Tahoori – Northeastern Tutorial 1 (FULL DAY) urable Processors be a Key Technology? Univ., United States Monday, January 19, 9:30–17:00 Room 411+412 Near-Future SoC Architectures – Can Dynamically Re- 9B-1 High-Speed Low-Power FinFET Based Domino Software Development and Programming of Multi- configurable Processors be a Key Technology? Logic core LSI Seid Hadi Rasouli (Univ. of California, Santa Barbara, Moderator: Hideharu Amano – Keio Univ., Japan Organizer: Ahmed Amine Jerraya – TIMA, France Panelists: Toru Awashima – NEC Corp., Japan United States), Hanpei Koike (AIST, Japan), Kaustav Banerjee (Univ. of California, Santa Barbara, United Speakers: Wayne Wolf – Georgia Institute of Technol- Hisanori Fujisawa – Fujitsu Laboratories ogy, United States Ltd., Japan States) Damir Jamsek – IBM, United States Naohiko Irie – Hitachi, Ltd., Japan 9B-2 A Stochastic Perturbative Approach to Design a Takashi Miyamori – Toshiba Corp., Japan Defect-Aware Thresholder in the Sense Amplifier Hiroyuki Tomiyama – Nagoya University, Tony Stansfield – Panasonic Europe Ltd., of Crossbar Memories Japan Great Britain M. Haykel Ben Jamaa (EPFL, Switzerland), David Fabien Clermidy – CEA-LETI, France Atienza (Univ. Complutense de Madrid, Spain), Yusuf LSI designs integrate an increasing number of heteroge- Thursday, January 22, 15:55 - 18:00 Leblebici, Giovanni De Micheli (EPFL, Switzerland) neous programmable units (CPU, ASIP and DSP subsys- Thursday, January 22, 15:55 - 18:00 Room 411+412 9B-3 An Alternate Design Paradigm for Robust Spin- tems) and sophisticated communication interconnects. In Session 9A: Memory Systems Simulation and Opti- Torque Transfer Magnetic RAM (STT MRAM) from conventional computers programming is based on an oper- mization Circuit/Architecture Perspective ating system that fully hide the underlying hardware architec- Chair: Zonghua Gu – HKUST, Hong Kong Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik ture. Unlike classic computers, the design of LSI includes the 9A-1 Soft Lists: A Native Index Structure for NOR- Roy (Purdue Univ., United States) building of application specific memory architecture and spe- Flash-Based Embedded Devices 9B-4 A Design Methodology and De- cific interconnect and other kinds of hardware components Li-Pin Chang, Chen-Hui Hsu (National Chiao Tung vice/Circuit/Architecture Compatible Simulation required to efficiently executing the software for a well defined Univ., Taiwan) Framework for Low-Power Magnetic Quantum class of applications. In this case, the programming model 9A-2 Energy-aware Register File Re-Partitioning for Cellular Automata Systems hides both hardware and software interfaces that may include Clustered VLIW Architectures Charles Augustine, Behtash Behin-Aein, Xuanyao sophisticated communication and synchronization concepts Chun Jason Xue, Minming Li, Yingchao Zhao, Bessie Fong, Kaushik Roy (Purdue Univ., United States) to handle parallel programs running on the processors. When the processors are heterogeneous, multiple software stacks Hu (City Univ. of Hong Kong, Hong Kong) 9B-5 Reconfigurable Double Gate Carbon Nanotube may be required. Additionally, when specific Hardware pe- 9A-3 Memory SubsystemSimulationin Software TLM/T Field Effect Transistor Based Nanoelectronic Ar- ripherals are used, the development of Hardware dependent Models chitecture Software (HdS) requires a long, fastidious and error prone Eric Cheung, Harry Hsieh (Univ. of California, River- Bao Liu (Univ. of Texas, San Antonio, United States) development and debug cycle. This full day tutorial deals with side, United States), Felice Balarin (Cadence Design Thursday, January 22, 15:55 - 18:00 Room 416+417 challenges and opportunities for the programming of such Systems, United States) Session 9D: Special Session: Dependable VLSI: De- complex devices. 9A-4 Exact and Fast L1 Cache Simulation for Embed- vice, Design and Architecture – How should • ded Systems they cooperate ? – Prof. Wayne Wolf will introduce and survey principles Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, for the programming of multicore LSI. Organizer: Shuichi Sakai – Univ. of Tokyo, Japan Tatsuo Ohtsuki (Waseda Univ., Japan) • Dr. Damir Jamsek will detail How to accelerate CAD 9A-5 Accuracy-Aware SRAM: A Reconfigurable Low Dependable VLSI: Device, Design and Architecture – applications with CUDA programming environment. Power SRAM Architecture for Mobile Multimedia How should they cooperate ? – • Prof. Hiroyuki Tomiyama will introduce and survey prin- Applications Organizer: Shuichi Sakai – Univ. of Tokyo, Japan ciples for RTOS (real-time operating systems) for mul- Minki Cho (Georgia Inst. of Tech., United States), Panelists: Hidetoshi Onodera – Kyoto Univ., Japan ticore LSI. Jason Schlessman (Princeton Univ., United States), Hiroto Yasuura – Kyushu Univ., Japan Wayne Wolf, Saibal Mukhopadhyay (Georgia Inst. of James C. Hoe – Carnegie Mellon Univ., • Dr. Fabien Clermidy will explore programming future Tech., United States) United States LSI based on Network on Chip.
55 56 57 Tutorial 2 (HALF DAY) Tutorial 3 (HALF DAY) Tutorials 4 and 5 (TWO HALF DAYs, morning and af- Monday,January19,9:30–12:30 Room413 Monday, January 19, 9:30–12:30 Room 414+415 ternoon) Formal Methods for C-Based Embedded System Statistical Design on the Verge of Maturity: Revis- Monday, January 19, 9:30–12:30 Room 416+417 Design Verification — Technical Trends and Prac- iting the Foundation Monday, January 19, 14:00–17:00 Room 416+417 tical Aspects — Circuit Reliability: Modeling, Simulation, and Re- Organizer: Michael Orshansky – University of Texas, silient Design Solutions Organizers: Masahiro Fujita – University of Tokyo, Japan Austin, United States Section I (morning): Reliability Mechanisms and Speakers: Masahiro Fujita – University of Tokyo, Japan Speakers: Sani Nassif – IBM, United States the Impact on IC Design Alan J. Hu – University of British Columbia, Michael Orshansky – University of Texas, Section II (afternoon): Circuit Aging Prediction and Canada Austin, United States Resilient Design Andy Chou – Coverity Inc., United States Statistical analysis and design (optimization) methods Recently there has been significant progress in formal have been actively researched over the last five years with Organizer: Yu (Kevin) Cao – Arizona State University, analysis on C/C++ programs. New bugs in Linux kernels, hundreds of papers published on the subject. Many novel United States which have several million lines of codes, have been found concepts and models have been presented, and alternative Section I by formal analysis methods. In embedded system designs, algorithms for SSTA and optimization developed. In this tu- Speakers: Yu (Kevin) Cao – Arizona State University, C-based hardware designs are becoming common, and the torial, we will re-assess the status of statistical analysis and United States techniques developed for C/C++ are expected to be applied design methodologies; evaluate evidence for its practical use, Kaushik Roy – Purdue University, United to hardware design descriptions as well. There are basically and point out the limitations of some of the assumptions States three approaches to the verification problem: static analy- made in the early years of the discipline. Section II sis based on local traces of the descriptions, model checking Physical sources of variability: This tutorial will review the Speakers: Marek Patyra – Intel, United States with automatic abstraction/reduction of the descriptions, and latest sets of variability data collected from state-of-the-art Subhasish Mitra – Stanford University, equivalence checking with efficient identification of the differ- production lines. The validity of some key assumptions often United States ences between the descriptions. With appropriate usages, made about data is specifically reviewed: The aggressive scaling of CMOS technology to sub-45nm all of the three approaches give practical values to designers, • Relative amount of variations inter-chip and intra-chip nodes has inevitably leads to multiple reliability concerns, and large and real-life design descriptions could be formally • such as negative-bias-temperature-instability (NBTI), soft analyzed. The point here is how and where the formal meth- Relative amounts of systematic/spatial and truly ran- errors, and time-dependent-dielectric-breakdown (TDDB). ods are applied. Concentrating on their practical aspects, this dom variations These effects manifest themselves as the temporal degrada- tutorial gives the state-of-the-art formal methods and imple- • Designer control of variations, i.e. dependence of vari- tion of transistor parameters, profoundly affecting all aspects mented tools for C based design descriptions. The tutorial ation on device geometry and circuit structure of circuit performance. While traditional research in this area has the following presentations: • Methods for reducing the impact of variability, regularity has focused only on technology improvement, ignoring these • Prof. Masahiro Fujita gives an overview of the three for intra-chip, and adaptation for inter-chip effects in the design process causes an excessive amount of approaches for the formal analysis of C-based design Statistical timing analysis methods: The state-of-the-art over-margining. As these reliability concerns become much descriptions. SSTA methods and the patterns of their adoption in industry more severe with continuous scaling, it is critical to under- • Dr. Andy Chou presents various static checking meth- will be presented. Specifically, this tutorial will describe the stand, simulate, and adaptively mitigate their impact during ods and implemented tools with their applications to use of SSTA as a multi-corner robustness checker. the design stage. real life C descriptions. Statistical/robust optimization: This tutorial will revisit the In this context, this tutorial will present basic and more ad- state of the art in statistical optimization methods for timing vanced topics on reliability modeling, simulation, and design • Prof. Alan J. Hu presents model checking based formal and power yield. solutions, including two sections: verification of C-based design descriptions with various Section I: Reliability Mechanisms and the Impact on IC De- efficiency increasing techniques sign • Prof. Masahiro Fujita describes formal equivalence • The underlying reliability mechanisms checking methods and implemented tools targeting de- • Compact modeling and analysis techniques of circuit signs under typical system level design flows. aging • Circuit design for reliability in both logic and memory circuits 58 59 60 Section II: Circuit Aging Prediction and Resilient Design Tutorial 7 (HALF DAY) ASP-DAC 2009 at a Glance • Circuit reliability analysis and prediction Monday,January19,14:00–17:00 Room413 Memory Architectures and Software Transforma- • Test and validation for circuit and product reliability Monday, January 19 tions for System Level Design • Latest design practices for resilience FULL-DAY Tutorial Organizer: Nikil Dutt – University of California, Irvine, This tutorial will conclude with a discussion on future reli- United States TUTORIAL 1 (9:30–17:00) Room 411+412 ability challenges, helping shed light on the need of resilient Speakers: Stylianos Mamagkakis – IMEC, Belgium design techniques and tools. Software Development and Programming Preeti Panda – Indian Institute of Technol- of Multicore LSI ogy, Delhi, India Tutorial 6 (HALF DAY) Memories continue to dominate the cost, performance and Monday, January 19, 14:00–17:00 Room 414+415 power of LSI designs. As we move towards sub-nanometer HALF-DAY Tutorials Recent Advances in Low-Leakage VLSI Design technologies, memories are also susceptible to soft-errors TUTORIAL 2 (9:30–12:30) Room 413 and thus affect the reliability of LSI designs. Traditionally Organizer: Youngsoo Shin – KAIST, Korea memory issues are considered at a late stage in a system- Formal Methods for C-Based Embedded Speaker: Youngsoo Shin – KAIST, Korea level design flow, often resulting in designs that do not meet System Design Verification Kaushik Roy – Purdue University, United performance and/or power budgets, and with unnecessarily States large memory footprints for the LSI designs. A memory- TUTORIAL 3 (9:30–12:30) Room 414+415 This tutorial will discuss recent advances for designing low- aware system level design flow can address these prob- leakage VLSI circuits, as well as challenges and opportuni- Statistical Design on the Verge of Maturity: lems by customizing both the underlying memory architec- Revisiting the Foundation ties for future research and development. The main focus tures/organizations, as well as by transforming the system- will be on cell-based semi-custom design, where consider- level source code to generate an input for system-level design TUTORIAL 4 (9:30–12:30) Room 416+417 ing the interaction with other tools in standard design flow that is better tuned to the memory architectures and organi- when new scheme is adopted is very important. The tutorial zations. Such a ”memory-aware” system level design flow Circuit Reliability: Modeling, Simulation, will start from leakage estimation considering process varia- can result in LSI designs exhibiting superior performance, and Resilient Design Solutions tions, which is important to further optimization and design power and memory footprint characteristics. This half-day Section I: Reliability Mechanisms planning. The next part of the tutorial will be minimizing leak- tutorial will survey emerging memory architectural platforms age when circuit is in active, or in very short idle. Conven- and organizations, as well as software transformations that and the Impact on IC Design tional multiple threshold voltage technique will be discussed, enable tuning of system-level applications to exploit the un- TUTORIAL 5 (14:00–17:00) Room 416+417 but recent advances in the area of sequential circuit design derlying memory organizations and architectures to improve will be a focus. This includes the use of flip-flops of multiple performance, power and code size. Case studies on indus- Circuit Reliability: Modeling, Simulation, gate-length and mixed threshold voltages, and adopting clock trial LSI designs will demonstrate the efficacy of these ap- and Resilient Design Solutions skew scheduling for further reducing leakage of sequential proaches. circuits. We will then go on to discuss fast power-gating cir- Section II: Circuit Aging Prediction and cuits, including zigzag power-gating, multiple sleep modes, • Prof. Preeti Panda will survey traditional and emerg- Resilient Design etc. Run-time power-gating will be discussed as well. In the ing memory architectures and organizations, including third part of the tutorial, we will address several circuit tech- caches, scratchpad memories, buffers, and describe TUTORIAL 6 (14:00–17:00) Room 414+415 niques for reducing standby leakage. This includes standard possible ways to exploit them. Recent Advances in Low-Leakage power-gating, adaptive body-bias, dynamic voltage scaling, • Dr. Stylianos Mamagkakis will present CleanC, a set VLSI Design and combination of these. Again, the main focus will be on of techniques and tools that enable source code level recent advances in these circuit techniques and how to em- parallelizationand memory hierarchy/data reuse explo- TUTORIAL 7 (14:00–17:00) Room 413 ploy these circuits in cell-based semi-custom design. ration techniques/tools. Memory Architectures and Software Transformations for System Level Design
61 62 63 Tuesday, January 20 A B C D 8:30 Opening Session & Keynote Address I (Small Auditorium, 5F) 10:00 Break 10:15 1A (Room 411+412) 1B (Room 413) 1C (Room 414+415) 1D (Room 416+417) On-Chip Communication Dealing with Thermal Advances in Behavioral University Design Architectures Issues Synthesis Contest 12:20 Lunch Break / University Design Contest Discussion at ASP-DAC Site (Room 418) 13:30 2A (Room 411+412) 2B (Room 413) 2C (Room 414+415) 2D (Room 416+417)
64 Special Session: MPSoC and IP Power Analysis and Logic and Arithmetic EDA Acceleration Using Integration Optimization Optimization New Architectures 15:35 Coffee Break (Room 418) 15:55 3A (Room 411+412) 3B (Room 413) 3D (Room 416+417) System-Level Design of Special Session: Advances in Timing 3D Chips and Hardware Dependent Software for Analysis and Modeling Configurable Systems Multi-Core Embedded Systems 18:00
Wednesday, January 21 A B C D 9:00 Keynote Address II (Small Auditorium, 5F) 10:00 Break 10:15 4A (Room 411+412) 4B (Room 413) 4C (Room 414+415) 4D (Room 416+417) Beyond Traditional Special Session: System Level Signal/Power Integrity Floorplanning and Challenges in 3D Architectures and Simulation Placement Integrated Circuit Design 12:20 Lunch Break / Student Forum (Room 418) 65 13:30 5A (Room 411+412) 5B (Room 413) 5C (Room 414+415) 5D (Room 416+417) Energy-Aware System Design for Manufacturing Analog, RF and Designers’ Forum: Level Design and Reliability Mixed-Signal CAD Consumer SoC Methodology 15:35 Coffee Break (Room 418) 15:55 6A (Room 411+412) 6B (Room 413) 6D (Room 416+417) System Level Simulation Chip and Package Designers’ Forum Panel: and Modeling Routing Techniques ESL Design Methods 18:00 Banquet 18:30–20:30 (Room 501+502)
Thursday, January 22 A B C D 9:00 Keynote Address III (Small Auditorium, 5F) 10:00 Break 10:15 7A (Room 411+412) 7B (Room 413) 7C (Room 414+415) 7D (Room 416+417) Designers’ Forum: Compilation Techniques Sequential Design Scan Test Generation Analog/RF Circuit for Embedded Systems Verification Designs 12:20 Lunch Break 13:30 8A (Room 411+412) 8B (Room 413) 8C (Room 414+415) 8D (Room 416+417) 66 Emerging Design Designers’ Forum Panel: High-Level Design and Verification, Test, and Methodologies and Near-Future SoC Scheduling Yield Applications Architectures 15:35 Coffee Break (Room 418) 15:55 9A (Room 411+412) 9B (Room 413) 9D (Room 416+417) Memory Systems Special Session: Dependable VLSI: Simulation and Emerging Technologies Device, Design and Architecture Optimization – How Should They Cooperate? – 18:00 Information restaurants. Certain foreign currencies may be accepted at to Honmoku-Sankeien-mae. a limited number of hotels, restaurants and souvenir shops. MARITIME MUSEUM Proceedings: You can exchange your currency for Japanese Yen at foreign The site of the previous Nippon Maru, the former training ship ASP-DAC 2009 will be producing two versions of the ASP- exchange banks and other authorized money exchange of- for Japan’s Maritime Defense Force. The Yokohama Maritime DAC 2009 Proceedings; a bound paper version and a CD- fices with your passport. Museum, which specializes in ports and ships, is located next ROM version. All papers will be included in both versions. Electrical Appliances: to the Nippon Maru. Conference registration in any of the categories will include Electrical appliances are supplied on 100 volts in Japan. Hours: 10:00-17:00 (Closed Monday) Admission: Y600 copies of both versions of the ASP-DAC 2009 Proceedings. The frequency is 50 Hz in eastern Japan including Tokyo, Access: 5 min. walk from Minato-mirai Station Additional Proceedings will be available for purchase at the Yokohama and 60 Hz in western Japan including Kyoto and Other Information: Conference. Prices are as follows: Osaka. Paper Form: Y5,000; CD-ROM Form: Y2,000; Shopping: JAPANTOURIST ORGANIZATION Both versions of the proceedings will also be available for The business hours of most department stores are from http://www.jnto.go.jp/ purchase after the conference; please contact IEEE for the 10:00 to 20:00. They are open on Sundays and national hol- YOKOHAMA CONVENTION & VISITORS BUREAU bound version and ACM SIGDA for the CD-ROM version. idays, but may close on some weekday. Business hours of http://www.welcome.city.yokohama.jp/eng/tourism/ Banquet: retail shops differ from one another, but most shops operate NARITA AIRPORT Conference registrants are invited to attend a banquet to be from 10:00 to 20:00. Shops are open on Sundays and na- http://www.narita-airport.jp/en/ held on January 21, 2009. The banquet will be held from tional holidays. YES ! TOKYO http://www.tcvb.or.jp/english/ 18:30 to 20:30 at the fifth floor of conference center. Regular Sightseeing: Member and Non-member Conference registrants receive a http://www.city.yokohama.jp/ne/info/hotspotE.html ticket to the banquet when they register at the conference. Participants can get sightseeing information at the JTB Full-time students, Designers’ Forum-only registrants, and Travel desk in the Conference site during the Conference pe- Tutorial-only registrants wishing to attend the banquet will be riod. required to pay Y5,000 for a ticket when they register on site. CHINA TOWN Visa Application: Being the largest Chinese settlement in Japan, Chinatown is Without a legal visa, foreign participants may be denied entry always alive with people who come to enjoy Chinese food. into Japan. Please contact your nearest Japanese embassy It is also a fun place for shopping or just walking around its in order to ensure entry. Notice that the ASP-DAC 2009 many streets and alleys lined with colorful restaurants, shops Organizing Committee issues the invitation letters and sup- overflowing with Chinese goods and stores that sell exotic ports the VISA applications only for presenters of the confer- ingredients and Chinese medicines. ence papers. All the other attendees have to apply for VISA LANDMARK TOWER through their travel agents or by yourself. In some cases it 296 meters high with 70 stories above ground and three may take two months to obtain a legal visa. The following levels underground. It is Japan’s tallest skyscraper. A 40- Web page of Japanese embassy may be helpful. second ride on the world’s fastest elevator skyrockets you http://www.mofa.go.jp/j info/visit/visa/ to the 69th floor’s Sky Garden, the highest observatory in Insurance: Japan. The organizer cannot accept responsibility for accidents Hours: 10:00-21:00 Admission: Y1,000 which might occur. Delegates are encouraged to obtain travel Access: 3 min. walk from Minato-mirai Station insurance (medical, personal accident, and luggage) in their SANKEIEN GARDEN home country prior to departure. A purely Japanese-style landscape garden. Accenting the Climate: main garden is an impressive three-story pagoda and grace- The temperature in Yokohama during the period of the Con- ful garden bridges. Inside contains several old houses and ference ranges between 5◦C and 12◦C. farm buildings as well as Important Cultural Properties such Currency Exchange: as Rinshunkaku Villa and Chosukaku House. Only Japanese Yen(Y) is accepted at ordinary stores and Hours:9:00-16:30 Admission:Y500 Access: From Sakuragicho Sta., take Bus No. 8 or No. 125 67 68 69 Access to Pacifico Yokohama Venue Map/Room Assignment
• ASP-DAC Conference is held at “Conference Center.” • EDS Fair 2009 and System Design Forum 2009 are
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Tra By Train By Train & Shinkansen By Air ● 70 71 72 Electronic Design and Solution Fair 2009 System Design Forum 2009 at EDS Fair Poster Discussion, Student Forum The Japan Electronics and Information Technology Industries As- Coffee Break sociation (JEITA) will be hosting the Electronic Design and Solution Friday, January 23, 10:00–12:00, 12:45-16:30 Fair 2009 at the Pacifico Yokohama on January 22 (Thursday) and Annex Hall, Pacifico Yokohama 4F 23 (Friday), 2009. The goal of EDSFair is to introduce and disseminate information Registration: On-line registration will be available from Designers’ Forum about the latest design solutions, design technologies and EDA tech- December 2008 at http://www.edsfair.com/e Session D, Tutorial 4, 5 nologies required to produce the electronic systems and semicon- ductors for the IT applications that will form the foundation of the fu- Sponsor: Japan Electronics and Information Technol- ture information society, whose citizens will enjoy a ubiquitous com- ogy Industries Association (JEITA) Session C, puting environment. The fair thus contributes to the development of Support: Open SystemC Initiative (OSCI) Tutorial 3, 6 electronics and other IT-related industries. This will be the 16th time the fair has taken place, including its previous incarnation as the EDA JEITA EDA Technical Committee (EDA-TC) will host Sys- TechnoFair. tem Design Forum 2009 at Pacifico Yokohama, Japan. This JEITA forecasts that this year Japan’s electronics industry will year’s forum, consisting of 2 sessions, will be held January continuously have achieved a 3% increase over last year, growing for three consecutive years, reaching more than Y21.trillion since 23, 2009. 2006 when Japan’s electronics industry recovered to a market size The first session (10:00–12:00) will cover system-level of Y20.trillion for the first time in 5 years. Also, with the worldwide de- design language (SystemC), some effective methods for Session B, mand expansion for digital products, semiconductors and electronic addressing the design crisis of SoC (System-on-a-Chip). Tutorial 2, 7 components are expected to make sound growth and be placed more Session A, expectations on the related development of design technology and Easy-to-understand explanations of the latest standardiza- Tutorial 1 service. tion, STARC transaction-level modeling Guideline and intro- “Design the Future! Cutting edge Technologies Excite the Sense” Rehearsal Room duction of the cutting-edge design examples will be given for VIP, Lecturer & is the theme of this Electronic Design and Solution Fair 2009. You SystemC. Meeting Room will find on display world-class, cutting-edge technologies tailored for an age that demands new solutions. There are a variety of seminars The second session (12:45–16:30) will focus on predict of and a conference offering a wide range of up-to-date information. 32 nm process variations and design methodology in statis- There are open sessions catering to young engineers, new zones tics from the perspective of cutting-edge, and introduce the that bring together both Japanese and foreign venture businesses, Secretariat current state of design methodology on considering varia- File Checking as well as initiatives for promoting substantive technical exchanges Room between industry, academia and government. tions. It is the fervent desire of all of us in JEITA that EDSFair will con- Session 1: SystemC Users Forum 2009, January 23 2F tribute to enhancing the design technologies available to Japan’s electronic and IT industries, and also that both exhibitors and visi- (10:00–12:00) tors will be able to make the best use of the opportunities afforded Chair: T. Hasegawa (JEITA SystemC Working Group) by this event for conducting effective and fruitful exchanges of infor- On December 12, 2005, IEEE approved SystemC (IEEE Std. mation, and for generating new business. We greatly look forward to 1666-2005). Since then, SystemC that is a C-based lan- your visit at the upcoming EDSFair2009. guage, has been widely used as a standard language for Etsuhiko Shoyama both verification and system-level design flows in the fields Chairman of both verification and design. Included in this session Japan Electronics and Information Technology Industries Association Registration, are: 1) Update of SystemC current status and road map, Information, (JEITA) Cloak presented by OSCI, 2) Easy-to-understand explanations of STARC transaction-level modeling Guideline, and 3) Exam- ples of design-related SystemC. Session 2: Nano-Scale Physical Design Forum, Jan- uary 23 (12:45-16:30) Chair: T. Kanamoto (JEITA Nano-Scale Physical Design Working Group) Along with recent advances in semiconductor devices and in- Conference Center Map terconnection technologies, new issues are emerging in cur- rent design methodology. Various approaches, such as new 73 74 75 libraries or design schemes, have been developed to solve these issues but left un-standardized even after those be- come commonplace. It prevents semiconductor manufactur- ers and their customers from smooth exchanging design in- formation. In this session, the following topics will be presented to overview the current status of variation-aware design methodology: 1) Variations of device characteristics in the process of next-generation, 2) Variations of circuit character- istics in the process of next-generation, 3) Process variations of SRAM and design methodology in statistics from the per- spective of cutting-edge, 4) Design methodology for reducing variation and variations in statistics.
Note: Most of the presentations at the System Design Forum 2009 will be given in Japanese.
For more information, visit the following web site: http://www.edsfair.com/e/.
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