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Revisiting Rowhammer: an Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

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Revisiting Rowhammer: an Experimental Analysis of Modern DRAM Devices and Mitigation Techniques Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques Jeremie S. Kim§† Minesh Patel§ A. Giray Yağlıkçı§ Hasan Hassan§ Roknoddin Azizi§ Lois Orosa§ Onur Mutlu§† §ETH Zürich †Carnegie Mellon University RowHammer is a circuit-level DRAM vulnerability, rst rig- RowHammer is a serious challenge for system designers orously analyzed and introduced in 2014, where repeatedly because it exploits fundamental DRAM circuit behavior that accessing data in a DRAM row can cause bit ips in nearby cannot be easily changed. This means that RowHammer is rows. The RowHammer vulnerability has since garnered sig- a potential threat across all DRAM generations and designs. nicant interest in both computer architecture and computer Kim et al. [62] show that RowHammer appears to be an eect security research communities because it stems from physi- of continued DRAM technology scaling [62, 88, 90, 91], which cal circuit-level interference eects that worsen with continued means that as manufacturers increase DRAM storage density, DRAM density scaling. As DRAM manufacturers primarily their chips are potentially more susceptible to RowHammer. depend on density scaling to increase DRAM capacity, future This increase in RowHammer vulnerability is often quantied DRAM chips will likely be more vulnerable to RowHammer than for a given DRAM chip by measuring the number of times a those of the past. Many RowHammer mitigation mechanisms single row must be activated (i.e., single-sided RowHammer) have been proposed by both industry and academia, but it is to induce the rst bit ip. Recently, Yang et al. [132] have unclear whether these mechanisms will remain viable solutions corroborated this hypothesis, identifying a precise circuit- for future devices, as their overheads increase with DRAM’s level charge leakage mechanism that may be responsible for vulnerability to RowHammer. RowHammer. This leakage mechanism aects nearby circuit In order to shed more light on how RowHammer aects mod- components, which implies that as manufacturers continue ern and future devices at the circuit-level, we rst present an to employ aggressive technology scaling for generational experimental characterization of RowHammer on 1580 DRAM storage density improvements [42, 53, 85, 125], circuit com- chips (408× DDR3, 652× DDR4, and 520× LPDDR4) from 300 ponents that are more tightly packed will likely increase a DRAM modules (60× DDR3, 110× DDR4, and 130× LPDDR4) chip’s vulnerability to RowHammer. with RowHammer protection mechanisms disabled, spanning To mitigate the impact of the RowHammer problem, numer- multiple dierent technology nodes from across each of the three ous works propose mitigation mechanisms that seek to pre- major DRAM manufacturers. Our studies denitively show that vent RowHammer bit ips from aecting the system. These newer DRAM chips are more vulnerable to RowHammer: as include mechanisms to make RowHammer conditions impos- device feature size reduces, the number of activations needed sible or very dicult to attain (e.g., increasing the default to induce a RowHammer bit ip also reduces, to as few as 9.6k DRAM refresh rate by more than 7x [62], or probabilistically (4.8k to two rows each) in the most vulnerable chip we tested. activating adjacent rows with a carefully selected probabi- We evaluate ve state-of-the-art RowHammer mitigation lity [62]) and mechanisms that explicitly detect RowHam- mechanisms using cycle-accurate simulation in the context of mer conditions and intervene (e.g., access counter-based ap- real data taken from our chips to study how the mitigation proaches [57, 62, 76, 112, 113]). However, all of these solu- mechanisms scale with chip vulnerability. We nd that existing tions [2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 15, 24, 25, 27, 30, 33, 38, 41, 44, 57, mechanisms either are not scalable or suer from prohibitively 61,62,66,76,77,78,115,122,126,127,128,133] merely treat the large performance overheads in projected future devices given symptoms of a RowHammer attack (i.e., prevent RowHammer our observed trends of RowHammer vulnerability. Thus, it is conditions) without solving the core circuit vulnerability. critical to research more eective solutions to RowHammer. To better understand the problem in order to pursue more comprehensive solutions, prior works study the RowHam- 1. Introduction mer failure mechanism both experimentally [62,95,96] and DRAM is the dominant main memory technology of nearly in simulation [132]. Unfortunately, there has been no work all modern computing systems due to its superior cost-per- since the original RowHammer paper [62] that provides a capacity. As such, DRAM critically aects overall system rigorous characterization-based study to demonstrate how performance and reliability. Continuing to increase DRAM chips’ vulnerabilities to RowHammer (i.e., the minimum num- capacity requires increasing the density of DRAM cells by ber of activations required to induce the rst RowHammer arXiv:2005.13121v2 [cs.AR] 29 May 2020 reducing (i.e., scaling) the technology node size (e.g., feature bit ip) scale across dierent DRAM technology generations. size) of DRAM, but this scaling negatively impacts DRAM While many works [5, 63, 89, 90, 91] speculate that modern reliability. In particular, RowHammer [62] is an important chips are more vulnerable, there is no rigorous experimental circuit-level interference phenomenon, closely related to tech- study that demonstrates exactly how the minimum activa- nology scaling, where repeatedly activating a DRAM row tion count to induce the rst RowHammer bit ip and other disturbs the values in adjacent rows. RowHammer can result RowHammer characteristics behave in modern DRAM chips. in system-visible bit ips in DRAM regions that are physi- Such an experimental study would enable us to predict future cally nearby rapidly accessed (i.e., hammered) DRAM rows. chips’ vulnerability to RowHammer and estimate whether RowHammer empowers an attacker who has access to DRAM existing RowHammer mitigation mechanisms can eectively address X with the ability to modify data in a dierent lo- prevent RowHammer bit ips in modern and future chips. cation Y such that X and Y are physically, but not neces- Our goal in this work is to experimentally demonstrate sarily logically, co-located. In particular, X and Y must be how vulnerable modern DRAM chips are to RowHammer at located in dierent DRAM rows that are in close proximity the circuit-level and to study how this vulnerability will scale to one another. Because DRAM is widely used throughout going forward. To this end, we provide a rigorous experimen- modern computing systems, many systems are potentially tal characterization of 1580 DRAM chips (408× DDR3, 652× vulnerable to RowHammer attacks, as shown by recent works DDR4, and 520× LPDDR4) from 300 modern DRAM modules (e.g., [21, 26, 34, 35, 50, 69, 81, 89, 99, 101, 107, 118, 121, 122, 129]). (60× DDR3, 110× DDR4, and 130× LPDDR4) from across all 1 three major DRAM manufacturers, spanning across multiple RowHammer in the future. We discuss directions for future dierent technology node generations for each manufacturer. research in this area in Section 6.3.1. To study the RowHammer vulnerability at the circuit level in- We make the following contributions in this work: stead of at the system level, we disable all accessible RowHam- • We provide the rst rigorous RowHammer failure charac- mer mitigation mechanisms.1 We observe that the worst-case terization study of a broad range of real modern DRAM circuit-level RowHammer conditions for a victim row are chips across dierent DRAM types, technology node gener- when we repeatedly access both physically-adjacent aggres- ations, and manufacturers. We experimentally study 1580 sor rows as rapidly as possible (i.e., double-sided RowHam- DRAM chips (408× DDR3, 652× DDR4, and 520× LPDDR4) mer). To account for double-sided RowHammer in our study, from 300 DRAM modules (60× DDR3, 110× DDR4, and we dene Hammer Count (HC) as the number of times each 130× LPDDR4) and present our RowHammer characteriza- physically-adjacent row is activated and HCrst as the mini- tion results for both aggregate RowHammer failure rates mum HC required to cause the rst RowHammer bit ip in and the behavior of individual cells while sweeping the the DRAM chip. For each DRAM type (i.e., DDR3, DDR4, hammer count (HC) and stored data pattern. LPDDR4), we have chips from at least two dierent tech- • Via our rigorous characterization studies, we denitively nology nodes, and for each of the LPDDR4 chips, we know demonstrate that the RowHammer vulnerability signi- the exact process technology node: 1x or 1y. This enables cantly worsens (i.e., the number of hammers required to us to study and demonstrate the eects of RowHammer on induce a RowHammer bit ip, HCrst, greatly reduces) in two distinct independent variables: DRAM type and DRAM newer DRAM chips (e.g., HCrst reduces from 69.2k to 22.4k technology node. in DDR3, 17.5k to 10k in DDR4, and 16.8k to 4.8k in LPDDR4 Our experiments study the eects of manipulating two key chips across multiple technology node generations). testing parameters at a xed ambient temperature on both • We demonstrate, based on our rigorous evaluation of ve aggregate and individual DRAM cell failure characteristics: state-of-the-art RowHammer mitigation mechanisms, that (1) hammer count (HC), and (2) data pattern written to DRAM. even though existing RowHammer mitigation mechanisms Our experimental results denitively show that newer are reasonably eective at mitigating RowHammer in to- DRAM chips manufactured with smaller technology nodes day’s DRAM chips (e.g., 8% average performance loss on are increasingly vulnerable to RowHammer bit ips. For ex- our workloads when HCrst is 4.8k), they will cause sig- nicant overhead in future DRAM chips with even lower ample, we nd that HCrst across all chips of a given DRAM type reduces greatly from older chips to newer chips (e.g., HCrst values (e.g., 80% average performance loss with the 69.2k to 22.4k in DDR3, 17.5k to 10k in DDR4, and 16.8k to most scalable mechanism when HCrst is 128).
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