Considerations for Designing an Embedded IA System with DDR3 ECC SO-DIMMS
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2GB DDR3 SDRAM 72Bit SO-DIMM
Apacer Memory Product Specification 2GB DDR3 SDRAM 72bit SO-DIMM Speed Max CAS Component Number of Part Number Bandwidth Density Organization Grade Frequency Latency Composition Rank 0C 78.A2GCB.AF10C 8.5GB/sec 1066Mbps 533MHz CL7 2GB 256Mx72 256Mx8 * 9 1 Specifications z Support ECC error detection and correction z On DIMM Thermal Sensor: YES z Density:2GB z Organization – 256 word x 72 bits, 1rank z Mounting 9 pieces of 2G bits DDR3 SDRAM sealed FBGA z Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) --- PCB height: 30.0mm --- Lead pitch: 0.6mm (pin) --- Lead-free (RoHS compliant) z Power supply: VDD = 1.5V + 0.075V z Eight internal banks for concurrent operation ( components) z Interface: SSTL_15 z Burst lengths (BL): 8 and 4 with Burst Chop (BC) z /CAS Latency (CL): 6,7,8,9 z /CAS Write latency (CWL): 5,6,7 z Precharge: Auto precharge option for each burst access z Refresh: Auto-refresh, self-refresh z Refresh cycles --- Average refresh period 7.8㎲ at 0℃ < TC < +85℃ 3.9㎲ at +85℃ < TC < +95℃ z Operating case temperature range --- TC = 0℃ to +95℃ z Serial presence detect (SPD) z VDDSPD = 3.0V to 3.6V Apacer Memory Product Specification Features z Double-data-rate architecture; two data transfers per clock cycle. z The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture. z Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver. z DQS is edge-aligned with data for READs; center aligned with data for WRITEs. -
Different Types of RAM RAM RAM Stands for Random Access Memory. It Is Place Where Computer Stores Its Operating System. Applicat
Different types of RAM RAM RAM stands for Random Access Memory. It is place where computer stores its Operating System. Application Program and current data. when you refer to computer memory they mostly it mean RAM. The two main forms of modern RAM are Static RAM (SRAM) and Dynamic RAM (DRAM). DRAM memories (Dynamic Random Access Module), which are inexpensive . They are used essentially for the computer's main memory SRAM memories(Static Random Access Module), which are fast and costly. SRAM memories are used in particular for the processer's cache memory. Early memories existed in the form of chips called DIP (Dual Inline Package). Nowaday's memories generally exist in the form of modules, which are cards that can be plugged into connectors for this purpose. They are generally three types of RAM module they are 1. DIP 2. SIMM 3. DIMM 4. SDRAM 1. DIP(Dual In Line Package) Older computer systems used DIP memory directely, either soldering it to the motherboard or placing it in sockets that had been soldered to the motherboard. Most memory chips are packaged into small plastic or ceramic packages called dual inline packages or DIPs . A DIP is a rectangular package with rows of pins running along its two longer edges. These are the small black boxes you see on SIMMs, DIMMs or other larger packaging styles. However , this arrangment caused many problems. Chips inserted into sockets suffered reliability problems as the chips would (over time) tend to work their way out of the sockets. 2. SIMM A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s . -
Product Guide SAMSUNG ELECTRONICS RESERVES the RIGHT to CHANGE PRODUCTS, INFORMATION and SPECIFICATIONS WITHOUT NOTICE
May. 2018 DDR4 SDRAM Memory Product Guide SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - May. 2018 Product Guide DDR4 SDRAM Memory 1. DDR4 SDRAM MEMORY ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 K 4 A X X X X X X X - X X X X SAMSUNG Memory Speed DRAM Temp & Power DRAM Type Package Type Density Revision Bit Organization Interface (VDD, VDDQ) # of Internal Banks 1. SAMSUNG Memory : K 8. Revision M: 1st Gen. A: 2nd Gen. 2. DRAM : 4 B: 3rd Gen. C: 4th Gen. D: 5th Gen. -
Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines, External
5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines June 2012 EMI_DG_005-4.1 EMI_DG_005-4.1 This chapter describes guidelines for implementing dual unbuffered DIMM (UDIMM) DDR2 and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT) setting of 75 Ω versus an ODT setting of 150 Ω f For detailed information about a single-DIMM DDR2 SDRAM interface, refer to the DDR2 and DDR3 SDRAM Board Design Guidelines chapter. DDR2 SDRAM This section describes guidelines for implementing a dual slot unbuffered DDR2 SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 5–1 shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface configuration using the ODT feature of the DDR2 SDRAM components. Figure 5–1. Dual-DIMM DDR2 SDRAM Interface Configuration (1) VTT Ω RT = 54 DDR2 SDRAM DIMMs (Receiver) Board Trace FPGA Slot 1 Slot 2 (Driver) Board Trace Board Trace Note to Figure 5–1: (1) The parallel termination resistor RT = 54 Ω to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination (OCT). © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. -
DDR SDRAM SO-DIMM MODULE, 2.5V 128Mbyte - 16MX64 AVK6416U35C5266K0-AP
DDR SDRAM SO-DIMM MODULE, 2.5V 128MByte - 16MX64 AVK6416U35C5266K0-AP FEATURES JEDEC Standard DDR 266MHz PC2100 Version 1.0, Lead Free, RoHS compliant Clock frequency: 133MHz with CAS latency 2.5 256 byte serial EEPROM Data input and output masking Programmable burst length: 2, 4, 8 Programmable burst type: sequential and interleave Programmable CAS latency: 2.5 Auto refresh and self refresh capability Gold card edge fingers 8K refresh per 64ms Low active and standby current consumption SSTL-2 compatible inputs and outputs Decoupling capacitors at each memory device Double-sided module 30.75mm (1.25 inch) height DESCRIPTION The AVK6416U35C5266K0-AP is an Unbuffered DDR SDRAM SODIMM memory module. This module is JEDEC- standard 200-pin, small-outline, dual in-line memory module. A 256 byte serial EEPROM on board can be used to store module information such as timing, configuration, density, etc. The AVK6416U35C5266K0-AP memory module is 128MByte and organized as a 16MX64 array using (8) 8MX16 DDR SDRAMs in lead free TSSOP II packages. All memory modules are fabricated using the latest technology design, six-layer printed circuit board substrate construction with low ESR decoupling capacitors on-board for high reliability and low noise. PHYSICAL DIMENSIONS 67.60 (2.66) 3.50 (0.14) SPD 128Mbit 128Mbit 128Mbit 128Mbit ) 5 8MbX16 8MbX16 8MbX16 8MbX16 2 . 1 ( DDR DDR DDR DDR 5 7 SDRAM SDRAM SDRAM SDRAM . 1 ) 3 7 8 7 . 0 ( 0 2 FRONT SIDE 1.00 (0.04) Pin 1 Pin 199 NOTES: 1- All dimensions are in milimeters (inches) 2- All blue ICs are on the front, and all red ICs are on the back side of the module. -
DDR2 SDRAM FBDIMM (DR, FB, X72) Features DDR2 SDRAM FBDIMM MT18HTF12872FD – 1GB MT18HTF25672FD – 2GB
Preliminary‡ 240-Pin 1GB, 2GB DDR2 SDRAM FBDIMM (DR, FB, x72) Features DDR2 SDRAM FBDIMM MT18HTF12872FD – 1GB MT18HTF25672FD – 2GB For the latest data sheet, refer to Micron’s Web site: www.micron.com Features Figure 1: 240-Pin FBDIMM (MO-256 R/C B) • 240-pin DDR2 fully buffered, dual in-line memory module (FBDIMM) with ECC to detect and report PCB height: 30.35mm (1.19in) channel errors to the host memory controller • Fast data transfer rates: PC2-4200 and PC2-5300 using 533 MT/s and 667 MT/s DDR2 SDRAM components • 3.2 Gb/s and 4.0 Gb/s link transfer rates • High-speed, differential, point-to-point link between host memory controller and the AMB using Options Marking serial, dual-simplex bit lanes – 10-pair southbound (data path to FBDIMM) •Package – 240-pin FBDIMM (lead-free) Y – 14-pair northbound (data path from FBDIMM) 1 • Fault tolerant; can work around a bad bit lane in •Frequency/CL each direction – 3.75ns @ CL = 5 (DDR2-667) -667 • High-density scaling with up to 8 dual-rank modules – 3.75ns @ CL = 4 (DDR2-533) -53E (288 DDR2 SDRAM devices) per channel •PCB height • SMBus interface to AMB for configuration register – 30.35mm (1.19in) access Notes: 1. CL = CAS (READ) latency. • In-band and out-of-band command access • Deterministic protocol – Enables memory controller to optimize DRAM accesses for maximum performance – Delivers precise control and repeatable memory behavior •Automatic DDR2 SDRAM bus and channel calibration • Transmitter de-emphasis to reduce ISI • MBIST and IBIST test functions • Transparent mode for DDR2 SDRAM test support •VDD = VDDQ = +1.8V for DDR2 SDRAM •VREF = 0 .9V SDRAM C/A termination •VCC = 1.5V for advanced memory buffer (AMB) •VDDSPD = +1.7V to +3.6V for SPD EEPROM • Serial presence-detect (SPD) with EEPROM • Gold edge contacts •Dual rank • Supports 95°C operation with 2X refresh (tREFI = 7.8µs at or below 85°C; tREFI = 3.9µs above 85°C) PDF: 09005aef81a2f20c/Source: 09005aef81a2f25b Micron Technology, Inc., reserves the right to change products or specifications without notice. -
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices.Pdf
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices © November 2008 AN-436-4.0 Introduction DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that include lower power consumption, higher data bandwidth, enhanced signal quality with multiple on-die termination (ODT) selection and output driver impedance control. DDR3 SDRAM brings higher memory performance to a broad range of applications, such as PCs, embedded processor systems, image processing, storage, communications, and networking. Although DDR2 SDRAM is currently the more popular SDRAM, to save system power and increase system performance you should consider using DDR3 SDRAM. DDR3 SDRAM offers lower power by using 1.5 V for the supply and I/O voltage compared to the 1.8-V supply and I/O voltage used by DDR2 SDRAM. DDR3 SDRAM also has better maximum throughput compared to DDR2 SDRAM by increasing the data rate per pin and the number of banks (8 banks are standard). 1 The Altera® ALTMEMPHY megafunction and DDR3 SDRAM high-performance controller only support local interfaces running at half the rate of the memory interface. Altera Stratix® III and Stratix IV devices support DDR3 SDRAM interfaces with dedicated DQS, write-, and read-leveling circuitry. Table 1 displays the maximum clock frequency for DDR3 SDRAM in Stratix III devices. Table 1. DDR3 SDRAM Maximum Clock Frequency Supported in Stratix III Devices (Note 1), (2) Speed Grade fMAX (MHz) –2 533 (3) –3 and I3 400 –4, 4L, and I4L at 1.1 V 333 (4), (5) –4, 4L, and I4L at 0.9 V Not supported Notes to Table 1: (1) Numbers are preliminary until characterization is final. -
Intel® NUC Products NUC7CJY/NUC7PJY Technical Product Specification
Intel® NUC Products NUC7CJY/NUC7PJY Technical Product Specification Regulatory Models: NUC7JY (Kit/Mini PC) NUC7JYB (Board) February 2018 Order Number: J96982-002 Intel NUC Products NUC7CJY/NUC7PJY Technical Product Specification The Intel NUC Products NUC7CJY/NUC7PJY may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in the Intel NUC Products NUC7CJY/NUC7PJY Specification Update. ii Revision History Revision Revision History Date 001 First release of Intel NUC Products NUC7CJY/NUC7PJY Technical Product January 2018 Specification 002 Spec Change February 2018 Disclaimer This product specification applies to only the standard Intel® NUC Boards, Kits and Mini PCs with BIOS identifier JYGLKCPX.86A. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. All Intel® NUC Boards are evaluated as Information Technology Equipment (I.T.E.) for use in personal computers (PC) for installation in homes, offices, schools, computer rooms, and similar locations. -
ECE 571 – Advanced Microprocessor-Based Design Lecture 16
ECE 571 { Advanced Microprocessor-Based Design Lecture 16 Vince Weaver http://web.eece.maine.edu/~vweaver [email protected] 4 April 2017 Announcements • HW8 was assigned, read about Newer Intel chips for Thursday • Slow getting back to you about project ideas • Sorry about voice, mild cold 1 How to save Energy in TLB? • Turn off Virtual Memory completely (aside about ARM1176 manual and caches). Can you run Linux without VM? ucLinux • TLB is similar to cache, can make similar optimizations (drowsy, sizing, etc) • Assume in current page (i.e. 1-entry 0-level TLB) (Kadayif, Sivasubramaniam, Kandemir, Kandiraju, Chen. TODAES 2005). 2 (Kadayif,Sivasubramaniam, Kandemir, Kandiraju, Chen. Micro 2002) • Use virtual cache (Ekman and Stenstr¨om,ISLPED 2002) • Switch virtual to physical cache on fly (hybrid) (Basu, Hill, Swift. ISCA 2012) • Dynamically resize the TLB (Delaluz, Kandemir, Sivasubramaniam, Irwin, Vijaykrishnan. ICCD 2013) • Try to keep as much in one page as possible via compiler. (Jeyapaul, Marathe, Shrivastava, VLSI'09) 3 (Lee, Ballapuram. ISLPED'03) 4 DRAM • Single transistor/capacitor pair. (can improve behavior with more transistors, but then less dense) • Compare to SRAM that has 6 transistors (or 4 plus hard-to make resistors with high static power) • In 90nm process, 30fF capacitor, leakage in transistor 1fA. Can hold charge from milliseconds to seconds. • DRAMs gradually lose charge, need to be refreshed. Need to be conservative. Refresh every 32 or 64ms 5 • DRAM read is destructive, always have to write back 6 Diagram DRAM Column Decoder Sense Amps word line bit line Memory Array Row Decoder SRAM WL WL !BL BL !BL BL 7 Low Level • Trench Capacitors • Stacked Capacitors 8 SIMMs/DIMMS • How many chips on DIMM? 8? 9? 9 usually means ECC/parity • Chips x1 x4 x8 bits, how many get output at a time. -
High Bandwidth Memory for Graphics Applications Contents
High Bandwidth Memory for Graphics Applications Contents • Differences in Requirements: System Memory vs. Graphics Memory • Timeline of Graphics Memory Standards • GDDR2 • GDDR3 • GDDR4 • GDDR5 SGRAM • Problems with GDDR • Solution ‐ Introduction to HBM • Performance comparisons with GDDR5 • Benchmarks • Hybrid Memory Cube Differences in Requirements System Memory Graphics Memory • Optimized for low latency • Optimized for high bandwidth • Short burst vector loads • Long burst vector loads • Equal read/write latency ratio • Low read/write latency ratio • Very general solutions and designs • Designs can be very haphazard Brief History of Graphics Memory Types • Ancient History: VRAM, WRAM, MDRAM, SGRAM • Bridge to modern times: GDDR2 • The first modern standard: GDDR4 • Rapidly outclassed: GDDR4 • Current state: GDDR5 GDDR2 • First implemented with Nvidia GeForce FX 5800 (2003) • Midway point between DDR and ‘true’ DDR2 • Stepping stone towards DDR‐based graphics memory • Second‐generation GDDR2 based on DDR2 GDDR3 • Designed by ATI Technologies , first used by Nvidia GeForce FX 5700 (2004) • Based off of the same technological base as DDR2 • Lower heat and power consumption • Uses internal terminators and a 32‐bit bus GDDR4 • Based on DDR3, designed by Samsung from 2005‐2007 • Introduced Data Bus Inversion (DBI) • Doubled prefetch size to 8n • Used on ATI Radeon 2xxx and 3xxx, never became commercially viable GDDR5 SGRAM • Based on DDR3 SDRAM memory • Inherits benefits of GDDR4 • First used in AMD Radeon HD 4870 video cards (2008) • Current -
DDR3 SODIMM Product Datasheet
DDR3 SODIMM Product Datasheet 廣 穎 電 通 股 份 有 限 公 司 Silicon Power Computer & Communications Inc. TEL: 886-2 8797-8833 FAX: 886-2 8751-6595 台北市114內湖區洲子街106號7樓 7F, No.106, ZHO-Z ST. NEIHU DIST, 114, TAIPEI, TAIWAN, R.O.C This document is a general product description and is subject to change without notice DDR3 SODIMM Product Datasheet Index Index...................................................................................................................................................................... 2 Revision History ................................................................................................................................................ 3 Description .......................................................................................................................................................... 4 Features ............................................................................................................................................................... 5 Pin Assignments................................................................................................................................................ 7 Pin Description................................................................................................................................................... 8 Environmental Requirements......................................................................................................................... 9 Absolute Maximum DC Ratings.................................................................................................................... -
512MB (X64, SR) 204-Pin DDR3 SODIMM Features DDR3 SDRAM SODIMM MT4JSF6464H – 512MB
512MB (x64, SR) 204-Pin DDR3 SODIMM Features DDR3 SDRAM SODIMM MT4JSF6464H – 512MB Features Figure 1: 204-Pin SODIMM (MO-268 R/C C) • DDR3 functionality and operations supported as PCB height: 30.0mm (1.18in) defined in the component data sheet • 204-pin, small-outline dual in-line memory module (SODIMM) • Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400 • 512MB (64 Meg x 64) • VDD = 1.5V ±0.075V • VDDSPD = 3.0–3.6V • Nominal and dynamic on-die termination (ODT) for Options Marking 1 data, strobe, and mask signals • Operating temperature – Commercial (0°C ≤ T ≤ +70°C) None • Single rank A – Industrial (–40°C ≤ T ≤ +85°C) I • On-board I2C temperature sensor with integrated A Package serial presence-detect (SPD) EEPROM • – 204-pin DIMM (lead-free) Y 8 internal device banks • • Frequency/CAS latency • Fixed burst chop (BC) of 4 and burst length (BL) of 8 – 1.25ns @ CL = 11 (DDR3-1600) -1G6 via the mode register set (MRS) – 1.5ns @ CL = 9 (DDR3-1333) -1G4 • Selectable BC4 or BL8 on-the-fly (OTF) – 1.87ns @ CL = 7 (DDR3-1066) -1G1 • Gold edge contacts Notes: 1. Contact Micron for industrial temperature • Lead-free module offerings. • Fly-by topology 2. Not recommended for new designs. • Terminated control, command, and address bus Table 1: Key Timing Parameters Speed Industry Data Rate (MT/s) tRCD tRP tRC Grade Nomenclature CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 (ns) (ns) (ns) -1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1G4 PC3-10600 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625 -1G0 PC3-8500 – – – 1066 – 800 667 15 15 52.5 -80B PC3-6400 – – – – – 800 667 15 15 52.5 PDF: 09005aef82b2f090 Micron Technology, Inc.