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Assistant Professor, Department of ECE, SNS College of Technology, SNS Kalvi Nagar, Vazhiyampalyam Pirivu, Coimbatore - 035 ------G

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Assistant Professor, Department of ECE, SNS College of Technology, SNS Kalvi Nagar, Vazhiyampalyam Pirivu, Coimbatore - 035 ------G Assistant Professor, Department of ECE, SNS College of Technology, SNS Kalvi Nagar, Vazhiyampalyam Pirivu, Coimbatore - 035 ----------------------------------------------------------------------------------------------------------------------------------------------------- G. NAVEEN BALAJI, B.E., M.E., (M.B.A.), (Ph.D.) Objective To work in a healthy, innovative and challenging environment extracting the best out of me, which is helpful to learn and grow at professional as well as personal level thereby directing my future happenings as an asset to the organization. Educational Qualification Pursuing 9.25 Doctor of Philosophy - Low cost testing of Scan – BIST VLSI Circuits Information and Communication Engineering Anna University, Chennai – 600025 2013 8.74 Master of Engineering – VLSI Design - First class with Distinction (Anna University – 17th Rank), Madha Engineering College, Kundrathur, Chennai – 600069 2011 81.08 Bachelor of Engineering – ECE - First class with Distinction Arasu Engineering College, Kumbakonam, Thanjavur – 622501 Projects Bachelor of Engineering - BTS Site Creation in CDMA Duration : 04 Months Venue : BSNL’s Rajiv Gandhi Memorial Telecom Training Center, Chennai Master of Engineering - Economical Scan-BIST VLSI Circuits based on reducing testing time by means of ADP Duration : 12 Months Venue : Madha Engineering College, Chennai Publications – International Journal 1. P. Pattunarajam, G. Naveen Balaji "Economical SCAN-BIST VLSI Circuits Based on Reducing Testing Time by means of ADP" International Journal of Science, Engineering and Technology Research, Vol. 2, Issue 5 (May 2013) pp: 1088 - 1094 ISSN: 2278 – 7798 2. G. Naveen Balaji, S. Vinoth Vijay "Arbitrary Density Pattern (ADP) Based Reduction of Testing Time in Scan-BIST VLSI Circuits" International Journal of Science, Engineering and Technology Research, Vol. 2, Issue 6 (June 2013) pp: 1237 - 1243 ISSN: 2278 – 7798 3. G. Naveen Balaji, D. Rajesh "Linear Assembly in ATPG: Applications in Fast SCAN – BIST VLSI Circuits" International Journal of Innovations in Engineering and Technology, Vol. 6, Issue 3 (Feb 2016) pp: 101-106 ISSN: 2319-1058 4. G. Naveen Balaji, S. Chenthur Pandian "Novel Automatic Test Pattern Generator (ATPG) for degenerated SCAN - BIST VLSI Circuits" International Research Journal of Engineering and Technology, Vol. 3, Issue 3 (Mar 2016) pp: 1087-1091 ISSN: 2395 -0056 5. G. Naveen Balaji, K. Ambhikavathi, S. Geethiga "Master–Slave Flip- Flops Using Transmission Gate By Accessing High Speed Design Values" International Journal of Emerging Trends in Science and Technology, Vol. 3, Issue 5 (May 2016) pp: 363-368 ISSN: 2348-9480 6. M. Srinivasaperumal, G. Naveen Balaji, M. Jagadesh "Heterogenous Node Recovery from crash in wireless Sensor actor networks" International Journal of Modern Trends in Engineering and Science, Vol. 3, Issue 6 (2016) pp: 116-120 ISSN: 2348-3121 7. G.Naveen balaji, N.V.Hari suriya, S.Anandvikash, B.Adithya, S.Arun kumar "Cost effective power supply based on transformer-less circuitry using bridge rectifier" International Journal of Engineering Research, Vol. 4, Issue 3 (May June 2016) pp: 70-74 ISSN: 2321-7758 8. G. Naveen Balaji, S. Chenthur Pandian, D. Rajesh "A survey on effective Automatic Test Pattern Generator for self-checking Scan - BIST VLSI circuits" International Research Journal of Engineering and Technology, Vol. 3, Issue 5 (May 2016) pp: 645-648 ISSN: 2395 -0056 9. G. Naveen Balaji, V.Aathira, K. Ambhikavathi, S. Geethiga, R. Havin "Combinational Circuits Using Transmission Gate Logic for Power Optimization" International Research Journal of Engineering and Technology, Vol. 3, Issue 5 (May 2016) pp: 649-654 ISSN: 2395 -0056 10. R. Arun Sekar, G. Naveen Balaji, A. Gautami, B. Sivasankari “High Efficient Carry Skip Adder in various Multiplier Structures” Advances in Natural and Applied Sciences (Annexure II), Vol. 10 Issue 14 (Special) (Oct 2016) pp: 193- 197 ISSN: 1995-0772 Papers presented International Conferences 1. “Transmission Gate based Digital Circuits by Re-Evaluating Extraordinary Speed Design Principles” on 25-27.05.2016, International Conference on Advanced Communication Control and Computing Technologies (ICACCCT’16), Syed Ammal Engineering College, Ramanathapuram. (ISBN: 978-1-4673-9544-1) 2. “Master–Slave Flip- Flops using Transmission Gate by accessing High Speed Design Values” on 28.05.2016, International Conference on Progressive Engineering & Technology (INCPET’16), Institute of Engineering Research, Salem, Tamilnadu. (CSN: INC-06-SLM-280416-01) 3. “High Efficient Carry Skip Adder in Various Multiplier Structures” on 28.08.2016, International Conference on Theory and Practical Relation in Engineering (ICTPRE’16), International Institute for Research and Development in Engineering and Management, Chennai, Tamilnadu.(ISBN: 978-1-5373-1357-3) 4. “Low power and high performance JK Flipflop using 45nm technology” on 18-19.10.2016, International Conference on Applied Science Engineering and Technology (ICASET’16), Swetha Institute ofTechnology and Science, Tirupati. (Volume: IFERP,ISBN: 978-8-1932-9660-8) National Conferences 1. “Feature Extraction for Ultrasound image based on CBIR system” on 23.03.2016, National Conference NCOVIP’10, Arasu Engineering College, Kumbakonam. 2. “Enterprising of BTS site in CDMA technology with scheme for intelligent hand-off algorithm” on 24.05.2011, National Conference ETEC 2011, Jayam Engineering College, Namakkal. 3. “BTS (Site Creation) in CDMA” on 06.04.2011, National Conference NCCSP’11, Arasu Engineering College, Kumbakonam. 4. “Economical Scan-BIST VLSI circuits based on reducing testing time by means of ADP” on 08.03.2013, National Conference RECCE’13, Srinivasan Engineering College, Perambalur. 5. “Economical Scan-BIST VLSI circuits based on reducing testing time by means of ADP” on 11.04.2013, National Conference RTEC 2013, St. Joseph College of Engineering, Sriperumbudur. 6. “Arbitrary Density Pattern (ADP) Based Reduction of Testing Time in Scan-BIST VLSI Circuits” on 19.04.2013, National Conference OPTEST 2013, Bannari Amman Institute of Technology, Sathyamanagalam Symposium 1. “Digital Signal Processing and its applications – Google Maps” on 18.09.2009, National level Technical Symposium Vibrantz’09, Paavai Engineering College, Namakkal. 2. “Robot control by haptic responses” on 19.03.2009, First place in paper presentation event MechZeal’09, Arasu Engineering College, Kumbakonam. Experience Post Held, S. No. Employer Period Nature of Job Sudharsan Engineering College, Sathiyamangalam, Assistant Professor 1 16.08.2013 To 30.04.2015 Pudukottai (Dt), Tamilnadu - 622501 Grade I SNS College of Technology, SNS Kalvi Nagar, Assistant Professor 2 22.06.2015 To Till Date Coimbatore - 641035 Grade I Post ME Co-Curricular S. No. Nature Title Organizer / Venue Duration 02.01.2014 ISTE sponsored Signals and Systems Indian Institute of Technology, 1 To Workshop (National Mission on Education, MHRD) Kharagpur, West Bengal 12.01.2014 02.12.2014 ISTE sponsored Control Systems Indian Institute of Technology, 2 To Workshop (National Mission on Education, MHRD) Kharagpur, West Bengal 12.12.2014 24.08.2014 National Level Design of Embedded Power Electronics 3 VIT University, Vellore To Workshop System for Home Automation 25.08.2014 Faculty 23.06.2015 SNS College of Technology, 4 Orientation Internal Quality Assurance Cell (IQAC) To Coimbatore Programme 25.06.2015 IEEE Sponsored Karpagam College of 5 Latex for Research Publications 06.02.2016 Workshop Engineering, Coimbatore National Level Hindusthan Institute of 6 VLSI Chip Design 22.07.2016 Workshop Technology, Coimbatore International Top Engineers @YWCA, 7 IC Engine Electronics 07.08.2016 Workshop Coimbatore International Research Proposals Writing, Execution SNS College of Technology, 8 10.08.2016 Seminar and Patenting Coimbatore Cognitive Radio and Wireless 01.09.2016 MHRD sponsored Indian Institute of Technology, 9 Communication - Theory, Practice and To GIAN Course Kanpur, Uttar Pradesh Security 10.09.2016 Events Handled Handled a session in the Seven days Faculty development programme on “EC6503 – Transmission Lines and Wave Guides” organized by Anna University, Chennai along with SNS College of Technology, Coimbatore during 23.05.2016 to 29.05.2016. Memberships 1. Indian Society for Technical Education - Life Member (LM 109016) 2. International Association of Engineers - Member (157852) 3. International Society for Research and Development - Member (M4150900424) 4. Institute of Research Engineers and Doctors - Associate Member (AM10100051919) 5. International Safety Quality Environment Management - Associate Member (15M27853) Added supports 1. District level IInd prize in Tamil Essay writing contest organized by ‘Tamizh Valarchi Thurai 2006 - 2007’, Villupuram. 2. In - Plant Training (IPT) in IPM Software solutions, Chennai (17 - 21 May 2010) 3. IPT in Integral Coach Factory, Chennai (24 - 31 May 2010) 4. IPT on ‘Embedded systems’ at Accel IT Academy, Trichy (7 - 9 June 2010) 5. Attended a workshop on ‘Embedded System’ at Arasu Engineering College, Kumbakonam (03.09.2010) 6. Attended a workshop on ‘Latest Trends in Electronics’ at Bluechip Technologies, Trichy (12.09.2010) 7. Participated in National level seminar on ‘Network Simulator’ held on 28.03.2011, Arasu Engineering College, Kumbakonam. Personal Information D.O.B : 09 April 1990 Gender : Male Father’s name : Gowthaman P Languages Known : Tamil, English, Hindi (R/W) and Telugu (Broken) Hobbies : Playing Chess and Photography Permanent Address : 60, Co- operative Nagar, Umamaheshwarapuram (Po) Thiruvidaimarudhur (Tk), Thanjavur (Dt) - 612103 .
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