Microprocessor (COM 9323)

Lecture 6: Memory Modes of Operation (cont’d)

Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt

March 2nd, 2016 1 Text Book/References*

Textbook: The Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 (Chapter 02)

*The presentation is based on the text book and their official presentations

2 Contents oHow its memory space is addressed? . Real mode of operation . of operation . Flat mode of operation

3 Real Mode Memory Addressing (Segmentation)

o Fixed segment size: 64K bytes in length o To address the first 1 Megabytes under MSDOS operation o Physical address= start address + offset Address o Start address=(Segment register address) 0 H

4 Contents oHow its memory space is addressed? . Real mode of operation . Protected mode of operation . Flat mode of operation

5 Protected Mode Addressing o Windows Mode o Allows access to data and programs located anywhere in the memory o Variable Segment size o Using the segment register to select a description from the global descriptor table. . In this example, the DS register accesses memory locations 00100000H–001000FFH as a data segment. 8 Bytes o The entry in the global descriptor table selects a segment in the memory system.

Selector

Descriptor describes the memory segment’s location, length, and access rights. 6 Selector Format

The highest privilege level is 00 and the lowest is 11. o If the requested privilege level matches or is higher in priority than the privilege level set by the access rights byte, access is granted. o For example, if the requested privilege level is 10 and the access rights byte sets the segment privilege level at 11, access is granted because 10 is higher in priority than privilege level 11 o If privilege levels are violated, the system normally indicates an application or privilege level violation 7 Format of a descriptor for the 80286 through the Core2.

oEach descriptor is 8 bytes in length .global and local descriptor tables are a maximum of 64K bytes in length o The base address of the descriptor indicates the starting location of the memory segment . (24 bit)16 Mega byte, 32 bit 4Gbyte o The segment limit contains the last offset address found in a segment . (16 bit) 1 to 64K, . (20 bit) 1 to 1M (G=0), 4k to 4G in steps of 4k (G=1) Limit x 4k= (Limit)FFF H

8 Descriptors Format: AV- Bit oThe AV bit, in the 80386 and above descriptor, is used by some operating systems to indicate that the segment is available ( AV=1) or not available (AV=0 )

9 Descriptors Format: D- Bit oThe D bit indicates how the 80386 through the Core2 instructions access register and memory data in the protected or real mode. oIf D=0, the instructions are 16-bit instructions, compatible with the 8086– 80286 microprocessors. This means that the instructions use 16-bit offset addresses and 16-bit register by default. This mode is often called the 16- bit instruction mode or DOS mode. oIf D=1, the instructions are 32-bit instructions. By default, the 32-bit instruction mode assumes that all offset addresses and all registers are 32 bits.

10 Protected Mode Applications

oOperating systems operate in a 16- or 32-bit environment. oDOS uses a 16-bit environment. oMost Windows applications use a 32-bit environment called WIN32. oMSDOS/PCDOS & Windows 3.1 operating systems require 16-bit instruction mode. oInstruction mode is accessible only in a protected mode system such as Windows Vista.

11 Descriptors Format: L- Bit oIn the 64-bit descriptor, the L bit (probably means large, but Intel calls it the 64-bit) selects 64-bit addresses in a Pentium 4 or Core2 with 64-bit extensions when L = 1 and 32-bit compatibility mode when L=0. oIn 64-bit protected operation, the code segment register is still used to select a section of code from the memory.

12 Descriptors Format: L- Bit (cont’d) oNotice that the 64-bit descriptor has no limit or base address. It only contains an access rights byte and the control bits. oIn the 64-bit mode, there is no segment or limit in the descriptor and the base address of the segment, although not placed in the descriptor, is 00 0000 0000H (1 Tbyte space). o This means that all code segments start at address zero for 64-bit operation. There are no limit checks for a 64-bit code segment

13 Program-Invisible Registers

oGlobal and local descriptor tables are found in the memory system. oTo access & specify the table addresses, 80286–Core2 contain program- invisible registers. . not directly addressed by software . although some of these registers are accessed by the system software oEach segment register contains a program-invisible portion used in the protected mode. . often called cache memory because cache is any memory that stores information

14 Program- Invisible Registers

15 Program-Invisible Registers

oWhen a new segment number is placed in a segment register, the microprocessor accesses a descriptor table and loads the descriptor into the program-invisible portion of the segment register. . held there and used to access the memory segment until the segment number is changed oThis allows the microprocessor to repeatedly access a memory segment without referring to the descriptor table. . hence the term cache

16 Program-Invisible Registers

oThe GDTR (global descriptor table register) and IDTR (interrupt descriptor table register) contain the base address of the descriptor table and its limit. . when protected mode operation desired, address of the global descriptor table and its limit are loaded into the GDTR oThe location of the local descriptor table is selected from the global descriptor table. . one of the global descriptors is set up to address the local descriptor table

17 Program-Invisible Registers

oTo access the local descriptor table, the LDTR (local descriptor table register) is loaded with a selector. . selector accesses global descriptor table, & loads local descriptor table address, limit, & access rights into the cache portion of the LDTR oThe TR (task register) holds a selector, which accesses a descriptor that defines a task. . a task is most often a procedure or application oAllows multitasking systems to switch tasks to another in a simple and orderly fashion.

18 oThe memory paging mechanism allows any physical memory location to be assigned to any linear address. oLinear address is defined as the address generated by a program. oPhysical address is the actual memory location accessed by a program. oWith memory paging, the linear address is invisibly translated to any physical address. oIn Windows, each application is allowed a 2G linear address space from location 00000000H–7FFFFFFFH even though there may not be enough memory or memory available at these addresses. oThrough paging to the hard disk drive and paging to the memory through the memory paging unit, any Windows application can be executed 19 Paging Registers oThe paging unit is controlled by the contents of the microprocessor’s control registers. oBeginning with Pentium, an additional control register labeled CR4 controls extensions to the basic architecture.

The control register structure of the microprocessor

20 Paging Registers oThe leftmost bit (PG) position of CR0 selects paging when placed at a logic 1 level. oIf the PG bit is cleared (0), the linear address generated by the program becomes the physical address used to access memory. o If the PG bit is set (1), the linear address is converted to a physical address through the paging mechanism. oThe paging mechanism functions in both the real and protected modes.

The control register structure of the microprocessor

21 Paging Registers oCR3 contains the page directory base or root address oThe page directory base address locates the directory for the page translation unit oNote that this address locates the page directory at any 4K boundary in the memory system because it is appended internally with 000H. o The page directory contains 1024 directory entries of 4 bytes each. oEach page directory entry addresses a page table that contains 1024 entries

The control register structure of the microprocessor

22 Memory Paging: linear address

oThe linear address, as generated by software, is broken into three sections that are used to access the page directory entry, page table entry, and memory page offset address.

oThe page directory contains 1024 directory entries of 4 bytes each. oEach page directory entry addresses a page table that contains 1024 entries

23 The linear address and its makeup for paging

When the program Format of a linear address accesses a location between 00000000H and 00000FFFH, the microprocessor physically addresses location 00100000H–00100FFFH.

Format of a page directory or page table entry

24 Memory Paging

oIntel has incorporated a special type of cache called TLB (translation look-aside buffer). . because repaging a 4K-byte section of memory requires access to the page directory and a page table, both located in memory oThe 80486 cache holds the 32 most recent page translation addresses. . if the same area of memory is accessed, the address is already present in the TLB . This speeds program execution oPentium contains separate TLBs for each of their instruction and data caches.

25 The Page Directory and Page Table

oOnly one page directory in the system. oThe page directory contains 1024 doubleword addresses that locate up to 1024 page tables. oPage directory and each page table are 4K bytes in length.

26 The paging mechanism (80386-)

The page directory, a few page tables, and some memory pages.

27 The Page Directory and Page Table

oDOS and EMM386.EXE use page tables to redefine memory between locations C8000H–EFFFFH as upper memory blocks. . done by repaging to backfill conventional memory system to allow DOS access to additional memory oEach entry in the page directory corresponds to 4M bytes of physical memory. oEach entry in the page table repages 4K bytes of physical memory. oWindows also repages the memory system.

28 The page directory, page table 0, and two memory pages.

Note how the address of page 000C8000–000C9000 has been moved to 00110000–00110FFF.

29 Contents oHow its memory space is addressed? . Real mode of operation . Protected mode of operation . Flat mode of operation

30 Flat Mode Memory

oA flat mode memory system is one in which there is no segmentation. . does not use a segment register to address a location in the memory oFirst byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH. . address is 40-bits oThe segment register still selects the privilege level of the software

31 Flat Mode Memory

oReal mode system is not available if the processor operates in the 64-bit mode. oProtection and paging are allowed in the 64-bit mode. oThe CS register is still used in the protected mode operation in the 64-bit mode. oMost programs today are operated in the IA32 compatible mode. . current software operates properly, but this will change in a few years as memory becomes larger and most people have 64-bit computers

32 The 64-bit flat mode memory model

33 Chapter Summary o The programming model of the 8086 through 80286 contains 8- and 16-bit registers. o The programming model of the 80386 and above contains 8-, 16-, and 32-bit extended registers as well as two additional 16-bit segment registers: FS and GS.

34 Summary (cont’d) o 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL. o 16-bit registers are AX, BX, CX, DX, SP, BP, DI, and SI. o The segment registers are CS, DS, ES, SS, FS, and GS. o 32-bit extended registers are EAX, EBX, ECX, EDX, ESP, EBP, EDI, and ESI.

35 Summary (cont’d) o The 64-bit registers in a Pentium 4 with 64-bit extensions are RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI, and R8 through R15. o In addition, the microprocessor contains an instruction pointer (IP/EIP/RIP) and flag register (FLAGS, EFLAGS, or RFLAGS). o All real mode memory addresses are a combination of a segment address plus an offset address.

36 Summary (cont’d) o The starting location of a segment is defined by the 16-bit number in the segment register that is appended with a hexadecimal zero at its rightmost end. o The offset address is a 16-bit number added to the 20-bit seg-ment address to form the real mode memory address. o All instructions (code) are accessed by the combination of CS (segment ad-dress) plus IP or EIP (offset address).

37 Summary (cont’d) o Data are normally referenced through a combination of the DS (data segment) and either an offset address or the contents of a register that contains the offset address. o The 8086-Core2 use BX, DI, and SI as default offset registers for data if 16-bit registers are selected. o The 80386 and above can use the 32-bit registers EAX, EBX, ECX, EDX, EDI, and ESI as default offset registers for data.

38 Summary (cont’d) o Protected mode operation allows memory above the first 1M byte to be accessed by the 80286 through the Core2 microprocessors. o This extended memory system (XMS) is accessed via a segment address plus an offset address, just as in the real mode. o In the protected mode, the segment starting address is stored in a descriptor that is selected by the segment register. 39 Summary (cont’d) o The 80286 microprocessor allows a memory segment to start at any of its 16M bytes of memory using a 24-bit base address. o The 80386 and above allow a memory segment to begin at any of its 4G bytes of memory using a 32-bit base address. o This allows an 80286 memory segment limit of 64K bytes, and an 80386 and above mem-ory segment limit of either 1M bytes

40 Summary (cont’d) o The segment register contains three fields of information in the protected mode. o The leftmost 13 bits of the segment register address one of 8192 descriptors from a descriptor table. o The program-invisible registers are used by the 80286 and above to access the descriptor tables.

41 Summary (cont’d) o Each segment register contains a cache portion that is used in protected mode to hold the base address, limit, and access rights acquired from a descriptor. o The cache allows the microprocessor to access the memory segment without again referring to the descriptor table until the segment register's contents are changed.

42 Summary (cont’d) o A memory page is 4K bytes in length. The linear address, as generated by a program, can be mapped to any physical address through the paging mechanism found within the 80386 through the Pentium 4. o Memory paging is accomplished through control registers CR0 and CR3. o The PG bit of CR0 enables paging, and the contents of CR3 addresses the page directory.

43 Summary (cont’d) o The page directory contains up to 1024 page table addresses that are used to access paging tables. o The page table contains 1024 entries that locate the physical address of a 4K-byte memory page. o The TLB (translation look-aside buffer) caches the 32 most recent page table translations.

44 Summary (cont’d) o The flat mode memory contains 1T byte of memory using a 40-bit address. o In the future, Intel plans to increase the address width to 52 bits to access 4P bytes of memory. o The flat mode is only available in the Pentium 4 and Core2 that have their 64-bit extensions enabled.

45 Objectives 1. Describe the function and purpose of each program-visible register in the 8086–Core2 microprocessors, including the 64-bit extensions. 2. Detail the flag register and the purpose of each flag bit. 3. Describe how memory is accessed using real mode memory-addressing techniques. 4. Describe how memory is accessed using protected mode memory- addressing techniques. 5. Describe how memory is accessed using the 64-bit flat memory model. 6. Describe the program-invisible registers found within the 80286 through Core2 microprocessors.

7. Detail the operation of the memory-paging mechanism. 46 Questions

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