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Probabilistic Boolean Logic, Arithmetic and Architectures

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Probabilistic Boolean Logic, Arithmetic and Architectures PROBABILISTIC BOOLEAN LOGIC, ARITHMETIC AND ARCHITECTURES A Thesis Presented to The Academic Faculty by Lakshmi Narasimhan Barath Chakrapani In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Computer Science, College of Computing Georgia Institute of Technology December 2008 PROBABILISTIC BOOLEAN LOGIC, ARITHMETIC AND ARCHITECTURES Approved by: Professor Krishna V. Palem, Advisor Professor Trevor Mudge School of Computer Science, College Department of Electrical Engineering of Computing and Computer Science Georgia Institute of Technology University of Michigan, Ann Arbor Professor Sung Kyu Lim Professor Sudhakar Yalamanchili School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Professor Gabriel H. Loh Date Approved: 24 March 2008 College of Computing Georgia Institute of Technology To my parents The source of my existence, inspiration and strength. iii ACKNOWLEDGEMENTS आचायातर् ्पादमादे पादं िशंयः ःवमेधया। पादं सॄचारयः पादं कालबमेणच॥ “One fourth (of knowledge) from the teacher, one fourth from self study, one fourth from fellow students and one fourth in due time” 1 Many people have played a profound role in the successful completion of this disser- tation and I first apologize to those whose help I might have failed to acknowledge. I express my sincere gratitude for everything you have done for me. I express my gratitude to Professor Krisha V. Palem, for his energy, support and guidance throughout the course of my graduate studies. Several key results per- taining to the semantic model and the properties of probabilistic Boolean logic were due to his brilliant insights. In this sense, the results pertaining to the semantic model and the properties of probabilistic Boolean logic, were developed in a truly collaborative manner. I express my sincere gratitude to Professor Zvi Kedem for his enthusiasm and insightful feedback on the logic aspects of this work. I thank my dissertation committee member, Professor Sudhakar Yalamanchili for his patience, support and guidance during my stay at Georgia Tech. My dissertation committee member, Professor Gabriel Loh provided me invaluable feedback and advice on my research and writing. Given their standing in the microelectronics community and their busy schedules, I consider myself very fortunate to have had the guidance and encouragement of Professor James Meindl and Dr. Ralph Cavin. I thank my disser- tation committee members, Professor Trevor Mudge and Professor Sung Kyu Lim for 1Ancient subhashita, usually attributed to Haradatta’s commentary on Apastamba Dharmasutra iv their encouragement and suggestions. I wish to thank Professor Vincent Mooney for his interest and encouragement. I wish to express my sincere and profound gratitude to Dr. Ranjani Parthasarathi for stimulating my interest in computer science and encouraging me to pursue graduate studies. I would like to acknowledge the funding support from Defense Advanced Research Projects Agency (DARPA). Dr. Robert Graybill supported our research, right from its infancy, and enabled us to pursue it through a DARPA seedling in 2002. I wish to thank Dr. Shekhar Borkar, Dr. Vivek De and Dr. Keith Bowman for their enthusiastic support and guidance and acknowledge Intel Corporation for the funding which supported in part, the research reported in this dissertation. I benefited greatly from the stimulating environment at the Georgia Institute of Technology, the California Institute of Technology and Rice University. I thank everyone who granted me an opportunity to work at these institutions. I thank my colleagues Dr. Pinar Korkmaz and Suresh Cheemalavagu for their friendship and collaboration. A large part of this dissertation is synergistic with and complements Pinar’s ideas and foundations. I thank Dr. Bilge Akgul, Jason George and Bo Marr for their friendship and collaboration on many joint papers. I wish to thank my friends Dr. Rodric Rabbah, Yogesh Chobe, Tushar Kumar and Dr. Bal- asubramanian Seshasayee for the many stimulating conversations and eclectic ideas. I thank my friends Romain Cledat, Jaswanth Sreeram and Rick Copeland for their friendship. I thank my friends Karthik Sankaranarayanan, Easwaran Raman, Mad- husudanan Seshadri and Niranjan Venkatraman for their friendship over the many years, their standard of academic excellence and their personal integrity. I wish to thank Kiruthika for her friendship, patience, interesting conversations and company. Words cannot express my gratitude for the sacrifices, patience, trust and support of my mother Saroja, my father Chakrapani, my sister Manjula and my brother-in-law Srivats. v TABLE OF CONTENTS DEDICATION ................................... iii ACKNOWLEDGEMENTS ............................ iv LIST OF TABLES ................................. ix LIST OF FIGURES ................................ x SUMMARY ..................................... xii I INTRODUCTION .............................. 1 1.1 Reading Guide and Roadmap ..................... 9 II HISTORICAL PERSPECTIVE AND BACKGROUND . 11 2.1 Logic, Computing and Probabilistic Algorithms ........... 11 2.2 Frequentist Interpretation of Probability and Probability in Logics .......................... 13 2.2.1 The Frequentist Interpretation of Probability ........ 13 2.2.2 Probability in Logics ...................... 15 2.3 Thermodynamics and the Energy Cost of Computing ........ 16 2.3.1 The Energy Cost of Probabilistic Computing ........ 20 2.4 Current Technology Challenges .................... 22 2.4.1 Probabilistic Complementary Metal Oxide Semiconductor Devices ............................. 23 2.4.2 Techniques for Energy Efficient and Error-free Computing . 25 2.4.3 The Trade off between Energy, Error and Quality of Solution 26 2.4.4 Theoretical Approaches to Computing in the Presence of Faults 27 2.4.5 Practical Approaches to Computing In the Presence of Faults 28 III A PROBABILISTIC BOOLEAN LOGIC AND ITS MEANING . 30 3.1 Probabilistic Boolean Logic and Well-Formed Formulae ....... 31 3.1.1 Boolean Logic Preliminaries .................. 32 3.1.2 The Operational Meaning of Probabilistic Boolean Operators 33 vi 3.1.3 Probabilistic Boolean Formulae and their Truth Tables ... 34 3.2 The Event Set Semantics of Probabilistic Boolean Logic ...... 35 3.2.1 A Frequentist View of Probabilistic Boolean Logic ..... 36 3.2.2 An Interpretation of a Probabilistic Boolean Formula for a Fixed Assignment Through Event Sets ............ 39 3.3 A Formal Model for Probabilistic Boolean Logic ........... 44 IV PROPERTIES OF PROBABILISTIC BOOLEAN LOGIC . 49 4.1 Classical Identities That are Preserved ................ 49 4.2 Identities that are not Preserved ................... 50 4.2.1 Associativity .......................... 50 4.2.2 Distributivity .......................... 51 4.3 Degree of Non-Associativity ...................... 52 4.3.1 Balanced Binary and Linear Probabilistic Boolean Formula 53 4.3.2 An Upper bound on the Probability of Unsatisfiability of a Balanced Binary Probabilistic Boolean Formula ....... 55 4.3.3 A Lower bound on the Probability of Unsatisfiability of a Linear Probabilistic Boolean Formula ............. 58 4.3.4 The Degree of Non-associativity of Probabilistic Boolean Logic 60 V PROBABILISTIC BOOLEAN LOGIC AND MODELS OF COMPUTING 62 5.0.5 Thermodynamic Separation of Implicitly and Explicitly Probabilistic Gates and The Circuit Model of Computation 62 5.0.6 Energy Considerations For Realizing Probabilistic and Randomized Boolean Operators ................ 66 5.0.7 Extending to Computational Model with State ....... 66 VI PROBABILISTIC ARCHITECTURES . 69 6.1 Probabilistic System on a Chip Architectures ............ 70 6.2 Energy and Performance Metrics for Probabilistic System on a Chip Architectures .............................. 72 6.2.1 Performance and Energy Modeling of Probabilistic System on a Chip Architectures .................... 73 6.3 A Co-design framework ........................ 74 vii 6.3.1 A Brief Description of the Applications of Interest ..... 75 6.3.2 Application Level Gains .................... 77 6.3.3 An Analysis of Gains ...................... 78 6.3.4 Implementation Independent Characteristics Influencing Co-design ............................ 79 6.3.5 Implementation Dependent Characteristics Influencing Co-design ............................ 84 6.4 A Comparison of Implicitly Probabilistic and Explicitly Random Circuits in the System on a Chip Context .............. 88 6.5 The Suite of Applications, Partitioning, Optimization and psoc Implementation ............................. 90 6.6 Some Practical Considerations .................... 95 6.6.1 Reducing Multiple Voltage Levels ............... 95 6.6.2 Quality of Randomization ................... 98 VII PROBABILISTIC ARITHMETIC ..................... 100 7.1 Abstracting a Mathematical Model .................. 101 7.1.1 A Mathematical Model for Deterministic Addition ..... 102 7.1.2 A Mathematical Model for Probabilistic Addition ...... 105 7.2 Cost and Magnitude of Error of Probabilistic Addition ....... 106 7.2.1 Error Magnitude of Probabilistic Addition .......... 107 7.3 Relative Magnitude of Error ...................... 110 7.4 Some Practical Considerations .................... 115 7.4.1 Truncation in Probabilistic Arithmetic ............ 117 7.5 Case Study of Probabilistic Arithmetic in Digital Signal Processing 119 VIII REMARKS AND FUTURE DIRECTIONS . 121 REFERENCES ..................................
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