DOCSLIB.ORG

Data-Parallel Programming on Manycore Graphics Processors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Data-Parallel Programming on Manycore Graphics Processors !"#"$%"&"''(')%&*+&",,-.+)*.) /".01*&()2&"34-15)%&*1(55*&5) 6&0".)7"#".8"&*) 9.-:(&5"')%"&"''(')7*,3;#-.+)<(5("&14)7(.#(&) 9.-:(&5-#0)*=)7"'-=*&.-">)6(&?('(0) Overview !! Terminology: Multicore, Manycore, SIMD !! The CUDA Programming model !! Mapping CUDA to Nvidia GPUs !! Experiences with CUDA Multicore and Manycore /;'#-1*&() /".01*&() !! Multicore: yoke of oxen "! Each core optimized for executing a single thread !! Manycore: flock of chickens "! Cores optimized for aggregate throughput, deemphasizing individual performance Multicore & Manycore, cont. !"#$%&$'()*+, -).#,%/,012, 345678, /*$#"%&0*/*123*4567* 9?*$#"%&0*@*123*4567* !"#$%&&'()*+,%-%(.&* 89:;*<=>* 8A:B*<=>* /*$#"%&0*;*.G"%2D&0*/* 9?*$#"%&0*9;*4567* C%&'D%(.*4."2(D&E 123*4567K* L%$.#"&0*9;*123* FG"%2D&*H-2IJ* 4567K* 7*&()-@)ABC.,D) 9;*&."2(D&* 9?M;?*.G"%2D&* 4!*<NOP!E&* A?;* A?@?* 6%-#"3*Q2(D1'D.G* ;B:R*<QE&* ABS*<QE&* C%)'&.%"*N',%* T* A:@MB*6Q* O#$2,*4.#"%* T* /@?*UQ* 2EFGHC)ACC.,D) What is a core? !! Is a core an ALU? "! ATI: We have 800 streaming processors!! !! Actually, we have 5 way VLIW * 16 way SIMD * 10 “SIMD cores” !! Is a core a SIMD vector unit? "! Nvidia: We have 240 streaming processors!! !! Actually, we have 8 way SIMD * 30 “multiprocessors” "! To match ATI, they could count another factor of 2 for dual issue !! In this lecture, we’re using core consistent with the CPU world "! Superscalar, VLIW, SIMD, SMT, etc. are part of a core’s architecture, not the number of cores SIMD a b a1 a2 b1 b2 IJ/!) IJI!) + + K-L#4MG) c c1 c2 !! Single Instruction Multiple Data architectures make use of data parallelism !! SIMD can be area and power efficient "! Amortize control overhead over SIMD width !! Parallelism exposed to programmer & compiler SIMD: Neglected Parallelism !! It is difficult for a compiler to exploit SIMD !! How do you deal with sparse data & branches? "! Many languages (like C) are difficult to vectorize "! Fortran is somewhat better !! Most common solution: "! Either forget about SIMD !! Pray the autovectorizer likes you "! Or instantiate intrinsics (assembly language) "! Requires a new code version for every SIMD extension A Brief History of x86 SIMD 8 x 8 bit Integer MMX 4 x 32 bit 4 x 32 bit 3dNow! SP Float Subset SSE SP Float 2 x 64 bit SSE2 DP Float Future Subset SSE3 ?? SSSE3 SSE4.1 SSE4.A SSE4.2 Larrabee 8 x 32 bit SSE5 AVX SP Float 16 x 32 bit SP Float AVX+FMA 3 operands What to do with SIMD? B)K"0)IJ/!)AIIND) OP)K"0)IJ/!)AQ<6D) !! Neglecting SIMD in the future will be more expensive "! AVX: 8 way SIMD, Larrabee: 16 way SIMD, Nvidia: 32 way SIMD, ATI: 64 way SIMD !! This problem composes with thread level parallelism !! We need a programming model which addresses both problems The CUDA Programming Model !! CUDA is a recent programming model, designed for "! Manycore architectures "! Wide SIMD parallelism "! Scalability !! CUDA provides: "! A thread abstraction to deal with SIMD "! Synchronization & data sharing between small groups of threads !! CUDA programs are written in C + extensions !! OpenCL uses very similar programming model, but is HW & SW vendor neutral Hierarchy of Concurrent Threads !! Parallel kernels composed of many threads "! all threads execute the same sequential program E4&("L)#) !! Threads are grouped into thread blocks "! threads in the same block can cooperate 6'*1?)R) !"#!$#%#!&# !! Threads/blocks have unique IDs What is a CUDA Thread? What is a CUDA Thread Block? Synchronization !! Threads within a block may synchronize with barriers #%#'!()#$#%# **+,-.!/0(12+345# %#'!()#6#%# !! Blocks coordinate via atomic memory operations "! e.g., increment shared queue pointer with 1!789.:-.34# !! Implicit barrier between dependent kernels ;(.*89-<+===->?7.@+A#>?@+9B(CCC31A#>A#.45# ;(.*27!===->?7.@+A#>?@+9B(CCC3.A#.45# Blocks must be independent Scalability !! Manycore chips exist in a diverse set of configurations S;,R(&)*=)1*&(5) 35 30 25 20 15 10 5 0 8300GS 9400M 8800GTX GTX285 !! 79!T)"''*K5)*.()R-."&0)#*)#"&+(#)"'')#4(5()14-35) !! E4&("L)R'*1?5)R&-.+)51"'"R-'-#0U) Hello World: Vector Addition DDE78)<!(#;(.!70#+<8#EFGHI# DDJ1./#!/0(12#)(0K708+#7-(#)190L9+(#1229!97-# **M?7>1?**#;792#;(.G223K?71!N#1A#K?71!N#>A#K?71!N#.4#O# #9-!#9#F#>?7.@:2PQP#N#>?7.@R98QP#H#!/0(12:2PQP5# #.S9T#F#1S9T#H#>S9T5# U# 9-!#819-34#O# #DDV<-#&D6WX#>?7.@+#7K#6WX#!/0(12+#(1./# #;(.G22===&D6WXA#6WXCCC32*1A#2*>A#2*.45# U# Flavors of parallelism !! Thread parallelism "! each thread is an independent thread of execution !! Data parallelism "! across threads in a block "! across blocks in a kernel !! Task parallelism "! different blocks are independent "! independent kernels Memory model Block E4&("L) %(&$#4&("L) %(&$R'*1?) Q*1"')/(,*&0) I4"&(L)/(,*&0) Memory model V) Per Device Global V) Memory Memory model Device ? Memory Host !"#$%&'!()*+, Memory Device A Memory Using per-block shared memory 6'*1?) Shared CUDA: Minimal extensions to C/C++ !! Declaration specifiers to indicate where things live #**M?7>1?**#;792#Y(0-(?Z<-.3QQQ45##DD#kernel callable from host #**2(;9.(**#;792#R(;9.(Z<-.3QQQ45##DD#function callable on device #**2(;9.(**#9-!##[?7>1?\105 #####DD#variable in device memory #**+/10(2**#9-!##'/10(2\105 #####DD#in per-block shared memory !! Extend function invocation syntax for parallel kernel launch Y(0-(?Z<-.===W""A#$6]CCC3QQQ45####DD#500 blocks, 128 threads each !! Special variables for thread identification in kernels 298^#!/0(12:2P5##298^#>?7.@:2P5##298^#>?7.@R985# !! Intrinsics that expose specific operations in kernel code **+,-.!/0(12+345#################DD#barrier synchronization# CUDA: Features available on GPU CUDA: Runtime support Mapping CUDA to Nvidia GPUs !! CUDA is designed to be functionally forgiving "! First priority: make things work. Second: get performance. !! However, to get good performance, one must understand how CUDA is mapped to Nvidia GPUs !! Threads: "! each thread is a SIMD vector lane !! Warps: "! A SIMD instruction acts on a “warp” "! Warp width is 32 elements: LOGICAL SIMD width !! Thread blocks: "! Each thread block is scheduled onto a processor "! Peak efficiency requires multiple thread blocks per processor Mapping CUDA to a GPU, continued !! The GPU is very deeply pipelined "! Throughput machine, trying to hide memory latency !! This means that performance depends on the number of thread blocks which can be allocated on a processor !! Therefore, resource usage costs performance: "! More registers => Fewer thread blocks "! More shared memory usage => Fewer thread blocks "! In general: More resources => less effective parallelism !! It is often worth trying to reduce register count in order to get more thread blocks to fit on the chip SIMD & Control Flow Memory, Memory, Memory ! Chapter 1. Introduction to CUDA "#$%&'(')#*!+!,-("'./!01('!23(%1)"4!3,*5,3)*2!)4!(6#&'!+!(*5!'1,3,7#3,!5,4)2*,5! !! A many4&"1!'1('!$#3,!'3(*4)4'#34!(3,!5,8#',5!'#!5('(!%3#",44)*2!3('1,3!'1(*!5('(!"("1)*2! core processor ! A device for turning a compute bound(*5!7.#0!"#*'3#.9!(4!4"1,$(')"(../!)..&4'3(',5!6/! problem into a memory bound:)2&3,!;<=>! problem ! Control ALU ALU ALU ALU Cache DRAM DRAM CPU GPU ! !! Lots of processors, only one socket Figure 1-2. The GPU Devotes More Transistors to Data !! Memory concernsProcessing dominate performance tuning ! ?#3,!4%,")7)"(../9!'1,!@AB!)4!,4%,")(../!0,..<4&)',5!'#!(553,44!%3#6.,$4!'1('!"(*!6,! ,-%3,44,5!(4!5('(<%(3(..,.!"#$%&'(')#*4!+!'1,!4($,!%3#23($!)4!,-,"&',5!#*!$(*/! 5('(!,.,$,*'4!)*!%(3(..,.!+!0)'1!1)21!(3)'1$,')"!)*',*4)'/!+!'1,!3(')#!#7!(3)'1$,')"! #%,3(')#*4!'#!$,$#3/!#%,3(')#*4>!C,"(&4,!'1,!4($,!%3#23($!)4!,-,"&',5!7#3!,("1! 5('(!,.,$,*'9!'1,3,!)4!(!.#0,3!3,D&)3,$,*'!7#3!4#%1)4')"(',5!7.#0!"#*'3#.E!(*5! 6,"(&4,!)'!)4!,-,"&',5!#*!$(*/!5('(!,.,$,*'4!(*5!1(4!1)21!(3)'1$,')"!)*',*4)'/9!'1,! $,$#3/!("",44!.(',*"/!"(*!6,!1)55,*!0)'1!"(."&.(')#*4!)*4',(5!#7!6)2!5('(!"("1,4>! F('(<%(3(..,.!%3#",44)*2!$(%4!5('(!,.,$,*'4!'#!%(3(..,.!%3#",44)*2!'13,(54>!?(*/! (%%.)"(')#*4!'1('!%3#",44!.(32,!5('(!4,'4!"(*!&4,!(!5('(<%(3(..,.!%3#23($$)*2!$#5,.! '#!4%,,5!&%!'1,!"#$%&'(')#*4>!G*!HF!3,*5,3)*2!.(32,!4,'4!#7!%)-,.4!(*5!8,3')",4!(3,! $(%%,5!'#!%(3(..,.!'13,(54>!I)$).(3./9!)$(2,!(*5!$,5)(!%3#",44)*2!(%%.)"(')#*4!4&"1! (4!%#4'<%3#",44)*2!#7!3,*5,3,5!)$(2,49!8)5,#!,*"#5)*2!(*5!5,"#5)*29!)$(2,!4"(.)*29! 4',3,#!8)4)#*9!(*5!%('',3*!3,"#2*)')#*!"(*!$(%!)$(2,!6.#"J4!(*5!%)-,.4!'#!%(3(..,.! %3#",44)*2!'13,(54>!G*!7("'9!$(*/!(.2#3)'1$4!#&'4)5,!'1,!7),.5!#7!)$(2,!3,*5,3)*2! (*5!%3#",44)*2!(3,!("",.,3(',5!6/!5('(<%(3(..,.!%3#",44)*29!73#$!2,*,3(.!4)2*(.! %3#",44)*2!#3!%1/4)"4!4)$&.(')#*!'#!"#$%&'(')#*(.!7)*(*",!#3!"#$%&'(')#*(.!6)#.#2/>! K1,!LBFM!%3#23($$)*2!$#5,.!)4!8,3/!0,..!4&)',5!'#!,-%#4,!'1,!%(3(..,.! "(%(6).)'),4!#7!@AB4>!K1,!.(',4'!2,*,3(')#*!#7!NOGFGM!@AB49!6(4,5!#*!'1,!K,4.(! (3"1)',"'&3,!P4,,!M%%,*5)-!M!7#3!(!.)4'!#7!(..!LBFM<"(%(6.,!@AB4Q9!4&%%#3'4!'1,! LBFM!%3#23($$)*2!$#5,.!(*5!'3,$,*5#&4./!("",.,3(',4!LBFM!(%%.)"(')#*4>! ! CUDA Programming Guide Version 2.0 3! Memory is SIMD too !! Virtually all processors have SIMD memory subsystems ?* A* ;* 9* /* B* R* M* 1"14()'-.()K-L#4) !! E4-5)4"5)#K*)(W(1#5X) !! I3"&5()"11(55)K"5#(5)R".LK-L#4) G)K*&L5);5(L>)H)K*&L5)'*"L(LX) ? A ; 9 / B R M * * * * * * * * Y))(W(1#-:()R".LK-L#4) !! 9."'-+.(L)"11(55)K"5#(5)R".LK-L#4) B)K*&L5);5(L>)H)K*&L5)'*"L(LX) ?* A* ;* 9* /* B* R* M* Z)(W(1#-:()R".LK-L#4) Coalescing !! Current GPUs don’t have cache lines as such, but they do have similar issues with alignment and sparsity !! Nvidia GPUs have a “coalescer”, which examines memory requests dynamically and coalesces them into vectors !! To use bandwidth effectively,
Load more

Recommended publications
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • RISC-V Vector Extension Webinar I
    RISC-V Vector Extension Webinar I July 13th, 2021 Thang Tran, Ph.D. Principal Engineer Who WeAndes Are Technology Corporation CPU Pure-play RISC-V Founding Major Open-Source CPU IP Vendor Premier Member Contributor/Maintainer RISC-V Ambassador 16-year-old Running Task Groups Public Company TSC Vice Chair Director of the Board Quick Facts + NL 100 years 80% FR BJ KR USA JP IL SH CPU Experience in Silicon Valley R&D SZ TW (HQ) 200+ 20K+ 7B+ Licensees AndeSight IDE Total shipment of Andes- installations Embedded™ SoC Confidential Taking RISC-V® Mainstream 2 Andes Technology Corporation Overview Andes Highlights •Founded in March 2005 in Hsinchu Science Park, Taiwan, ROC. •World class 32/64-bit RISC-V CPU IP public company •Over 200 people; 80% are engineers; R&D team consisting of Silicon Valley veterans •TSMC OIP Award “Partner of the Year” for New IP (2015) •A Premier founding member of RISC-V Foundation •2018 MCU Innovation Award by China Electronic News: AndesCore™ N25F/NX25F •ASPENCORE WEAA 2020 Outstanding Product Performance of the Year: AndesCore™ NX27V •2020 HsinChu Science Park Innovation Award: AndesCore™ NX27V Andes Mission • Trusted Computing Expert and World No.1 RISC-V IP Provider Emerging Opportunities • AIoT, 5G/Networking, Storage and Cloud computing 3 V5 Adoptions: From MCU to Datacenters • Edge to Cloud: − ADAS − Datacenter AI accelerators − AIoT − SSD: enterprise (& consumer) − Blockchain − 5G macro/small cells − FPGA − MCU − Multimedia − Security − Wireless (BT/WiFi) 5G Macro • 1 to 1000+ core • 40nm to 5nm • Many in AI Copyright© 2020 Andes Technology Corp. 4 Webinar I - Agenda • Andes overview • Vector technology background – SIMD/vector concept – Vector processor basic • RISC-V V extension ISA – Basic – CSR – Memory operations – Compute instructions • Sample codes – Matrix multiplication – Loads with RVV versions 0.8 and 1.0 • AndesCore™ NX27V introduction • Summary Copyright© 2020 Andes Technology Corp.
    [Show full text]
  • NASM – the Netwide Assembler
    NASM – The Netwide Assembler version 2.14rc7 © 1996−2017 The NASM Development Team — All Rights Reserved This document is redistributable under the license given in the file "LICENSE" distributed in the NASM archive. Contents Chapter 1: Introduction . 17 1.1 What Is NASM?. 17 1.1.1 License Conditions . 17 Chapter 2: Running NASM . 19 2.1 NASM Command−Line Syntax . 19 2.1.1 The −o Option: Specifying the Output File Name . 19 2.1.2 The −f Option: Specifying the Output File Format . 20 2.1.3 The −l Option: Generating a Listing File . 20 2.1.4 The −M Option: Generate Makefile Dependencies. 20 2.1.5 The −MG Option: Generate Makefile Dependencies . 20 2.1.6 The −MF Option: Set Makefile Dependency File. 20 2.1.7 The −MD Option: Assemble and Generate Dependencies . 20 2.1.8 The −MT Option: Dependency Target Name . 21 2.1.9 The −MQ Option: Dependency Target Name (Quoted) . 21 2.1.10 The −MP Option: Emit phony targets . 21 2.1.11 The −MW Option: Watcom Make quoting style . 21 2.1.12 The −F Option: Selecting a Debug Information Format . 21 2.1.13 The −g Option: Enabling Debug Information. 21 2.1.14 The −X Option: Selecting an Error Reporting Format . 21 2.1.15 The −Z Option: Send Errors to a File. 22 2.1.16 The −s Option: Send Errors to stdout ..........................22 2.1.17 The −i Option: Include File Search Directories . 22 2.1.18 The −p Option: Pre−Include a File . 22 2.1.19 The −d Option: Pre−Define a Macro .
    [Show full text]
  • AMD's Bulldozer Architecture
    AMD's Bulldozer Architecture Chris Ziemba Jonathan Lunt Overview • AMD's Roadmap • Instruction Set • Architecture • Performance • Later Iterations o Piledriver o Steamroller o Excavator Slide 2 1 Changed this section, bulldozer is covered in architecture so it makes sense to not reiterate with later slides Chris Ziemba, 鳬o AMD's Roadmap • October 2011 o First iteration, Bulldozer released • June 2013 o Piledriver, implemented in 2nd gen FX-CPUs • 2013 o Steamroller, implemented in 3rd gen FX-CPUs • 2014 o Excavator, implemented in 4th gen Fusion APUs • 2015 o Revised Excavator adopted in 2015 for FX-CPUs and beyond Instruction Set: Overview • Type: CISC • Instruction Set: x86-64 (AMD64) o Includes Old x86 Registers o Extends Registers and adds new ones o Two Operating Modes: Long Mode & Legacy Mode • Integer Size: 64 bits • Virtual Address Space: 64 bits o 16 EB of Address Space (17,179,869,184 GB) • Physical Address Space: 48 bits (Current Versions) o Saves space/transistors/etc o 256TB of Address Space Instruction Set: ISA Registers Instruction Set: Operating Modes Instruction Set: Extensions • Intel x86 Extensions o SSE4 : Streaming SIMD (Single Instruction, Multiple Data) Extension 4. Mainly for DSP and Graphics Processing. o AES-NI: Advanced Encryption Standard (AES) Instructions o AVX: Advanced Vector Extensions. 256 bit registers for computationally complex floating point operations such as image/video processing, simulation, etc. • AMD x86 Extensions o XOP: AMD specified SSE5 Revision o FMA4: Fused multiply-add (MAC) instructions
    [Show full text]
  • C++ Code __M128 Add (Const __M128 &X, Const __M128 &Y){ X X3 X2 X1 X0 Return Mm Add Ps(X, Y); } + + + + +
    ECE/ME/EMA/CS 759 High Performance Computing for Engineering Applications Final Project Related Issues Variable Sharing in OpenMP OpenMP synchronization issues OpenMP performance issues November 9, 2015 Lecture 24 © Dan Negrut, 2015 ECE/ME/EMA/CS 759 UW-Madison Quote of the Day “Without music to decorate it, time is just a bunch of boring production deadlines or dates by which bills must be paid.” -- Frank Zappa, Musician 1940 - 1993 2 Before We Get Started Issues covered last time: Final Project discussion Open MP optimization issues, wrap up Today’s topics SSE and AVX quick overview Parallel computing w/ MPI Other issues: HW08, due on Wd, Nov. 10 at 11:59 PM 3 Parallelism, as Expressed at Various Levels Cluster Group of computers communicating through fast interconnect Coprocessors/Accelerators Special compute devices attached to the local node through special interconnect Node Group of processors communicating through shared memory Socket Group of cores communicating through shared cache Core Group of functional units communicating through registers Hyper-Threads Group of thread contexts sharing functional units Superscalar Group of instructions sharing functional units Pipeline Sequence of instructions sharing functional units Vector Single instruction using multiple functional units Have discussed already Haven’t discussed yet 4 [Intel] Have discussed, but little direct control Instruction Set Architecture (ISA) Extensions Extensions to the base x86 ISA One way the x86 has evolved over the years Extensions for vectorizing
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • An Introduction to CUDA/Opencl and Graphics Processors
    An Introduction to CUDA/OpenCL and Graphics Processors Bryan Catanzaro, NVIDIA Research Overview ¡ Terminology ¡ The CUDA and OpenCL programming models ¡ Understanding how CUDA maps to NVIDIA GPUs ¡ Thrust 2/74 Heterogeneous Parallel Computing Latency Throughput Optimized CPU Optimized GPU Fast Serial Scalable Parallel Processing Processing 3/74 Latency vs. Throughput Latency Throughput ¡ Latency: yoke of oxen § Each core optimized for executing a single thread ¡ Throughput: flock of chickens § Cores optimized for aggregate throughput, deemphasizing individual performance ¡ (apologies to Seymour Cray) 4/74 Latency vs. Throughput, cont. Specificaons Sandy Bridge- Kepler EP (Tesla K20) 8 cores, 2 issue, 14 SMs, 6 issue, 32 Processing Elements 8 way SIMD way SIMD @3.1 GHz @730 MHz 8 cores, 2 threads, 8 14 SMs, 64 SIMD Resident Strands/ way SIMD: vectors, 32 way Threads (max) SIMD: Sandy Bridge-EP (32nm) 96 strands 28672 threads SP GFLOP/s 396 3924 Memory Bandwidth 51 GB/s 250 GB/s Register File 128 kB (?) 3.5 MB Local Store/L1 Cache 256 kB 896 kB L2 Cache 2 MB 1.5 MB L3 Cache 20 MB - Kepler (28nm) 5/74 Why Heterogeneity? ¡ Different goals produce different designs § Manycore assumes work load is highly parallel § Multicore must be good at everything, parallel or not ¡ Multicore: minimize latency experienced by 1 thread § lots of big on-chip caches § extremely sophisticated control ¡ Manycore: maximize throughput of all threads § lots of big ALUs § multithreading can hide latency … so skip the big caches § simpler control, cost amortized over
    [Show full text]
  • (GAMI) API Specification Designed and Implemented for Intel® Rack Scale Design Software V2.3.2 Release
    Intel® Rack Scale Design (Intel® RSD) Generic Assets Management Interface (GAMI) API Specification Software v2.3.2 September 2018 Revision 003US Document Number: 337206-003US All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at www.intel.com. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and noninfringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Copies of documents that have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting http://www.intel.com/design/literature.htm. Intel, Xeon, and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2018 Intel Corporation. All rights reserved. Intel® RSD GAMI API Specification Software v2.3.2 September 2018 2 Document Number: 337206-003US Contents 1.0 Introduction ........................................................................................................................................................................
    [Show full text]
  • 128-Bit SSE5 Instruction Set and Supplemental 64-Bit Media
    AMD64 Technology 128-Bit SSE5 Instruction Set Publication No. Revision Date 43479 3.01 August 2007 Advanced Micro Devices © 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
    [Show full text]
  • Zynq-7000 All Programmable Soc Architecture Porting Quick Start Guide
    Zynq-7000 All Programmable SoC Architecture Porting Quick Start Guide UG1181 (v1.1.1) October 22, 2015 Revision History The following table shows the revision history for this document. Date Version Revision 10/22/2015 1.1.1 Updated title. 08/31/2015 1.1 Updated the TrustZone section. 06/25/2015 1.0 Initial Xilinx release. Architecture Porting Guide www.xilinx.com Send Feedback 2 UG1181 (v1.1.1) October 22, 2015 Table of Contents Revision History . 2 Chapter 1: Introduction Chapter 2: Porting Considerations ARM Cortex-A9 Features . 6 Chapter 3: Feature Comparison Across Architectures Architectural Comparison . 13 Address Maps. 18 Detailed Porting Guides: MIPS, PowerPC, Intel, and Renesas . 24 Appendix A: Additional Resources and Legal Notices Xilinx Resources . 25 Solution Centers. 25 References . 25 Please Read: Important Legal Notices . 25 Architecture Porting Guide www.xilinx.com Send Feedback 3 UG1181 (v1.1.1) October 22, 2015 Chapter 1 Introduction This document supports Xilinx® Zynq®-7000 All Programmable (AP) SoC customers that want to port embedded software from non ARM based processors to an ARM processing architecture. This porting guide references documentation on porting for PowerPC®, Intel®, Renesas-SH, and MIPS processors to ARM processors. (Zynq-7000 AP SoC contains the ARM® Cortex®-A9 dual core processor.) The ARM Cortex-A9 processor is a popular general purpose choice for low-power or thermally constrained, cost-sensitive devices. The processor is a mature option and remains a very popular choice for smart phones, digital TV, and both consumer and enterprise applications enabling the Internet of Things. The Cortex-A9 processor is available with a range of supporting ARM technology.
    [Show full text]
  • SHA-3 Conference, March 2012, BLAKE and 256-Bit Advanced
    BLAKE and 256-bit advanced vector extensions Samuel Neves1 and Jean-Philippe Aumasson2 1 University of Coimbra, Portugal 2 NAGRA, Switzerland Abstract. Intel recently documented its AVX2 instruction set extension that introduces support for 256-bit wide single-instruction multiple-data (SIMD) integer arithmetic over double (32-bit) and quad (64-bit) words. This will enable Intel’s future processors—starting with the Haswell architecture, to be released in 2013—to fully support 4-way SIMD com­ putation of 64-bit ARX algorithms (32-bit is already supported since SSE2). AVX2 also introduces instructions with potential to speed-up cryptographic functions, like any-to-any permute and vectorized table lookup. In this paper we show how the AVX2 instructions will benefit the SHA-3 finalist hash function BLAKE, an algorithm that naturally lends itself to 4-way 32- or 64-bit SIMD implementations thanks to its inherent parallelism. We also wrote BLAKE-256 assembly code for AVX and AVX2, and measured for the former a speed of 7.62 cycles per byte, setting a new speed record. Keywords: hash functions, SHA-3, implementation, SIMD 1 Introduction NIST will announce the winner of the SHA-3 competition3 in the second quarter of 2012. At the time of writing (February 26, 2012), no significant security weakness has been discovered on any of the five finalists—BLAKE, Grøstl, JH, Keccak, and Skein—and all seem to provide a comfortable margin of security against future attacks. It is thus expected that secondary evaluation criteria such as performance and ease of implementation will be decisive in the choice of SHA-3.
    [Show full text]
  • Six-Core AMD Opteron Processor Istanbul Paul G. Howard, Ph.D
    Six-Core AMD Opteron Processor Istanbul Paul G. Howard, Ph.D. Chief Scientist, Microway, Inc. Copyright 2009 by Microway, Inc. In April 2009 AMD™ announced the first 6-core Opteron processor, codenamed Istanbul1; delivery began in June 2009, four months ahead of schedule. Istanbul is based on the AMD 64-bit K10 architecture, and is available for 2-, 4-, and 8-socket systems, with clock speeds ranging from 2.0 to 2.8 GHz. Istanbul is the successor to the quad-core Shanghai processor, launched in 2008. It provides up to 30 percent more performance in the same socket and with the same power draw. Here is a summary of the features of the 6-core Istanbul processor: • Six cores mean more performance, and also more performance per watt because the power and thermal envelopes are the same as for 4-core processors • Consistent architecture, scalable to 2, 4, or 8 processor systems • Energy efficient, incorporates AMD-P power management • Virtualization support using AMD-V • Improved bandwidth, through the use of HyperTransport 3.0 and HT Assist. The current state of AMD Opteron processors Istanbul is based on the AMD K10 64-bit architecture and manufactured on a 45 nm SOI process2. Processors in the K10 line to date are shown in the following table. Code Frequency L3 cache Model number Introduction name Cores Sockets (GHz) (MB) Process range3 date Barcelona 4 4 or 8 1.9-2.5 2 65 nm 8346-8360 September 2007 Barcelona 4 2 1.9-2.5 2 65 nm 2344-2360 September 2007 Budapest 4 1 2.1-2.5 2 65 nm 1352-1356 June 2008 Shanghai 4 4 or 8 2.2-3.1 6 45 nm 8374-8393 November 2008 Shanghai 4 2 2.1-3.1 6 45 nm 2372-2393 November 2008 Suzuka 4 1 2.5-2.9 6 45 nm 1381-1389 June 2009 Istanbul 6 4 or 8 2.1-2.8 6 45 nm 8425-8439 June 2009 Istanbul 6 2 2.0-2.8 6 45 nm 2423-2439 June 2009 Budapest uses the same core as Barcelona, and Suzuka uses the same core as Shanghai.
    [Show full text]