128-Bit SSE5 Instruction Set and Supplemental 64-Bit Media

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128-Bit SSE5 Instruction Set and Supplemental 64-Bit Media

AMD64 Technology 128-Bit SSE5 Instruction Set Publication No. Revision Date 43479 3.01 August 2007 Advanced Micro Devices © 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. MMX is a trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 43479—Rev. 3.01—August 2007 AMD64 Technology Contents Revision History. xi Preface. xiii 1 New 128-Bit Instructions. .1 1.1 New 128-Bit Media Instruction Format . 1 1.2 Four-Operand 128-Bit Media Instructions . 3 1.3 Three-Operand 128-Bit Media Instructions. 5 1.4 Other 128-Bit Media Instructions . .6 1.5 16-Bit Floating-Point Data Type . .7 1.6 Floating Point Multiply and Add/Subtract . 9 1.7 Integer Multiply (Add) and Accumulate Instructions . 10 1.8 Packed Integer Horizontal Add and Subtract . 12 1.9 Vector Conditional Moves. 13 1.10 Packed Integer Rotates and Shifts . .14 1.11 Floating Point Comparison and Predicate Generation. 14 1.12 Test Instruction . 15 1.13 Precision Control and Rounding . .16 1.14 Convert . 16 2 SSE5 128-Bit Media Instructions . .17 2.1 Notation . 17 2.2 Instruction Reference. 18 COMPD . 18 COMPS . 21 COMSD . 24 COMSS . 28 CVTPH2PS . 31 CVTPS2PH . 33 FMADDPD . 36 FMADDPS . 39 FMADDSD . 42 FMADDSS . 45 FMSUBPD. 48 FMSUBPS . 51 FMSUBSD. 54 FMSUBSS . 57 FNMADDPD. 60 FNMADDPS . 63 FNMADDSD. 66 FNMADDSS . 69 FNMSUBPD . 72 FNMSUBPS . 75 FNMSUBSD . 78 FNMSUBSS . 81 Contents iii AMD64 Technology 43479—Rev. 3.01—August 2007 FRCZPD . 84 FRCZPS. 86 FRCZSD . 88 FRCZSS. 90 PCMOV . 92 PCOMB . 95 PCOMD . 98 PCOMQ . 101 PCOMUB . 104 PCOMUD . 107 PCOMUQ . 110 PCOMUW . ..

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