aerospace Article An Implementation of Real-Time Phased Array Radar Fundamental Functions on a DSP-Focused, High-Performance, Embedded Computing Platform Xining Yu 1,*, Yan Zhang 1, Ankit Patel 1, Allen Zahrai 2 and Mark Weber 2 1 School of Electrical and Computer Engineering, University of Oklahoma, 3190 Monitor Avenue, Norman, OK 73019, USA;
[email protected] (Y.Z.);
[email protected] (A.P.) 2 National Severe Storms Laboratory, National Oceanic and Atomospheric Administration, Norman, OK 73072, USA;
[email protected] (A.Z.);
[email protected] (M.W.) * Correspondence:
[email protected]; Tel.: +1-405-325-2871 Academic Editor: Konstantinos Kontis Received: 22 July 2016; Accepted: 2 September 2016; Published: 9 September 2016 Abstract: This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of general purpose digital signal processors. First, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on a Micro Telecom Computing Architecture (MTCA) chassis using the Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebones design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including the Open Computing Language. Keywords: phased array radar; embedded computing; serial RapidIO; MPAR 1. Introduction 1.1. Real-Time, Large-Scale, Phased Array Radar Systems In [1], we had introduced the real-time phased array radar (PAR) processing based on the Micro Telecom Computing Architecture (MTCA) chassis.