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Mpeg 2.5 Layer Iii Audio Decoder with Adpcm Capability Product Preview

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Mpeg 2.5 Layer Iii Audio Decoder with Adpcm Capability Product Preview STA015 STA015B STA015T MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY PRODUCT PREVIEW SINGLE CHIP MPEG LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) - Lower sampling frequenciessyntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAM- PLING FREQUENCIES AND THE EXTEN- SION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMEN- TARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s ORDERING NUMBERS: STA015 (SO28) ADPCM CODEC CAPABILITIES: STA015T (TQFP44) - sample frequencyfrom 8 kHz to 32 kHz STA015B (LFBGA 64) - sample size from8 bits to 32 bits - encodingalgorithm: DVI, ITU-G726pack (G723-24,G721,G723-40) - Tone controlandfast-forwardcapability EASY PROGRAMMABLE GPSO INTERFACE APPLICATIONS FOR ENCODED DATA UP TO 5Mbit/s (TQFP44 & LFBGA 64) PC SOUND CARDS DIGITAL VOLUME MULTIMEDIA PLAYERS BASS & TREBLE CONTROL VOICE RECORDERS BYPASS MODE FOR EXTERNAL AUDIO SOURCE DESCRIPTION SERIAL BITSTREAM INPUT INTERFACE The STA015 is a fully integrated high flexibility EASY PROGRAMMABLE ADC INPUT INTER- MPEG Layer III Audio Decoder, capable of de- FACE coding Layer III compressed elementary streams, ANCILLARY DATA EXTRACTION VIA I2C IN- as specified in MPEG 1 and MPEG 2 ISO stand- TERFACE. ards. The device decodes also elementarystreams 2 compressed by using low sampling rates, as speci- SERIAL PCM OUTPUT INTERFACE (I S fied by MPEG 2.5. AND OTHER FORMATS) STA015 receives the input data through a Serial PLL FOR INTERNAL CLOCK AND FOR OUT- Input Interface. The decoded signal is a stereo, PUT PCM CLOCK GENERATION mono, or dual channel digital output that can be CRC CHECK AND SYNCHRONISATION ER- sent directly to a D/A converter, by the PCM Out- ROR DETECTION WITH SOFTWARE INDI- put Interface. This interface is software program- CATORS mable to adapt the STA015 digital output to the I2C CONTROL BUS most common DACs architectures used on the LOW POWER 2.4V CMOS TECHNOLOGY market. WIDE RANGE OF EXTERNAL CRYSTALS The functional STA015 chip partitioning is de- FREQUENCIES SUPPORTED scribed in Fig.1a and Fig.1b. August 2000 1/44 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. STA015-STA015B-STA015T Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package SDA SCL 31 32 35 STROBE TQFP44 20 18 2 I C CONTROL 16 14 34 SDI GPIO 37 IODATA INTERFACE [7:0] 36 SERIAL 39 SCKR INPUT DSP BASED 41 38 INTERFACE BIT_EN 43 MPEG L III VOLUME 27 BUFFER OUTPUT 42 DATA-REQ PARSER ADPCM & TONE SDO 256 x 8 BUFFER CORE CONTROL PCM 44 40 OUTPUT SCKT SCK_ADC INTERFACE 2 26 ADC LRCKT LRCK_ADC INPUT 3 24 INTERFACE OCLK SDI_ADC 4 GPSO_REQ SYSTEM & AUDIO CLOCKS 28 GPSO GPSO_SCKR INTERFACE 33 GPSO_DATA 25 15 13 22 12 RESET XTI XTOTESTEN FILT D99AU1116A Note: pin numbers refer to TQFP44 only. Figure 1b. BLOCK DIAGRAM for SO28 package SDA SCL 34 SO28 I2C CONTROL 5 SDI 6 SERIAL SCKR INPUT DSP BASED 7 INTERFACE BIT_EN 9 SDO MPEG L III VOLUME 28 BUFFER OUTPUT PCM 10 DATA-REQ PARSER ADPCM & TONE OUTPUT SCKT 256 x 8 BUFFER CORE CONTROL INTERFACE 11 8 LRCKT SCK_ADC 12 27 ADC OCLK LRCK_ADC INPUT 25 INTERFACE SDI_ADC SYSTEM & AUDIO CLOCKS 26 21 20 24 19 RESET XTI XTOTESTEN FILT D99AU1117A 2/44 STA015-STA015B-STA015T Figure 2. PIN CONNECTIONS VDD_1 1 28 OUT_CLK/DATA_REQ VSS_1 2 27 LRCK_ADC SDA 3 26 RESET SCL 4 25 SDI_ADC SDI 5 24 TESTEN SCKR 6 23 VDD_4 BIT_EN 7 22 VSS_4 SRC_INT/SCK_ADC 8 SO28 21 XTI SDO 9 20 XTO SCKT 10 19 FILT LRCKT 11 18 PVSS OCLK 12 17 PVDD VSS_2 13 16 VDD_3 VDD_2 14 15 VSS_3 D99AU1061 SCKT IODATA[7] SDO IODATA[6] SRC_INT/SCK_ADC IODATA[5] BIT_EN IODATA[4] SCKR GPIO/STROBE SDI 44 43 42 4140 39 38 37 36 35 34 N.C. 1 33 GPSO_DATA LRCKT 2 32 SCL OCLK 3 31 SDA GPSO_REQ 4 30 VSS_1 VSS_2 5 29 VDD_1 VDD_2 6 TQFP44 28 GPSO_SCKR VSS_3 7 27 OUT_CLK/DATA_REC VDD_3 8 26 LRCK_ADC N.C. 9 25 RESET PVDD 10 24 SDI_ADC PVSS 11 23 N.C. 12 13 14 15 16 17 18 19 20 21 22 D99AU1062 XTI N.C. FILT XTO VSS_4 VDD_4 TESTEN IODATA[3] IODATA[2] IODATA[1] IODATA[0] 8 7 6 5 4 3 2 1 A1 = SDI G7 = FILT C2 = GPIO_STROBE B2 = SCKR G8 = XTO C3 = IODATA [4] A D4 = BIT_EN F7 = XTI E3 = IODATA [5] B D1 = SRC_INT E7 = VSS_4 D2 = IODATA [6] C E2 = SDO C8 = VDD_4 F1 = IODATA [7] F2 = SCKT D7 = TESTEN G3 = GPSO_REQ D H1 = LRCKT A7 = SDI_ADC F8 = IODATA [3] E H3 = OCLK B6 = RESET F6 = IODATA [2] F3 = VSS_2 A5 = LRCK_ADC E6 = IODATA [1] F E4 = VDD_2 C5 = OUT_CLK/DATA_REQ C7 = IODATA [0] G G4 = VSS_3 B5 = VDD_1 C6 = GPSO_SCKR G5 = VDD_3 B4 = VSS_1 A2 = GPSO_DATA H F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL D00AU1149 LFBGA64 3/44 STA015-STA015B-STA015T 1. OVERVIEW rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces 1.1 - MP3 decoder engine can be used to feed data: the serial input inter- face (same interface used also to feed MP3 bit- The MP3 decoder engine is able to decode any stream) or the ADC input interface, which pro- Layer III compliant bitstream: MPEG1, MPEG2 vides a seamless connection with an external A/D and MPEG2.5 streams are supported. Besides converter. audio data decoding the MP3 engine also per- The currently used interface is selected via I2C forms ANCILLARY data extraction: these data bus. can be retrieved via I2C bus by the application Also to retrieve encoded data two different inter- microcontroller in order to implement specific faces are available: the I2C bus or the faster functions. GPSO output interface. GPSO interface is able to Decoded audio data goes through a software vol- output data with a bitrate up to 5 Mbit/s and its ume control and a two-band equalizer blocks be- control pins (GPSO_SCKR, GPSO_DATA and fore feeding the output I2S interface. This results GPSO_REQ) can be configured in order to easily in no need for an external audio processor. fit the target application. MP3 bitstream is sent to the decoder using a sim- ple serial input interface (see pins SDI, SCKR, 1.3 - BYPASS functional mode BIT_EN and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input buffer which provides a In order to allow using the device to post-process feedback line (see DATA_REQ pin) to the bit- auxiliary audio sources a special BYPASS mode stream source (tipically an MCU). is available. When the device is configured in BYPASS mode 1.2 - ADPCM encoder/decoder engine the embedded DSP will process digital audio data coming through the ADC input interface and will output the resulting data to the external DAC. This device also embeds a multistandard ADPCM Available processings include volume and a tone encoder/decoder supporting different sample controls. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD Power Supply -0.3 to 4 V Vi Voltage on Input pins -0.3 to VDD +0.3 V VO Voltage on output pins -0.3 to VDD +0.3 V Tstg Storage Temperature -40 to +150 °C Toper Operative ambient temp -20 to +85 °C THERMAL DATA Symbol Parameter Value Unit Rth j-amb Thermal resistance Junction to Ambient 85 °C/W 4/44 STA015-STA015B-STA015T PIN DESCRIPTION SO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description 1 29 B5 VDD_1 Supply Voltage 2 30 B4 VSS_1 Ground 3 31 A4 SDA I/O i2C Serial Data + CMOS Input Pad Buffer Acknowledge CMOS 4mA Output Drive 4 32 B3 SCL I I2C Serial Clock CMOS Input Pad Buffer 5 34 A1 SDI I Receiver Serial Data CMOS Input Pad Buffer 6 36 B2 SCKR I Receiver Serial Clock CMOS Input Pad Buffer 7 38 D4 BIT_EN I Bit Enable CMOSInput Pad Buffer with pull up 8 40 D1 SRC_INT/SCK_ADC I Interrupt Line/ADC Serial CMOS Input Pad Buffer Clock 9 42 E2 SDO O TransmitterSerialData(PCMData) CMOS 4mA Output Drive 10 44 F2 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive 11 2 H1 LRCLKT O Transmitter Left/Right Clock CMOS 4mA Output Drive 12 3 H3 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer CMOS 4mA Output Drive 13 5 F3 VSS_2 Ground 14 6 E4 VDD_2 Supply Voltage 15 7 G4 VSS_3 Ground 16 8 G5 VDD_3 Supply Voltage 17 10 F5 PVDD PLL Power 18 11 G6 PVSS PLL Ground 19 12 G7 FILT O PLL Filter Ext. Capacitor Conn. 20 13 G8 XTO O Crystal Output CMOS 4mA Output Drive 21 15 F7 XTI I Crystal Input (Clock Input) Specific Level Input Pad (see paragraph 2.1) 22 19 E7 VSS_4 Ground 23 21 C8 VDD_4 Supply Voltage 24 22 D7 TESTEN I Test Enable CMOS Input Pad Buffer with pull up 25 24 A7 SDI_ADC I ADC Data Input CMOS Input Pad Buffer 26 25 B6 RESET I System Reset CMOS Input Pad Buffer with pull up 27 26 A5 LRCK_ADC I ADC Left/Right Clock CMOS Output Pad Buffer 28 27 C5 OUT_CLK/ O Buffered Output Clock/ CMOS 4mA Output Drive DATA_REQ Data Request Signal 20 C7 IODATA[0] I/O GPIO Data Line CMOS 4mA Schmitt Trigger 18 E6 IODATA[1] I/O GPIO Data Line Bidir Pad Buffer 16 F6 IODATA[2] I/O GPIO Data Line 14 F8 IODATA[3] I/O GPIO Data Line 37 C3 IODATA[4] I/O GPIO Data Line 39 E3 IODATA[5] I/O GPIO Data Line 41 D2 IODATA[6] I/O GPIO Data Line 43 F1 IODATA[7] I/O GPIO Data Line 35 C2 GPIO_STROBE I/O GPIO Strobe Signal 4 G3 GPSO_REQ O GPSO Request Signal CMOS Output Pad Buffer 28 C6 GPSO_SCKR I GPSO Serial Clock CMOS Input Pad Buffer 33 A2 GPSO_DATA O GPSO Serial Data CMOS Output Pad Buffer Note: In functional mode TESTEN must be connected to VDD.
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