ECE334 Digital Electronics -‐ Fall 2017
Overview This course is an introduction to digital integrated circuits (ICs) and emphasis is placed on the transistor-level aspects of IC design.
Instructor • Dr. Tome Kosteski [email protected] PR371 Office Hours: Thur 1pm – 2pm Textbook CMOS VLSI Design (fourth edition) by N.H. E. Weste and D. Harris, Addison Wesley, 2011 Topics Topics to be covered are from chapters 1-6, 9-10, 12 of the textbook: • CMOS logic design • Layout design • Transistor sizing • Combinational circuit design • Sequential logic • Power dissipation • Crossing clock domains • Memory circuits
Learning Outcomes Upon successful completion of the course students will: 1. Master the fundamental techniques of digital circuit analysis and design in terms of their sizing, noise tolerance and the resistive and capacitive effects on their delay, mostly as applied to static CMOS combinational circuits. 2. Be able to read and design basic digital integrated circuit layout and understand its relationship with key integrated circuit micro-fabrication steps. 3. Understand the topology and function of key memory circuits such as SRAM, DRAM and EEPROM. 4. Master basic analysis and design of sequential digital circuits using flip-flops, both synchronous and asynchronous.
Lectures Refer to Faculty timetable.
Tutorials (weekly) Refer to Faculty timetable Laboratory Information (every two weeks) Handouts relating to the labs will be available on the UofT Portal/Blackboard website for the course under ‘Course Documents’ -> ‘Labs’.
Term tests (tentative) Test 1 October 18, 2017 5 - 6 pm Test 2 November 15, 2017 5 - 6 pm
Grades The final grade composition will be as follows: • Term Test 1 20% • Term Test 2 20% • Final Exam 50% • Laboratory 10% Term tests and the final exam are non-programmable calculators and no aid sheet.
Missed Work File a petition for all missed work.
ECE334 Lecture Content (Approx.) Section Description 1 1.1-‐1.3 Course introduction; MOS Transistors 2 1.4 Transistors, CMOS logic 3 1.4 CMOS logic 4 1.5 CMOS Layout (intro) 5 2.1, 2.2, Ideal MOS transistors, Simple MOS Capacitance 2.3 6 2.3 Detailed MOS Capacitance 7 2.4 Non-‐ideal effects 8 2.5 DC Transfer Characteristics (static CMOS) 9 2.5, 2.6 DC Transfer Characteristics (ratioed logic) 10 3.1, 3.2 CMOS Processing and Layout Design rules 11 3.3 CMOS Processing Technologies 12 Review 13 4.1, 4.2 Delay, transient response 14 4.3.1-‐4.3.3 RC Delay Model, effective resistance 15 notes Transistor equivalency, transistor sizing 16 notes, 4.3 RC delay model, unit delay estimation, inverter chain sizing 17 4.3.4-‐4.3.6 Transient response, Elmore Delay, layout considerations 18 4.4, 4.4.1- Logical effort ‐4.4.3 19 5.1-‐5.3 Power dissipation, dynamic and static power 20 6.1 to Interconnect: wire resistance, capacitance, delay 6.3 21 9.1, 9.2 Digital circuit families (static CMOS, ratioed, pass-‐transistor circuits, CVSL, dynamic circuits) 22 12.1 Memory architecture / organization 23 12.2 SRAM cell operation, cell design and read stability 24 Review 25 12.2 SRAM cell design: read speed, write ability 26 12.2 SRAM: write ability, bit line twisting, column circuitry 27 12.3 DRAM array architecture, basic operation 28 12.3 DRAM cell analysis, read, write, refresh sequences 29 12.4 ROM memories 30 12.4 FLASH memories 31 10.1, 10.2 Sequential Circuit Design, Sequencing static circuits 32 10.2 Synchronous Circuit Design: Max Delay Constraints 33 10.2.3 & Min delay constraints, clock skew 5 34 10.3 Design of latches and flip-‐flops 35 notes Characterizing sequencing element delays, setup and hold times 36 10.6 Synchronizers, metastability 37 10.6 Metastability, clock domains, MTBF