CMOS Gate Propagation Delay

10/7/2019 DIGITAL ELECTRONICS SCHEDULE THIS WEEK SYSTEM DESIGN FALL 2019 Jiwon Choe will be covering my lecture this Wednesday PROF. IRIS BAHAR Introduction to sequential logic OCTOBER 7, 2019 McKenna Cisler will be holding a Verilog tutorial this LECTURE 10: CMOS TRANSIENT BEHAVIOR THURSDAY from 5-7pm in the fishbowl He will be swapping his usual Wednesday hours with Andrew NMOS I-V SUMMARY CMOS INVERTER VTC NMOS off PMOS res Taking those intersection 2.5 Shockley 1st order transistor models NMOS sat points from the load curves, PMOS res we obtain the voltage- 2 transfer characteristic 0 cutoff 1.5 NMOS sat (V) β linear PMOS sat 2 out 1 V NMOS res saturation 0.5 PMOS sat NMOS res 2 PMOS off 0 00.511.522.5 where C is the capacitance per unit area of SiO ox 2 Vin (V) 1 10/7/2019 SWITCHING THRESHOLD MOS STRUCTURE RESISTANCE Define VM to be the point where Vin = Vout (both PMOS and The simplest model assumes the transistor is a switch with an NMOS in saturation since VDS = VGS) infinite “off” resistance and a finite “on” resistance Ron If VM = VDD/2, then this implies symmetric rise/fall behavior for the CMOS gate VGS VT 2 Ron Recall at saturation, ID=(k’/2)(W/L) (VGS-Vth) , S D where k’n= nCox= nox/tox However Ron is nonlinear, time-varying, and dependent on the Setting IDp= -IDn operation point of the transistor 2 2 How can we determine an equivalent (constant and linear) resistance to use instead? , if , · Assuming Vthn=-Vthp EQUIVALENT MOS STRUCTURE MOS STRUCTURE RESISTANCE RESISTANCE 6 Approximate Ron as the resistance 5 3 VDD x105 found during linear operation Req 7 4 4 IDSAT (for VGS = VDD, 6 V = V V /2) 3 where DS DD DD Simple to calculate but limited accuracy 5 2 2 4 Cox W VDSAT IDSAT (VDD VT )VDSAT Instead use the average value of the 1 3 2 L 2 2 resistances, R , at the end-points of 0 eq so, the transition (i.e., V and V /2) 00.511.522.5 1 DD DD 0 3 L VDD Req 2 0.511.522.5 ID 2Cox W VDSAT DD T DSAT 1 VGS = VDD (V V )V R (R (t ) R (t )) 2 VDD (V) eq 2 on 1 on 2 L L Rmid R , R 1 VDD VDD / 2 eqNMOS eqPMOS nW pW 2 I I DSAT DSAT R0 3 VDD VDS Req is essentially independent of VDD as long as VDD >> VT+VDSAT/2 4 I DSAT VDD/2 VDD 2 10/7/2019 CMOS INVERTER: DYNAMIC BEHAVIOR SOURCES OF CAPACITANCE Vout Vin VDD Vout2 Transient, or dynamic, CL response determines the maximum speed at which a CG4 Rp M2 device can be operated. M4 CDB2 V V V out out2 in C GD12 Cw Vout = 0 CDB1 t = f(R , C ) M M3 pHL n L 1 C CL G3 Rn intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances Vin = V DD wiring (interconnect) capacitance SOURCES OF CAPACITANCE DELAY DEFINITIONS Vout Vin V V V out2 Vin in out CL Propagation delay input 50% tp = (tpHL + tpLH)/2 CG4 waveform M2 M4 CDB2 t Vout Vout2 Vin tpHL tpLH C L Vout CDB1 M M3 90% 1 C G3 output signal slopes waveform 50% 10% t CL ≈ CDB2+CDB1+CG4+CG3 tf tr 3 10/7/2019 INVERTER PROPAGATION DELAY MODELING PROPAGATION DELAY Propagation delay proportional to time-constant of network formed by ON resistor and the load capacitance. Model circuit as first-order RC network v (t) = (1 – e–t/)V VDD t = f(R , C ) out in pHL n L R where = RC vout Rp 3 C Time to reach 50% point is 4 vin t = ln(2) = 0.69 Vout = 0 Time to reach 90% point is CL Rn Want to have equal rise/fall delays t = ln(9) = 2.2 make Rn=Rp t p (t pHL t pLH ) / 2 0.69CL (Rn Rp ) / 2 Vin = V DD SWITCH DELAY MODEL INPUT PATTERN EFFECTS ON DELAY A Req Delay is dependent on the pattern of A R R Rp p p Rp Rp inputs B A B A B st Rp 1 order approximation of delay: R Rn A p C CL ≈ R int tp 0.69 Reff CL n CL A A R A n CL Rn A R R Cint Reff depends on the input pattern R n n CL n C B int A B B INVERTER NOR NAND 4 10/7/2019 INPUT PATTERN EFFECTS ON DELAY TRANSISTOR SIZING 01 transition on output: 2 possibilities How should NMOS and PMOS devices be sized relative to an one input goes low: what is Reff ? inverter with equal rise/fall times? Rp Rp delay is 0.69 Rp CL A B both inputs go low: what is R ? Rp Rp Rp eff 11 2 A B B R delay is 0.69 Rp/2 CL since 2 p-resistors on in parallel n CL A 10 transition on output: 1 possibility R 2 Rp C n CL int both inputs go high 2 R A n C A int delay is 0.69 2R C B n L 2 Rn Rn Rn C Cint 1 L B A B 1 tp ≈ 0.69 Reff CL Adding transistors in series (without sizing) slows down the circuit TRANSISTOR SIZING A COMPLEX GATE TRANSISTOR SIZING A COMPLEX GATE B 4 8 B 3 6 A 2 4 • Size the shortest A 1.5 3 • Alternate sizing: C 4 8 path first C 3 6 size the longest • Numbers in black path first D 2 4 are relative to an D 3 6 inverter • Numbers in green A 2 A 2 are relative to a D D 1 minimum width 1 BC22device BC22 OUT = !(D + A • (B + C)) OUT = !(D + A • (B + C)) 5.

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