Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading ∗
Real-World Design and Evaluation of Compiler-Managed GPU Redundant Multithreading ∗ Jack Wadden Alexander Lyashevsky§ Sudhanva Gurumurthi† Vilas Sridharan‡ Kevin Skadron University of Virginia, Charlottesville, Virginia, USA †AMD Research, Advanced Micro Devices, Inc., Boxborough, MA, USA §AMD Research, Advanced Micro Devices, Inc., Sunnyvale, CA, USA ‡ RAS Architecture, Advanced Micro Devices, Inc., Boxborough, MA, USA {wadden,skadron}@virginia.edu {Alexander.Lyashevsky,Sudhanva.Gurumurthi,Vilas.Sridharan}@amd.com Abstract Structure Size Estimated ECC Overhead Reliability for general purpose processing on the GPU Local data share 64 kB 14 kB (GPGPU) is becoming a weak link in the construction of re- Vector register file 256 kB 56 kB liable supercomputer systems. Because hardware protection Scalar register file 8 kB 1.75 kB is expensive to develop, requires dedicated on-chip resources, R/W L1 cache 16 kB 343.75 B and is not portable across different architectures, the efficiency Table 1: Reported sizes of structures in an AMD Graphics Core of software solutions such as redundant multithreading (RMT) Next compute unit [4] and estimated costs of SEC-DED ECC must be explored. assuming cache-line and register granularity protections. This paper presents a real-world design and evaluation of automatic software RMT on GPU hardware. We first describe These capabilities typically are provided by hardware. Such a compiler pass that automatically converts GPGPU kernels hardware support can manifest on large storage structures as into redundantly threaded versions. We then perform detailed parity or error-correction codes (ECC), or on pipeline logic power and performance evaluations of three RMT algorithms, via radiation hardening [19], residue execution [16], and other each of which provides fault coverage to a set of structures techniques.
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