MODULE-5 : Coprocessor and advance microprocessors: 8087 architecture, instruction set, programming with 8087, comparison of 8086 with advance microprocessors like 80386,80486, Pentium processors, Core-2 etc. 8087-The numeric or arithmetic coprocessor: This is a special-purpose microprocessor, which executes arithmetic and transcendental operations. The microprocessor executes the normal instruction set, and the coprocessor executes only the coprocessor instructions. The coprocessor instructions are actually escape (ESC) instructions. These instructions are used by the microprocessor to generate a memory address for the coprocessor to execute a coprocessor instruction. The 80486DX–Core2 microprocessors contain their own internal and fully compatible versions of the 80387. With other family members, the coprocessor is an external integrated circuit that parallels most of the connections on the microprocessor. Both the microprocessor and coprocessor will execute their respective instructions simultaneously or concurrently. Internal Structure of the 8087: Figure 1 shows the internal structure of the arithmetic coprocessor. It has two major sections: the control unit and the numeric execution unit. The control unit interfaces the coprocessor to the microprocessor-system data bus. Both the devices monitor the instruction stream. If the instruction is an ESCape (coprocessor) instruction, the coprocessor executes it; if not, the microprocessor executes it. The numeric execution unit (NEU) is responsible for executing all coprocessor instructions. The NEU has an eight-register stack that holds operands for arithmetic instructions and the results of arithmetic instructions. Instructions either address data in specific stack data registers or use a push-and-pop mechanism to store and retrieve data on the top of the stack. Other registers in the NEU are status, control, tag, and exception pointers. A few instructions transfer data between the coprocessor and the AX register in the microprocessor. The stack within the coprocessor contains eight registers that are each 80 bits wide. These stack registers always contain an 80-bit extended-precision floating-point number. The only time that data appear as any other form is when they reside in the memory system. The coprocessor converts from signed integer, BCD, single-precision, or double-precision form as the data are moved between the memory and the coprocessor register stack. Figure 1 Internal Structure of the 8087 STATUS REGISTER: The status register (Fig ) reflects the overall operation of the coprocessor. The status register is accessed by executing the instruction (FSTSW), which stores the contents of the status register into a word of memory. B-busy bit indicates that the coprocessor is busy executing a task. Busy is tested by examining the status register or by using the FWAIT instruction. C0–C3 The condition code bits indicate conditions about the coprocessor. these bits have different meanings for different instructions. The top of the stack is denoted as ST.For eg, for FCOM instruction,0000 means ST>operand. ST: top-of-stack (ST) bit indicates the current register addressed as the top-of-the stack (ST). It is normally register T(0). ES The error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is set. In the 8087 coprocessor, the error summary also caused a coprocessor interrupt. PE The precision error indicates that the result or operands exceed the selected precision. UE-underflow error indicates a nonzero result that is too small to represent with the current precision selected by control word. OE-overflow error indicates a result that is too large to be represented. If this error is masked, the coprocessor generates infinity for an overflow error. ZE - zero error indicates the divisor was zero while the dividend is a noninfinity or nonzero number. DE - denormalized error indicates that at least one of the operands is denormalized. IE -invalid error indicates a stack overflow or underflow, indeterminate form (0 ÷ 0, +∞, -∞, etc.),or the use of NAN(not a number) as an operand and indicates errors which are produced by taking the square root of a negativenumber, etc. TEST instruction is used to test individual bits of the status register.SAHF instruction is used to transfer the leftmost 8 bits of the status register into the microprocessor’s flag register. CONTROL REGISTER: Control Register. The control register is shown in above Figure. The control register selects the precision, rounding control, and infinity control. It also masks and unmasks the exception bits that correspond to the rightmost 6 bits of the status register. The FLDCW instruction is used to load a value into the control register.Following is a description of each bit or grouping of bits found in the control register: IC Infinity control selects either affine or projective infinity. Affine allows positive and negative infinity; projective assumes infinity is unsigned. RC Rounding control determines the type of rounding, as defined in Figure. PC The precision control sets the precision of the result, as defined in Figure. Exception Determine whether the error indicated by the exception affects the error bit in masks the status register. If a logic 1 is placed in one of the exception control bits, the corresponding status register bit is masked off. TAG REGISTER. The tag register indicates the contents of each location in the coprocessor stack.Figure illustrates the tag register and the status indicated by each tag. The tag indicates whether a register is valid; zero; invalid or infinity; or empty. The only way that a program can view the tag register is by storing the coprocessor environment using the FSAVE, or FRSTOR instructions. Each of these instructions stores the tag register along with other coprocessor data. INSTRUCTION SET: The arithmetic coprocessor executes over 68 different instructions. Whenever a coprocessor instruction references memory, the microprocessor automatically generates the memory address for the instruction. The coprocessor uses the data bus for data transfers during coprocessor instructions and the microprocessor uses it during normal instructions.The coprocessor uses the microprocessor memory-addressing modes. Each time that the assembler encounters a coprocessor mnemonic opcode, it converts it into a machine language ESC instruction. The ESC instruction represents an opcode to the coprocessor. Data Transfer Instructions There are three basic data transfers: floating-point, signed integer, and BCD. Data appears in the signed integer or BCD form is in the memory. Inside the coprocessor, data are always stored as an 80-bit extended-precision floating-point number. Floating-Point Data Transfers. There are four floating-point data transfer instructions. 1. FLD (load real): loads floating-point memory data to the top of the internal stack ST (stack top).Data is stored on the top of the stack ,then the stack pointer decremented by 1. Data loaded to the top of the stack are from any memory location or from another coprocessor register. Example 1: FLD ST(2) –copies the contents of register 2 to the stack top ST. The top of the stack is register 0 when the coprocessor is reset or initialized. Example 2: FLD DATA7- copies the contents of memory location DATA 7 to the top of the stack. The size of the data is determined by the assembler through the directives DD or REAL4 for single-recision,DQ or REAL 8 for double-precision, and DT or REAL10 for extended temporary-precision. 2.FST (store real): stores a copy of the top of the stack into the memory location or coprocessor register indicated by the operand. At the time of storage, the internal, extended temporary-precision floating-point number is rounded to the size of the floating-point number indicated by the control register. 3.FSTP (floating-point store and pop): stores a copy of the top of the stack into memory or any register, and then pops the data from the top of the stack. 4.FXCH (exchange): The FXCH instruction exchanges the register indicated by the operand with the top of the stack. For example, the FXCH ST(2) instruction exchanges the top of the stack with register 2. A new instruction is added to the Pentium Pro through Core2 called a conditional floating-point move instruction that uses the opcode FCMOV (For eg,FCMOVB-move if below,Conditional move)with a floating- point condition. Integer Data Transfer Instructions: There are three integer data transfer instructions FILD (load integer), FIST (store integer), and FISTP (store integer and pop). These three instructions function as did FLD, FST, and FSTP, except that the data transferred are integer data. The coprocessor automatically converts the internal extended temporary-precision floating-point data to integer data. The size of the data is determined by the way that the label is defined with DW, DD, or DQ in the assembly language program. BCD Data Transfer Instructions: There are two instructions to load or store BCD signed-integer data. FBLD- loads the top of the stack with BCD memory data, FBSTP- stores the top of the stack and does a pop. Arithmetic Instructions-addressing modes: Arithmetic instructions include addition, subtraction, multiplication, division, and calculating square roots. The arithmetic-related instructions are scaling, rounding,absolute value, and changing the sign. Table shows the basic addressing modes allowed for the arithmetic operations. Each addressing mode is shown with an example using the FADD (real addition) instruction. All arithmetic operations are floating-point, except some cases in which memory data are referenced as an operand. Stack addressing uses the top of the stack as the source operand and the next to the top of the stack as the destination operand. Afterward, a pop removes the source data from the stack and only the result in the destination register remains at the top of the stack.this mode of instructions doesn’t have operand. For eg, FADD or FSUB. The FADD instruction adds ST to ST(1) and stores the answer at the top of the stack ST; it also removes the original two data from the stack by popping.