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Home , Control register, Coprocessor, Stack register

MODULE-5 : and advance : 8087 architecture, instruction set, programming with 8087, comparison of 8086 with advance microprocessors like 80386,80486, Pentium processors, Core-2 etc.

8087-The numeric or arithmetic coprocessor: This is a special-purpose , which executes arithmetic and transcendental operations. The microprocessor executes the normal instruction set, and the coprocessor executes only the coprocessor instructions. The coprocessor instructions are actually escape (ESC) instructions. These instructions are used by the microprocessor to generate a memory address for the coprocessor to execute a coprocessor instruction. The 80486DX–Core2 microprocessors contain their own internal and fully compatible versions of the 80387. With other family members, the coprocessor is an external that parallels most of the connections on the microprocessor. Both the microprocessor and coprocessor will execute their respective instructions simultaneously or concurrently. Internal Structure of the 8087: Figure 1 shows the internal structure of the arithmetic coprocessor. It has two major sections: the and the numeric . The control unit interfaces the coprocessor to the microprocessor-system data . Both the devices monitor the instruction stream. If the instruction is an ESCape (coprocessor) instruction, the coprocessor executes it; if not, the microprocessor executes it.  The numeric execution unit (NEU) is responsible for executing all coprocessor instructions. The NEU has an eight-register stack that holds operands for arithmetic instructions and the results of arithmetic instructions.  Instructions either address data in specific stack data registers or use a push-and-pop mechanism to store and retrieve data on the top of the stack. Other registers in the NEU are status, control, tag, and exception pointers.  A few instructions transfer data between the coprocessor and the AX register in the microprocessor. The stack within the coprocessor contains eight registers that are each 80 bits wide. These stack registers always contain an 80-bit extended-precision floating-point number.  The only time that data appear as any other form is when they reside in the memory system. The coprocessor converts from signed integer, BCD, single-precision, or double-precision form as the data are moved between the memory and the coprocessor register stack.

Figure 1 Internal Structure of the 8087 : The status register (Fig ) reflects the overall operation of the coprocessor. The status register is accessed by executing the instruction (FSTSW), which stores the contents of the status register into a word of memory.

B-busy bit indicates that the coprocessor is busy executing a task. Busy is tested by examining the status register or by using the FWAIT instruction. C0–C3 The condition code bits indicate conditions about the coprocessor. these bits have different meanings for different instructions. The top of the stack is denoted as ST.For eg, for FCOM instruction,0000 means ST>operand. ST: top-of-stack (ST) bit indicates the current register addressed as the top-of-the stack (ST). It is normally register T(0). ES The error summary bit is set if any unmasked error bit (PE, UE, OE, ZE, DE, or IE) is set. In the 8087 coprocessor, the error summary also caused a coprocessor . PE The precision error indicates that the result or operands exceed the selected precision. UE-underflow error indicates a nonzero result that is too small to represent with the current precision selected by control word. OE-overflow error indicates a result that is too large to be represented. If this error is masked, the coprocessor generates infinity for an overflow error. ZE - zero error indicates the divisor was zero while the dividend is a noninfinity or nonzero number. DE - denormalized error indicates that at least one of the operands is denormalized. IE -invalid error indicates a stack overflow or underflow, indeterminate form (0 ÷ 0, +∞, -∞, etc.),or the use of NAN(not a number) as an operand and indicates errors which are produced by taking the square root of a negativenumber, etc.

TEST instruction is used to test individual bits of the status register.SAHF instruction is used to transfer the leftmost 8 bits of the status register into the microprocessor’s flag register. :

Control Register. The control register is shown in above Figure. The control register selects the precision, rounding control, and infinity control. It also masks and unmasks the exception bits that correspond to the rightmost 6 bits of the status register. The FLDCW instruction is used to load a value into the control register.Following is a description of each bit or grouping of bits found in the control register: IC Infinity control selects either affine or projective infinity. Affine allows positive and negative infinity; projective assumes infinity is unsigned. RC Rounding control determines the type of rounding, as defined in Figure. PC The precision control sets the precision of the result, as defined in Figure. Exception Determine whether the error indicated by the exception affects the error bit in masks the status register. If a logic 1 is placed in one of the exception control bits, the corresponding status register bit is masked off. TAG REGISTER. The tag register indicates the contents of each location in the coprocessor stack.Figure illustrates the tag register and the status indicated by each tag. The tag indicates whether a register is valid; zero; invalid or infinity; or empty. The only way that a program can view the tag register is by storing the coprocessor environment using the FSAVE, or FRSTOR instructions. Each of these instructions stores the tag register along with other coprocessor data.

INSTRUCTION SET: The arithmetic coprocessor executes over 68 different instructions. Whenever a coprocessor instruction references memory, the microprocessor automatically generates the memory address for the instruction. The coprocessor uses the data bus for data transfers during coprocessor instructions and the microprocessor uses it during normal instructions.The coprocessor uses the microprocessor memory-addressing modes. Each time that the assembler encounters a coprocessor mnemonic opcode, it converts it into a machine language ESC instruction. The ESC instruction represents an opcode to the coprocessor. Data Transfer Instructions  There are three basic data transfers: floating-point, signed integer, and BCD.  Data appears in the signed integer or BCD form is in the memory.  Inside the coprocessor, data are always stored as an 80-bit extended-precision floating-point number. Floating-Point Data Transfers. There are four floating-point data transfer instructions. 1. FLD (load real):  loads floating-point memory data to the top of the internal stack ST (stack top).Data is stored on the top of the stack ,then the stack pointer decremented by 1.  Data loaded to the top of the stack are from any memory location or from another coprocessor register.  Example 1: FLD ST(2) –copies the contents of register 2 to the stack top ST. The top of the stack is register 0 when the coprocessor is reset or initialized.  Example 2: FLD DATA7- copies the contents of memory location DATA 7 to the top of the stack. The size of the data is determined by the assembler through the directives DD or REAL4 for single-recision,DQ or REAL 8 for double-precision, and DT or REAL10 for extended temporary-precision. 2.FST (store real): stores a copy of the top of the stack into the memory location or coprocessor register indicated by the operand. At the time of storage, the internal, extended temporary-precision floating-point number is rounded to the size of the floating-point number indicated by the control register. 3.FSTP (floating-point store and pop): stores a copy of the top of the stack into memory or any register, and then pops the data from the top of the stack. 4.FXCH (exchange): The FXCH instruction exchanges the register indicated by the operand with the top of the stack. For example, the FXCH ST(2) instruction exchanges the top of the stack with register 2.

A new instruction is added to the Pentium Pro through Core2 called a conditional floating-point move instruction that uses the opcode FCMOV (For eg,FCMOVB-move if below,Conditional move)with a floating- point condition.

Integer Data Transfer Instructions: There are three integer data transfer instructions FILD (load integer), FIST (store integer), and FISTP (store integer and pop). These three instructions function as did FLD, FST, and FSTP, except that the data transferred are integer data. The coprocessor automatically converts the internal extended temporary-precision floating-point data to integer data. The size of the data is determined by the way that the label is defined with DW, DD, or DQ in the assembly language program.

BCD Data Transfer Instructions: There are two instructions to load or store BCD signed-integer data. FBLD- loads the top of the stack with BCD memory data, FBSTP- stores the top of the stack and does a pop. Arithmetic Instructions-addressing modes: Arithmetic instructions include addition, subtraction, multiplication, division, and calculating square roots. The arithmetic-related instructions are scaling, rounding,absolute value, and changing the sign. Table shows the basic addressing modes allowed for the arithmetic operations.

Each is shown with an example using the FADD (real addition) instruction. All arithmetic operations are floating-point, except some cases in which memory data are referenced as an operand.  Stack addressing uses the top of the stack as the source operand and the next to the top of the stack as the destination operand. Afterward, a pop removes the source data from the stack and only the result in the destination register remains at the top of the stack.this mode of instructions doesn’t have operand.  For eg, FADD or FSUB. The FADD instruction adds ST to ST(1) and stores the answer at the top of the stack ST; it also removes the original two data from the stack by popping. Note carefully that FSUB subtracts ST from ST(1) and leaves the difference at ST. Therefore, a reverse subtraction (FSUBR) subtracts ST(1) from ST and leaves the difference at ST. The FDIVR instruction divides ST(1) into ST.  The register-addressing mode uses ST for the top of the stack and ST(n) for another location, where n is the register number.In this,one operand must be ST and the other is ST(n), where n is a 0–7. For many instructions, either ST or ST(n) can be the destination. Another example of register-addressing is FADD ST(1),ST where the contents of ST are added to ST(1) and the result is placed in ST(1).  Memory addressing always uses the top of the stack as the destination because the coprocessor is a stack- oriented machine. For eg, the FADD DATA instruction adds the real number contents of memory location DATA to the top of the stack.

Arithmetic Operations: FADDP: The letter P specifies a register pop after the operation (FADDP compared to FADD).  The letter R in an opcode (subtraction and division only-eg FSUBR,FDIVR) indicates reverse mode. The reverse mode is useful for memory data because memory data normally subtract from the top of the stack. A reversed subtract instruction subtracts the top of the stack from memory and stores the result in the top of the stack. For example, if the top of the stack contains a 10 and memory location DATAl contains a 1, the FSUB DATA1 instruction results in a +9 on the stack top, and the FSUBR instruction results in a –9. Another example is FSUBR ST,ST(1), which will subtract ST from ST(1) and store the result on ST. A variant is FSUBR ST(1),ST, which will subtract ST(1) from ST and store the result on ST(1).  The letter I as a second letter in an opcode indicates that the memory operand is an integer. For example, the FADD DATA instruction is a floating-point addition, while the FIADD DATA is an integer addition that adds the integer at memory location DATA to the floatingpoint number at the top of the stack. The same rules apply to FADD, FSUB, FMUL, and FDIV instructions. Arithmetic-Related Operations: Other operations that are arithmetic in nature include FSQRT (square root), FSCALE (scale a number), FPREM/FPREM1 (find partial remainder), FRNDINT (round to integer), FXTRACT (extract exponent and significand), FABS (find absolute value), and FCHG (change sign). These instructions and the functions that they perform follow: Finds the square root of the ST(top of the stack)and the result is in ST only.An invalid error occurs for FSQRT a negative number.So, the IE bit of the status register should be tested whenever an invalid result can occur.The IE bit c an be tested by loading the status register to register. Adds the contents of ST(1) (interpreted as an integer) to the exponent at the ST. FSCALE multiplies or FSCALE divides rapidly by powers of two.The value in ST(1)must be between 2–15 and 2+15. Not available in 8087--Performs modulo division of ST by ST(1). The resultant remainder is found in FPREM/FPR the top of the stack and has the same sign as the original dividend. Note that a modulo division results EM1 in a remainder without a quotient. Note also that FPREM is supported for the 8086 and 80287,and FPREM1 should be used in newer . FRNDINT Rounds the top of the stack to an integer. Decomposes the number at the top of the stack into two separate parts that represent the value of the unbiased exponent and the value of the significand. The extracted significand is found at the top of the FXTRACT stack and the unbiased exponent at ST(1). This instruction is often used to convert a floating-point number into a form that can be printed as a mixed number. FABS Changes the sign of the the top of the stack to positive. FCHS Changes the sign from positive to negative or negative to positive

Comparison Instructions  These instructions examine data at the top of the stack in relation to another element and return the result of the comparison in the status register condition code bits C3–C0. FCOM Compares the floating-point data at the top of the stack with an operand, which may be any register (floating-point or any memory operand. If the operand is not coded with the instruction, the next stack element compare) ST(1) is compared with the stack top ST. FCOMP (floating-point compare with a pop) /FCOMPP (floating- Both instructions perform as FCOM, but they also pop one or two data from the stack. point compare with two pops) FICOM/FICOMP(integ The top of the stack is compared with the integer stored at a memory operand. In addition to er compare & POP) the compare, FICOMP also pops the top of the stack. Tests the contents of the top of the stack against a zero. The result of the comparison is FTST (Test) coded in the status register condition code bits.Also, refer to Table 14–3 for a way of using SAHF and the conditional jump instruction with FTST. Examines the stack top and modifies the condition code bits to indicate whether the contents FXAM (Examine) are positive, negative, normalized, and so on. New to the Pentium Pro through the Pentium 4, this instruction compares in exactly the same FCOMI/FUCOMI manner as the FCOM instruction, with one additional feature: It moves the floating-point flags into the flag register. Also available is the unordered compare or FUCOMI.

Transcendental Operations: The transcendental instructions include FPTAN (partial tangent), FPATAN (partial arctangent),FSIN (sine), FCOS (cosine), FSINCOS (sine and cosine), F2XM1 (2X - 1), FYL2X (Y log2 X),and FYL2XP1 [Y log2 (X + 1)]. A list of these operations follows with a description of each transcendental operation:

Finds the partial tangent of Y/X = tan θ. The value of θ is at the ST. 0≤ θ ≤ n/4 radians for the 8087 and 80287, and 0≤ θ ≤ 263 for the 80387, 80486/7, and Pentium–Core2. The result is a ratio found as ST = X and FPTAN ST(1) = Y. If the value is outside the allowable range, an invalid error occurs, as indicated by the status register IE bit. Also note that ST(7) must be empty for this instruction to function properly. Finds the partial arctangent as θ = ARCTAN X/Y. The value of X is at ST and Y is at ST(1). The values FPATAN of X and Y must be as follows:0 ≤Y < X <∞. The instruction pops the stack and leaves θ in radians at the top of the stack. Finds the function 2X - 1. The value of X is taken from the ST and the result is at ST ,where -1≤ X ≤ 1. To obtain 2X add one to the result at ST.The F2XM1 instruction is used to derive the functions like F2XM1 Y Y Y Y Y Y 1. 10 (equation:2 × log2 10) 2. ε (equation: 2 × log2 ε) 3. X (equation: 2 × log2 X) Note that the constants log2 10 and log2 ε are built in as standard values for the coprocessor. FSIN/ (Not available in 8087)Finds the sine or cosine of the argument located in ST expressed in radians(360° = FCOS 2πradians), with the result found in ST. The values of ST must be less than 263. (Not available in 8087)Finds the sine and cosine of ST, expressed in radians, and results stored in ST = sine FSINCOS and ST(1) = cosine. As with FSIN or FCOS, the initial value of ST must be less than 263.

Finds Y log2 X. where 0≤ X ≤ ∞ & -∞≤ Y ≤ ∞ The value X is taken from ST, and Y is taken from ST(1). FYL2X The result is found at ST after a pop. -1 A logarithm with any positive base (b) is found by the equation LOGb X =(LOG2 b) X LOG2 X. Finds Y log (X + 1). The value of X is taken from ST and Y is taken from ST(1), FYL2P1 2 where 0≤ X ≤ 1-(SQRT(2)/2) & -∞≤ Y ≤ ∞ . The result is found at ST after a pop.

Constant Operations: The coprocessor instruction set includes opcodes that return constants to the ST.A list of these instructions shown inTable

Coprocessor Control Instructions: The coprocessor has control instructions for initialization, exception handling, and task switching. The control instructions have two forms. For example, FINIT initializes the coprocessor, as does FNINIT. The difference is that FNINIT does not cause any wait states, while FINIT does cause waits. The microprocessor waits for the FINIT instruction by testing the BUSY pin on the coprocessor. All control instructions have these two forms. Following is a list of each control instruction with its function: FINIT/FNI Performs a reset (initialize) operation on the arithmetic coprocessor .and uses extended-precision when NIT reset or initialized. It also sets register 0 as the top of the stack. Changes the addressing mode of the coprocessor to the protected addressing mode. This mode is used FSETPM when the microprocessor is also operated in the . FLDCW Loads the control register with the word addressed by the operand. FSTCW Stores the control register into the word-sized memory operand. Copies the contents of the control register to the AX register. This instruction is not available to the 8087 FSTSW AX coprocessor. FCLEX Clears the error flags in the status register and also the busy flag. FSAVE Writes the entire state of the machine to memory. Restores the state of the machine from memory. This instruction is used to restore the information saved FRSTOR by FSAVE. FSTENV Stores the environment of the coprocessor FLDENV Reloads the environment saved by FSTENV. FINCSP Increments the stack pointer. FDECSP Decrements the stack pointer. Frees a register by changing the destination register’s tag to empty. It does not affect the contents of the FFREE register. FNOP Floating-point coprocessor NOP. Causes the microprocessor to wait for the coprocessor to finish an operation. FWAIT should be used FWAIT before the microprocessor accesses memory data that are affected by the coprocessor.

8087 Programs: 1. Finding the Resonant Frequency the resonant frequency of an LC circuit is given by f = 1/ 2π SQRT(LC).This example uses L1 for the inductance L, C1 for the capacitor C, and RES for the resultant resonant frequency.

RES DD ? ;resonant frequency L1 DD 0.0001 ;1 mH inductor C1 DD 47E–6 ;47 μF capacitor

FR PROC NEAR FLD L1 :get L FMUL C1 ;form LC FSQRT ;form square root of LC FLDPI ;get pi FADD ST,ST(0) ;form 2 pi FMUL ;form 2 pi square root LC FLD1 FDIVR ;form reciprocal FSTP RES RET FR ENDP

2.Finding area of circle A=πr2 .model small .data Radius dd 3.4 Area dd ? .code Mov ax,@data Mov ds,ax Finit ;initialise 8087 Fld radius ;load radius in ST Fmul st,st(0) ;square radius Fldpi ;load π to ST Fmul ;multiply ST = ST * ST(1) Fstp area ;save area

Comparison of 8086 with advance microprocessors The 80386 Microprocessor • The 80386 microprocessor is an enhanced version of the 80286 microprocessor. • it includes . 80386 also includes 32-bit extended registers and a 32-bit address and data bus. • 80386 has a physical memory size of 4GBytes(232=4GB) and operates in the pipelined mode. • 80386 operates in both the real and protected modes. → In the , the 80386 addresses a 1MByte memory address space and is virtually identical to 8086 → In the protected mode, the 80386 addresses a 4 Gbytes memory space The 80486 Microprocessor • This is an improved version of the 80386 that contains an 8K-byte and 80387 arithmetic co • 80486 executes a few new instructions that control the internal cache memory. • A new feature found in the 80486 is the BIST(builtin self-test) that tests the microprocessor, coprocessor, and cache at reset time. • These new test registers are TR3 (cache data), TR4 (cache status), and TR5 (cache control).

Pentium Microprocessor • This is almost identical to the earlier 80386 and 80486 microprocessors and has 64 bit data bus. • Pentium has been modified internally to contain a dual cache (instruction and data) and a dual integer unit • The Pentium also operates at a higher clock speed of 66 MHz. • Memory access time, without wait states, is only about 18 ns in the 66 MHz Pentium. • The superscalar structure of the Pentium contains three independent processing units: a floating point processor and two integer processing units • Pentium contains a new mode of operation called the System Memory Management (SMM) mode. • Another feature found in the Pentium is the BIST(built-in self-test) that tests the microprocessor, coprocessor, and cache at reset time. • The Pentium allows 4MByte memory pages instead of the 4Kbyte pages.

Pentium Pro Microprocessor • The Pentium Pro is an enhanced version of the Pentium microprocessor that contains → level 1 caches found inside the Pentium → level 2 cache of 256 K or 512K found on most main boards • The Pentium Pro operates using the same 66 MHz bus speed as the Pentium and the 80486. • The only significant software difference between the Pentium Pro and earlier microprocessors is the addition of FCMOV and CMOV instructions. • The only hardware difference between the Pentium Pro and earlier microprocessors is the addition of 2M paging and four extra address lines that allow access to a memory address space of 64G Bytes. • The Pentium uses an internal clock generator to multiply the bus speed by various factors to obtain higher internal Execution speeds.

Pentium II and Pentium Xeon Microprocessors • Released in 1997, the Pentium II was an adaptation of the Pentium Pro aimed at the general public. • The main reason for the change is that the L2 cache found on the main circuit board of the Pentium was not fast enough to function properly with the Pentium II. • On the Pentium system, the L2 cache operates at the system bus speed of 60 MHz or 66 MHz. • New features are MMX (SIMD) support and a doubling of the Level 1 cache.

Pentium III Microprocessor • Released in 1999, the Pentium III microprocessor uses a faster core than the Pentium II, but it is still a P6 or Pentium Pro processor. • Another difference is that the Pentium III is available with clock frequencies of up to 1 GHz. • The slot 1 version contains a 512K cache and the flip-chip version contains a 256K cache. • The speeds are comparable because the cache in the slot 1 version runs at one-half the clock speed, while the cache in the flip-chip version runs at the clock speed. •Both versions use a memory bus speed of 100 MHz, while the Celeron7 uses memory bus clock speed of 66 MHz. Pentium 4 and Core2 Microprocessors • In late 2000, announced its new processor, the Pentium 4. • The most recent version of the Pentium is called the Core2 by Intel. • The Pentium 4 and Core2, like the Pentium Pro through the Pentium III, use the Intel P6 architecture. • The main difference is that → The Pentium 4 is available in speeds to 3.2 GHz and faster and → The chip sets that support the Pentium 4 use the RAMBUS or DDR memory technologies. • Intel has changed the level 1 cache size from 32K to 8K bytes and most recently to 64K.

Memory addressing in advanced microprocessors: 1.Protectedd mode of addressing 2.Paging 1.Introduction to Protected Mode Memory Addressing • Protected-mode memory addressing (80286 and above) allows access to data & programs located above first 1MB of memory & within first 1MB of memory. •Windows operates in this addressing mode.

Differences between real mode & protected mode • Real Mode Memory Addressing is for DOS concept. Protected Mode Memory Addressing is for windows. •In real mode addressing segment register contains segment address. But in protected mode, segment-register contains a selector that selects a descriptor from descriptor table. The difference is that the segment-address is not held in the segment-register. In the protected-mode, the segment starting-address is stored in a descriptor that is selected by the segment-register). • Descriptor describes i. memory-segment's location ii. length iii. access rights iv.some special bits(G,Av,D,L) • Another difference is that the offset-address can be a 32-bit number instead of a 16-bit number in the 80386 and above

1.1.Selectors & Descriptors • Selector(located in the segment-register) selects one of 8192(descriptors from one of 2 tables of descriptors. • Descriptor describes the location, length and access rights of the segment of memory.

• There are 2 descriptor-tables: 1) Global descriptor table (GDT) –> T1 =0 2) Local descriptors table.(LDT) --> T1 =1 • Global-descriptors contain segment-definitions that apply to all programs & also known as System descriptor •Local-descriptors are usually unique to an application also known as application descriptor. •Each descriptor-table contains 8192 descriptors (13bits for selector, so 213=8192 ), so a total of 8192 in GDT +8192 in LDT =16384 descriptors are available to an application at any time. •since a segment can be up to 4GB in 80386 above (232=4GB), an application can access 16384*4GB = 64TB

RPL (Request Privilege Level) •This requests the access privilege level of memory segment.Privilege levels are used in multiuser environment. •2 bits are allotted for RPL.if it is 00 then highest privilege level, if it is 11 then lowest privilege level.windows doesn’t use privilege levels 01,10

1.2.Descriptors: • A descriptor is of 64 bits (8Bytes) and it contains 1) Base-address which is starting-address of memory-segment 2) limit address which is last offset-address found in a segment 3) Access rights byte defines how the memory-segment is accessed via a program. • For 80286 microprocessor,the descriptor has(refer fig) i. the base-address(Bo-B23) is a 24-bit address, so segments begin at any location in its 224=24220=16MB of memory. ii. the limit-address(Lo-L15) is a 16-bit address, For example, if a segment begins at memory location F00000H(which is 24 bit base address) and the limit is 00FFH(which is of 16 bit) then segment ending location = F00000H + __ 00FFH. F000FFH

• For 80386 microprocessor,the descriptor has(refer fig) i. the base-address(Bo-B31) is a 32-bit address, so segments begin at any location in its 232=22230=4GB of memory. ii. the limit-address(Lo-L19) is a 20-bit address, For example, if a segment begins at memory location F0000000H(which is 32 bit base address) and the limit is 00FFFH(which is of 20 bit) then segment ending location = F0000000H + __ 00FFFH. F0000FFFH

• In 80386, if G(granularity)=0, the limit specifies a segment-limit of 00000H to FFFFFH(because limit is of 20 bits.so starting is 00000H & ending is FFFFFH) If G=1, the value of the limit is multiplied by 4KB. • In the 64-bit descriptor, if L=1, 64-bit address in a Pentium4 with 64-bit extensions is selected. if L=0, 32-bit compatibility mode is selected • The AV bit is used by some operating-systems to indicate that the segment is available(AV=1) or not available(AV=0). • D bit indicates how 80386 instructions access register & memory-data in protected- or real-mode. If D=0, the instructions are 16-bit instructions, compatible with the 8086 microprocessor. (This means that the instructions use 16-bit offset addresses and 16-bit register by default). If D=1, the instructions are 32-bit instructions. •In 64 bit P4,there is no segment base & limit addresses.descriptor has only access right bytes and G,D,L,AV bit.

1.3.Access Rights Byte • This controls access to the protected-mode segment. This byte describes how the segment functions in the system. • If the segment is a data-segment, the direction of growth is specified. If the segment grows beyond its limit, the operating-system program is interrupt to indicate a general protection-fault. • The RPL(request privilege level) requests the access privilege-level of a memory-segment. If the RPL is higher than the privilege-level set by the access rights byte, access is granted.

Figure :The access rights byte for the 80286 descriptor Example: For eg, let DS=0008h 1. If it is real mode addressing this DS content indicates the starting of segment address. 2. In protected mode it is viewed as selector,T1,RPL format (Refer the selector diagram ) DS=0008H= 0000 0000 0000 1000,by comparing with standard format RPL = 00(highest PL), T1=0(GDT),remaning 13bits are selector. 3.From the following figure descriptor content is 0000 9210 0000 00FF. 4. By comparing this with standard structure of 80386 descriptor table(refer descriptor fig) Base address B0-B31= 00100000 Limit L0-L19 = 000FF Ending address = 001000FF 5.access right bytes = 92 H=1001 0010

Figure: Using DS register to select a descriptor from the global descriptor table

2.Memory Paging •Paging is one of the memory management technique used for multitasking operating system. •Memory-paging mechanism allows any physical memory-location to be assigned to any linear-address. •80386 & above uses memory paging. The linear-address is defined as the address generated by a program The physical-address is the actual memory-location accessed by a program. •paging allows linear address is translated to physical address and allows relocation.

Paging Registers • Memory-paging is accomplished through control-registers CR0 and CR3. • The paging-unit is controlled by the contents of the control-registers. • CR0: 1. The leftmost bit(PG) position of CR0 selects paging when placed at a logic 1 level.If PG bit is cleared(0), linear-address generated by program becomes physical-address used to access memory.If PG bit is set(1), linear-address is converted to a physical-address through paging-mechanism. 2. CD-Cache disable –Enable/disable memory cache 3. NW – not write through- Enable / disable write through cache 4. AM-allignment mask- enable AC flag 5. WP- write protect-detemines whether CPU can write 6. NE-Numeric error-enable internal floating point error 7. ET – Extension type-specify math coprocessor 8. TS-task 9. EM-Emulation-set / clear floating point unit 10. MP-monitor coprocessor 11. PE-protected mode enable •CR3: This contains page directory page address,PCD&PWT bits.The page directory base-address locates the directory for the page translation-unit. • If PCD (page cache disable)is set(1),then it allows the external hardware to control the level 2 cache memory. •Page write through(PWT)-this bit appears on PWT pin during bus cycles that are not paged to control the write through cache in the system. •Page directory base address:locates the directory for the page translation unit.This address locates the page directory of 4KB at anywhere in the memory.This page directory contains 1024 directory entries of 4KB each.Each page directory entry addresses a that contains 1024 entries.

NOTE: draw the diagram of only CR0 and CR3.

Linear address format:. • The linear address is broken into 3 sections: 1) Page directory enrty. 2) Page table entry 3) Offset part selects a byte in the 4KB memory-page

Figure: The format for the linear address

• Page directory enrty: The bits 22-31adresses an entry in the page directory.So,totally 210=1024 page directory entries are there.For linear address 00000000-003FFFFF,the first page directory is used.Each page directory entry represents 4MB section of memory.(ie.page directory 10 bits& page table 10 bits,so totally 222=4MB). • Page table: Page table is selected by page directory.Page table is addressed by 10 bits(bit 12-21 in fig).So,totall 210=1024 pages.This means that address 00000000-00000FFF represents page directory 0,page table entry 0 which is of 4KB. • Offset: This offset part selects a byte from the page table size of 4KB.This offset part of linear address is (Bit 0-1)ie.212=4KB. Translation look aside buffer; •This is a special cache memory holds 32 most recent page translation address in 80486.So,if the same memory area is again used,then access to the page directory and the page table is not required.because TLB is having last 32 entries so additional execution time is reduced. Paging mechanism: