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NI Labview High-Performance FPGA Developer's Guide

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NI Labview High-Performance FPGA Developer's Guide NI LabVIEW High-Performance FPGA Developer’s Guide Recommended Practices for Optimizing LabVIEW RIO Applications Revision No. 1.1 – February 2014 ©2014 National Instruments. All rights reserved. CompactRIO, LabVIEW, National Instruments, NI, ni.com, NI FlexRIO, the National Instruments corporate logo, and the Eagle logo are trademarks of National Instruments. For other National Instruments trademarks see ni.com/trademarks. Other product and company names listed are trademarks or trade names of their respective companies. A National Instruments Alliance Partner is a business entity independent from National Instruments and has no agency, partnership, or joint-venture relationship with National Instruments. TABLE OF CONTENTS Introduction ................................................................................................................................................... 5 Intended Audience .................................................................................................................................... 5 Prerequisites and References ................................................................................................................... 5 High-Performance FPGA-Based Design ........................................................................................................ 7 Advantages of FPGAs ................................................................................................................................ 7 High-Performance LabVIEW FPGA ........................................................................................................... 7 Understanding the NI RIO Hardware Platform ............................................................................................. 9 NI RIO for PXI and the PC ......................................................................................................................... 9 NI RIO for Compact Embedded Applications .......................................................................................... 12 Selecting an FPGA Platform .................................................................................................................... 13 High-Performance Programming With the Single-Cycle Timed Loop ......................................................... 15 The SCTL Versus Standard LabVIEW FPGA Code .................................................................................. 15 Understanding the SCTL ......................................................................................................................... 16 Benefits of the SCTL ............................................................................................................................... 18 Restrictions of the SCTL.......................................................................................................................... 18 Throughput Optimization Techniques ......................................................................................................... 23 Increasing the Clock Rate ........................................................................................................................ 23 Increasing the Number of Samples Processed per Call .......................................................................... 24 Critical Path Reduction ............................................................................................................................ 25 Decreasing the Initiation Interval ............................................................................................................. 30 Integrating High-Throughput IP ................................................................................................................... 33 Recommended Sources of LabVIEW FPGA IP ....................................................................................... 33 LabVIEW FPGA High Throughput Function Palettes ............................................................................... 33 IP Handshaking Protocols ........................................................................................................................ 36 Determining Processing Chain Throughput............................................................................................. 42 The DSP48 Node ..................................................................................................................................... 43 The Fast Fourier Transform ..................................................................................................................... 44 The Xilinx CORE Generator IP System .................................................................................................... 46 Integrating HDL IP ................................................................................................................................... 48 Integrating IP Into Software-Designed Instruments ............................................................................... 50 Integrating IP From the Community ........................................................................................................ 52 Timing Optimization Techniques ................................................................................................................. 55 Determining and Specifying Latency With the SCTL .............................................................................. 55 Reducing Latency Through Parallelization ............................................................................................... 56 Removing Pipelining Registers ................................................................................................................ 58 Optimizing Data Types ............................................................................................................................ 58 Resource Optimization Techniques ............................................................................................................ 59 FPGA Resource Types............................................................................................................................. 59 Filling Up the FPGA ................................................................................................................................. 60 Optimizing Resources Through Data Types ............................................................................................ 61 Minimizing the Use of Front-Panel Controls and Indicators .................................................................... 64 Tweaking Output Overflow and Rounding Options ................................................................................ 65 Initializing Feedback Nodes ..................................................................................................................... 67 Resource Balancing ................................................................................................................................. 67 Multiplexing Logic ................................................................................................................................... 70 Using the SCTL as a Way to Save Resources ......................................................................................... 71 Data Transfer Mechanisms ......................................................................................................................... 73 Throughput and Latency of Data Transfer Mechanisms ......................................................................... 73 Transferring Data Within the FPGA ......................................................................................................... 75 Transferring Data between the FPGA and the Host System .................................................................. 82 Transferring Data between Devices ........................................................................................................ 87 Next Steps................................................................................................................................................... 93 Formal Training ........................................................................................................................................ 93 Evaluating the NI RIO Platform ............................................................................................................... 93 NI Alliance Partners and Services ............................................................................................................ 93 Revisions and Feedback .............................................................................................................................. 94 INTRODUCTION Field-programmable gate array (FPGA) technology provides the performance and reliability of dedicated, custom hardware. As a LabVIEW FPGA user, you can take advantage of FPGA technology within the same design environment you use to program desktop and real-time systems. High-performance LabVIEW FPGA applications push the capabilities of NI reconfigurable I/O (RIO) devices with respect to timing, FPGA resources, and other dimensions. This guide helps you create high- performance applications by offering a summary of common LabVIEW FPGA optimization concepts and techniques. INTENDED AUDIENCE If you are already familiar with LabVIEW or the LabVIEW FPGA Module, use this guide to learn about advanced, industry-agnostic LabVIEW FPGA concepts to help you tackle more demanding applications that require
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