Effect of Non-Idealities – Bilinear Switched-Capacitor Filters – Filter Design Summary • Comparison of Various Filter Topologies • Data Converters

EE247 Lecture 11 • Switched-Capacitor Filters (continued) – Effect of non-idealities – Bilinear switched-capacitor filters – Filter design summary • Comparison of various filter topologies • Data Converters

Summary Last Lecture

• Switched-capacitor filter design considerations – DDI & LDI Integrator characteristics – Bottom-plate LDI integrator Æ overcomes parasitic sensitivity issues – Continuous-time and complex conjugate terminations – Use of T-networks to implement high capacitor ratios • Switched-capacitor filters utilizing double sampling technique • Effect of non-idealities – Opamp finite gain – Opamp finite bandwidth – Finite slew rate of the opamp (this lecture)

C φ φ I 1 2 φ Vin φ 1 - 1 φ Cs Vo 2 + T=1/fs

− Vo =−Cs × z 1 (z) − CI 1−z 1 Vin C =−s × −1 C1I z

DDI Switched-Capacitor Integrator

C φ φ I 1 2 Vin φ - 1

Cs Vo +

− Vo =−Cs ×z 1 = jTω (z)− , z e CI 1−z 1 Vin αα− − jT/2ω jj− =×CCss1 = ×e α =ee ωωω− since: sin CCII1−−eeejT jT/2 jT/2 2j

− ω =−jeCs ×jT/2 × 1 CI 2sin()ωT/2

Cs 1 ωT/2 − jT/2ω =−ω × × e CjTI sin()ωT/2 ror se Er Ideal Integrator Magnitude Error Pha

Cs Vo + Example: Mag. & phase error for: sig 1- f max ./ fs = 1/12 Æ Mag. error = 1% or 0.1dB ω π π Phase error=- T/2= - f / fs= - /12 [radian] Æ 15 [degree] ω QintgÆ 1/( phase error @ ο in radian ) (Lecture 5 page 1) π Æ Qintg= -12/ = -3.8

2- f / fs=1/32 Æ Mag. error=0.16% or 0.014dB ω π π Phase error = T/2= - f / fs= - /32 [radian] Æ 5.6 [degree] π Qintg = -32/ = -10.2 DDI Integrator: Æ Magnitude error no problem Phase error major problem

LDI Switched-Capacitor Integrator C LDI (Lossless Discrete Integrator) Æ φ φ I 1 2 same as DDI but output is sampled ½ Vin φ clock cycle earlier - 2 LDI Cs Vo2 V − + o2 =−Cs ×z 1/2 = jTω (z)− , z e CI 1z− 1 Vin − ω =−CCse ×jT/2 = s × 1 −−+ωωω CCII1−−eeej T j T/2 j T/2

=−j Cs × 1 CI 2sin()ωT/2

Cs 1 ωT/2 =−ω × No Phase Error! CjTI sin()ωT/2 For signals at frequencies << sampling freq. Æ Magnitude error negligible Ideal Integrator Magnitude Error

Effect of parasitic capacitors:

1- Cp1 - driven by opamp o.k.

2- Cp2 - at opamp virtual gnd o.k.

3- Cp3 – Charges to Vin & discharges into CI Æ Problem parasitic sensitivity

Parasitic Insensitive Bottom-Plate Switched-Capacitor Integrator

Sensitive parasitic cap. Æ Cp1 Æ rearrange circuit so that Cp1 does not charge/discharge φ 1=1 Æ Cp1 grounded φ 2=1 Æ Cp1 at virtual ground Cp2 Æ driven by a low impedance source

φ φ CI 1 2 - C C s p1 Vo + Vi+ Cp2 Vi- Solution: Bottom plate capacitor integrator

Vi- Output/Input z-Transform Vo1 Vo2 Note: on φ1 on φ2 − 1 Different delay from Vi+ & −1 2 Vi+ CCsszz Vi- to either output CC−−11 on φ1 II1z−− 1z Æ Special attention needed for input/output connections Vi- −1 −−CCssz12 on φ2 −− CCII1z−−11 1z

Bottom Plate Switched-Capacitor Integrator z-Transform Model

φ φ CI φ 1 2 1 − −1 zz1 - 2 Vo1 −−C11φ 1z−−s 1z 2 Vo + Vo2 Vi+ −1 z12 − Input/Output−− z-transform Vi- 1z−−11 1z

−1 Vi+ CCs I 2 −1 Vo1 z z 2 − −1 + 1 Vi- −CCs I 1z z 2 Vo2

LDI

1 +1 C C + s − s 2 z 2 CI CI z

− - + 2 − 1 z − 1 1 1 1 z 2 z 2 τ 1 sτ s 4 sτ5 −1 − −1 3 1z− 2 1z− + - + - z −1 1 − 1 − 1z − z 2 z 2

C Cs C 1 Cs − s − s + C CI CI z 2 CI I

Delay around integrator loop is (z-1/2 . z+1/2 =1) Î LDI function

Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour • Opamp finite gain • Opamp finite bandwidth • Finite slew rate of the opamp • Non-linearities associated with opamp output/input characteristics

φ φ CI 1 2 - Cs Vo + ≈− Cs 1 Vi+ H(s) fs DC Gain = a CI Cs 1 sf+×s Input/Output z-transform CaI Vi- −ω H(s) ≈ o s +×ω 1 o a

⇒ Qa≈ ÆFinite DC gain same effect in S.C. filters as for C.T. filters ÆIf DC gain not high enough Æ causes lowing of overall Q & droop in passband

Effect of Opamp Non-Idealities Finite Opamp Bandwidth V φ φ CI o settling 1 2 error - Cs Vo + φ Vi+ 2 Unity-gain-freq. Input/Output z-transform time Vi- = ft T=1/fs

Assumption-

Opamp Æ does not slew (will be revisited) Opamp has only one pole Æ exponential settling

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 14 Effect of Opamp Non-Idealities Finite Opamp Bandwidth V φ φ CI o settling 1 2 error - Cs Vo + φ Vi+ 2 Unity-gain-freq. Input/Output z-transform time Vi- = ft T=1/fs

⎡⎤−−C − ≈ 1e−+×kk eI Z 1 H(Z)H(Z)actual ideal ⎢⎥ ⎣⎦CCIs+ Cf where k =×π It × CCIss+ f fts→−−→Opamp unity gain frequency , f Clock frequency Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Effect of Opamp Finite Bandwidth on Filter Magnitude Response |Τ| Τ| non-ideal /| ideal (dB) Example: For 1dB magnitude response deviation: fc /fs=1/32 Active RC 1- fc/fs=1/12 fc /fs=1/12 fc/ft~0.04 Æ ft>25fc

2- fc/fs=1/32 fc/ft~0.022 Æ ft>45fc 3- Cont.-Time

fc/ft~1/700 Æ ft >700fc fc /ft

Example: Δω ω For maximum critical c / c frequency shift of <1% f /f =1/32 Active RC c s 1- fc/fs=1/32 fc/ft~0.028 fc /fs=1/12 Æ ft>36fc

2- fc/fs=1/12 fc/ft~0.046 Æ ft>22fc 3- Active RC C.T. filters fc/ft~0.008 Æ ft >125fc fc /ft Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of SwitchedCapacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Opamp Bandwidth Requirements for Switched- Capacitor Filters Compared to Continuous-Time Filters

• Finite opamp bandwidth causes phase lag at the unity-gain frequency of the integrator for both type filters Æ Results in negative intg. Q & thus increases overall Q and gain @ results in peaking in the passband of interest

• For given filter requirements, opamp bandwidth requirements much less stringent for S.C. filters compared to cont. time filters Æ lower power dissipation for S.C. filters (at low freq.s only)

• Finite opamp bandwidth causes down shifting of critical frequencies in both type filters – Since cont. time filters are usually tunedÆ tuning accounts for frequency deviation – S.C. filters are untuned and thus frequency shift could cause problems specially for narrow-band filters

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 18 Sources of Distortion in Switched- Capacitor Filters • Distortion induced by finite slew rate of the opamp • Opamp output/input transfer function nonlinearity- similar to cont. time filters • Distortion incurred by finite setting time of the opamp • Capacitor non-linearity- similar to cont. time filters • Distortion due to switch clock feed-through and charge injection

What is Slewing?

C φ I 2 Vin CI - Vo Cs Vo CL + φ 2

Cs Vi- Vi+

Iss Assumption: Integrator opamp is a simple class A transconductance type differential pair with fixed tail current Iss

Opamp Io v.s. Vin C Io I V Imax= +Iss/2 o Slope ~ gm I φ o Vmax Vin 2

Cs Vi- Imax= -I ss/2 Vi+ Iss |VCs| > Vmax Æ Output current constant Io=Iss/2 or –Iss/2 Æ Vo ramps down/up Æ Slewing After Vcs is discharged enough to have:

|VCs|

Distortion Induced by Opamp Finite Slew Rate

Output Voltage Multiple pole settling

One pole settling

Time Slewing Settling Settling (multi-pole)

φ CI 1 Vin φ - 1 C Clock s Vo φ + 2

Vin C φ I 2 Vin - Vcs Cs Vo + Vo φ 2 High ÆCharge transferred from Cs to CI

Slew Limited Switched-Capacitor Integrator Output Slewing & Settling

φ 1 Clock φ 2

Vo-ideal

Vo-real

Slewing Linear Slewing Linear Settling Settling

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).

Distortion Induced by Opamp Finite Slew Rate

• Error due to exponential settling changes linearly with signal amplitude • Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error) ÆFor high-linearity need to have either high slew rate or non-slewing opamp ω T 2 V 8()sin os HD = o 2 k π STrs k ()k42 − ω 2 8()sin osT 2 V8Voo2 π fo →=HD3os3 for f >>→ f HD ≈ STrs 15π 15S r f s Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).

ω 2 8()sin osT Vo 2 HD3 = STrs 15π 12dB 2 8Vπ o fo HD3 ≈ 15Srs f

μ Switched-capacitor filter with 4kHz bandwidth, fs=128kHz, Sr=1V/ sec, Vo=3V

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).

Distortion Induced by Opamp Finite Slew Rate Example

-20

-40 V o =1V V o =2V -60 f / fs =1/12

HD3 [dB] f / f =1/32 -80 s V o =1 V V o =2V -100

-120 1 10 100 1000

(Slew-rate / fs ) [V]

• Note that for a high order switched capacitor filter Æ only the last stage slewing will affect the output linearity (as long as the previous stages settle to the required accuracy) Æ Can reduce slew limited linearity by using an amplifier with a higher slew rate only for the last stage Æ Can reduce slew limited linearity by using class A/B amplifiers • Even though the output/input characteristics is non-linear as long as the DC open-loop gain is high, the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) Æ no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time

More Realistic Switched-Capacitor Circuit Slew Scenario

C C φ I φ I 2 2 Vin - CL CL Cs Cs Vo Vo + t=0+

At the instant Cs connects to input of opamp (t=0+) Æ Opamp not yet active at t=0+ due to finite opamp bandwidth Æ delay Æ Feedforward path from input to output generates a voltage spike at the output

with polarity opposite to final Vo step- spike magnitude function of CI, CL , Cs Æ Spike increases slewing period Æ Eventually, opamp becomes active - starts slewing followed by subsequent settling

−+ CC Charg e sharing : C Vtt00=+ V() C C where C =IL s Cs Cs s eq eq + CCIL ++CCC − Δ=VVtt00IsI = V t 0 × out Cs+++ Cs CCIL CC seqIL CC << << → ≈ →tt00−+ ≈ + → tt 00 −+ ≈ AssumingCCCCCCVVCCVVL s I eq L s Cs Cs() s L Cs Cs

+−CC − →ΔVVtt00 ≈sI × ≈ V t 0 out Cs++ Cs CCsLIL CC Δ≈−≈−finalCCss t00+− t Note that Vout V Cs V Cs CCI I

More Realistic Switched-Capacitor Circuit Slew Scenario C C φ I φ I 2 2 Vin - CL CL Cs Cs Vo Vo + t=0+

Notice that if CL is large Æ some of the charge stored on Cs is lost prior to opamp becoming effective Æ operation looses accuracy −+ CC Charg e sharing : C Vtt00=+ V() C C where C =I L s Cs Cs s eq eq + CCI L +−CC − VVtt00==ss V t 0 Cs Cs+ Cs CC CCseq C + IL s + CCIL Æ Partly responsible for S.C. filters only good for low-frequency applications

Vo_ideal

Vo_real

Slewing Linear Slewing Linear Settling Settling Spike generated Vo_real at t=0+ Including t=0+ spike

Slewing Linear Slewing Settling Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. ‘84 (ERL Memorandum No. UCB/ERL M84/67).

Sources of Noise in Switched- Capacitor Filters • Opamp Noise – Thermal noise – 1/f (flicker) noise • Thermal noise associated with the switching process (kT/C) – Same as continuous-time filters • Precaution regarding aliasing of noise required

()=−++− ( ) () ( ) vnTvnTToo kvnTvnTT⎣⎡ ii ⎦⎤

⎡⎤−=+−−11 ⎡⎤ ⎣⎦1()1()zVzkoi ⎣⎦ z Vz

+ −1 ()==Vzo () 1 z Hz k −1 Vzi () 1− z

Bilinear Integrator

- Not implemented by “standard” SC integrators - Synthesis: Biquads: direct coefficient comparison Example: Bilinear S.C. integrator: − =−Cs ×1Z+ 1 H(Z ) − C1I 1Z− − ω =−Cs ×1e+ jT − ω CI 1−e jT ω = Cs 1 Ts ω CTIsjTω s tan 2 No Phase Error! For signals at frequency <

Ref: R. Gregorian, G. Temes, “Analog CMOS Integrated Circuits," Wiley, 1986, pp 277 .

LDI : − 1Z1/2 = Ts 1 ⇒ − ω s 1Z− 1 2 Ts jsin 2 ω s ⇒ 2 jsin Ts Ts 2

Bilinear − − ω 11Z+ 1 ==1e+ jT Ts 1 ⇒ − − ω ω s − 1T1−e jT 2 s 1Z jtan 2 ω s ⇒ 2 jtan Ts Ts 2

Other z domain Integrators Example: Bilinear

• Frequency translation

1 = () HzSC = 2π jfSC T s = π ze Bilinear LDI sjf2 RC

⎛ ⎞ ff⎛⎞ = fs π fSC = sSCπ fRC sin⎜ ⎟ fRC tan π ⎜ ⎟ π ⎜⎟ fs ⎝⎠fs ⎝ ⎠

0.5 fs ⎛ fSC ⎞ 0.45 f = tan⎜π ⎟ RC π ⎜ ⎟ 0.4 ⎝ fs ⎠ 0.35 s 0.3 /f

sc ω f 0.25 • Entire j axis maps onto the unit 0.2 circle 0.15 0.1 • Mapping is nonlinear (tan distortion) 0.05 Æ prewarp specifications of RC prototype 0 0.5 1 1.5 2 2.5 3 f /f Matlab filter design automates this RC s (see, e.g. bilinear)

Bilinear & LDI Transformation Frequency Warping

As long as f<

Pole-Zero Map 1 fs = 100kHz 0.8 fc = fs/8 zero at f /2 0.6 s 0.4

Q = 10 0.2

0 Imag Axis

-0.2 Matlab: -0.4 -0.6

-0.8

-1 0.0378 z^2 - 0.0378 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Real Axis H(z) = ------z^2 - 1.362 z + 0.9244

K4 CA = 1.125pF Martin-Sedra Biquad phi1 phi1

Periodic AC Analysis PAC1 phi2 phi2 log sweep from 1k to 50k (300 steps)

CLK1 K6 CA = 151.2fF fs = 100kHz

CA = 1pF CB = 1pF

K1 CA = 0F K5 CB = 500fF phi1 phi1 phi1 phi2 Vi -1M -1M Vo phi2 phi2 phi2 phi1

V1 ac = 1V K2 CA = 151.2fF

K3 CB = 37.8fF

Ref: K. Martin and A. S. Sedra, “Strays-insensitive switched- () 2 + ()()− + + + − Vo z = K3z 2K3 K1K5 K2K5 z K3 K2K5 capacitor filters based on the bilinear () 2 + ()()− + + + − z transform,” Electron. Lett., vol. 19, Vi z z 2 K4K5 K5K6 z 1 K5K6 pp. 365-6, June 1979.

-10

-20

-30

Magnitude [dB] -40

-50

-60

-70 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Frequency [Hz] 5 x 10

LDI vs Bilinear Transform

•LDI transform: – Realized by “standard” switched-capacitor integrators – Some high frequency zeros may get lost – Simple filter synthesis: • Replace RC integrators with SC integrators • Ensure clock phases chosen so that all integrators loops LDI type • Bilinear transform – Not implemented by “standard” SC integrators – Synthesis: • Biquads: direct coefficient comparison • Ladders: see R. B. Datar and A. S. Sedra, “Exact design of strays-insensitive switched capacitor high-pass ladder filters”, Electron. Lett., vol. 19, no 29, pp. 1010-12, Nov. 1983.

f = 128kHz f = 8kHz f = 8kHz fs= 1024kHz s s s

fs= 128kHz

f = 128kHz fs= 8kHz fs= 128kHz s

Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.

CODEC Transmit Path Lowpass Filter Frequency Response

0 Note: fs=128kHz

-10

-20

Magnitude (dB) -30

-40

-500 2000 4000 6000 8000 Frequency (Hz)

-10

-20 Magnitude (dB) -30

-40 Note: fs=8kHz

-50 10 100 1000 10000 Frequency (Hz)

CODEC Transmit Path Filter Overall Frequency Response

-10

-20 Magnitude (dB) -30

-40

-50 10 100 1000 10000 Frequency (Hz)

Low Q bandpass (Q<1) filter shapeÆ Implemented with lowpass followed by highpass

First filter (1st order RC type) performs anti-aliasing for the next S.C. biquad

The first 2 stage filters form 3rd order elliptic with corner frequency @ 32kHz Æ Anti-aliasing for the next lowpass filter

The stages prior to the high-pass perform anti-aliasing for high- pass

Notice gradual lowering of clock frequency Æ Ease of anti-aliasing

SC Filter Summary

9 Pole and zero frequencies proportional to

– Sampling frequency fs – Capacitor ratios ¾ High accuracy and stability in response ¾ Long time constants realizable without large R, C 9 Compatible with transconductance amplifiers – Reduced circuit complexity, power dissipation 9 Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only) / Issue: Sampled-data filters Æ require anti-aliasing prefiltering

Considering overall Magnitude effects: Error • Opamp finite unity- gain-bandwidth • Opamp settling issues • Opamp finite slew rate Cont. Time Filter • Clock feedthru • Switch+ sampling cap. finite time- S.C. Filter constant Filter bandwidth 5-10MHz Assuming constant opamp fu Æ Limited switched-capacitor filter performance frequency range

Summary Filter Performance versus Filter Topology

Max. Usable SNDR Freq. Freq. Bandwidth tolerance tolerance w/o tuning + tuning Opamp-RC ~10MHz 60-90dB +-30-50% 1-5%

Opamp- ~ 5MHz 40-60dB +-30-50% 1-5% MOSFET-C Opamp- ~ 5MHz 50-90dB +-30-50% 1-5% MOSFET-RC Gm-C ~ 100MHz 40-70dB +-40-60% 1-5%

Switched ~ 10MHz 40-90dB <<1% _ Capacitor

Material Covered in EE247 Where are We? 9 Filters – Continuous-time filters • Biquads & ladder type filters • Opamp-RC, Opamp-MOSFET-C, gm-C filters • Automatic frequency tuning – Switched capacitor (SC) filters • Data Converters – D/A converter architectures – A/D converter • Nyquist rate ADC- Flash, Pipeline ADCs,…. • Oversampled converters • Self-calibration techniques • Systems utilizing analog/digital interfaces

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 54 Data Converter Topics • Basic operation of data converters – Uniform sampling and reconstruction – Uniform amplitude quantization • Characterization and testing • Common ADC/DAC architectures • Selected topics in converter design – Practical implementations – Desensitization to analog circuit non-idealities • Figures of merit and performance trends

Suggested Reference Texts

• R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd ed., Kluwer, 2003.

• B. Razavi, Data Conversion System Design, IEEE Press, 1995.

• S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 1997. Extensive treatment of oversampled converters including stability, tones, bandpass converters.

• J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, 1995.

Data Converter Basics Analog Input • DSPs benefited from device Analog Filters scaling Preprocessing • However, real world signals are A/D ? still analog: Conversion – Continuous time 000 – Continuous amplitude DSP ...001... 110 • DSP can only process: D/A – Discrete time Conversion ? – Discrete amplitude Æ Need for data conversion from Analog Filters analog to digital and digital to Postprocessing analog Analog Output

A/D Conversion

D/A Conversion

Data Converters

• Stand alone data converters – Used in variety of systems – Example: Analog Devices AD9235 12bit/ 65Ms/s ADC- Applications: • Ultrasound equipment • IF sampling in wireless receivers • Various hand-held measurement equipment • Low cost digital oscilloscopes

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 60 Data Converters • Embedded data converters – Cost, reliability, and performance Æ Integration of data conversion interfaces along with DSPs – Main issues • Feasibility of integrating sensitive analog functions in a technology optimized for digital performance • Down scaling of supply voltage • Interference & spurious signal pick-up from on-chip digital circuitry • Portable applications dictate low power consumption

Example: Typical Cell Phone

Contains in integrated form: • 4 Rx filters • 4 Tx filters Dual Standard, I/Q • 4 Rx ADCs •4 Tx DACs • 3 Auxiliary ADCs Audio, Tx/Rx power control, Battery charge • 8 Auxiliary DACs control, display, ... Total: Filters Æ 8 ADCs Æ 7 DACs Æ 12

• For an ideal digital-to-analog MSB LSB converter accepting digital inputs b1- b1 b2 b3 bn bn and producing either an analog ……..… output voltage or current with: uniform, binary digital encoding & a V D/A 0 unipolar output ranging from 0 to VFS Nomenclature:

N= # of bits = VFS full scale output N bi Δ=min. step size → 1LSB VV= 0FS∑ i i1= 2 Δ=VFS N N 2 =Δ ×Ni− = VFS ∑bi 2 , bi 0 or 1 or N=→ log resolution i1= 2 Δ

D/A Converter Exampe: D/A with 3-bit Resolution

Example:N= 3 MSB LSB = Assume VFS 0.8V b b b Input code is101 1 2 3 1 0 1 =Δ()×+×+×210 V0 b2123 b2 b2 V Δ=3 = 0 Then: VFS / 2 0.1V D/A

→=210 = V0.1V0 ()12×+×+× 02 12

→=V0.5V0

N Note:MSB→→ VFS / 2 & LSB V FS / 2

• One-to-one mapping V /2 from input FS Step Height (1LSB =Δ) to output

VFS /8

Digital Input 000 001 010 011 100 101 110 111 Code

A/D Converter Transfer Characteristic

MSB LSB

• For an ideal analog-to-digital b1 b2 b3 bm converter with uniform, binary ……..… digital encoding & a unipolar V0 input range for 0 to VFS D/A where m= # of bits = VFS full scale output Δ= step size

Δ=VFS 2m = →−Δ Note:D()b1,allii VFS → ⎛⎞− 1 VFS ⎜⎟1 ⎝⎠2m

Digital Output • Ideal ADC introduces error 111 Æ(+-1/2 Δ) 110 Δ = V /2 m 101 FS m= # of bits 100 011

•This error is 010 called ``quantization 001 1LSB Analog input error`` 000 0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ

Data Converter Performance Metrics

• Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : – Static • Monotonicity • Offset • Gain error • Differential nonlinearity (DNL) • Integral nonlinearity (INL) – Dynamic • Delay, settling time • Aperture uncertainty • Distortion- harmonic content • Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR) • Idle channel noise • Dynamic range & spurious-free dynamic range (SFDR)