EE247 Lecture 11 • Switched-Capacitor Filters (continued) – Effect of non-idealities – Bilinear switched-capacitor filters – Filter design summary • Comparison of various filter topologies • Data Converters EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 1 Summary Last Lecture • Switched-capacitor filter design considerations – DDI & LDI Integrator characteristics – Bottom-plate LDI integrator Æ overcomes parasitic sensitivity issues – Continuous-time and complex conjugate terminations – Use of T-networks to implement high capacitor ratios • Switched-capacitor filters utilizing double sampling technique • Effect of non-idealities – Opamp finite gain – Opamp finite bandwidth – Finite slew rate of the opamp (this lecture) EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 2 Switched-Capacitor Direct-Transform Discrete (DDI) Integrator C φ φ I 1 2 φ Vin φ 1 - 1 φ Cs Vo 2 + T=1/fs − Vo =−Cs × z 1 (z) − CI 1−z 1 Vin C =−s × −1 C1I z EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 3 DDI Switched-Capacitor Integrator C φ φ I 1 2 Vin φ - 1 Cs Vo + − Vo =−Cs ×z 1 = jTω (z)− , z e CI 1−z 1 Vin αα− − jT/2ω jj− =×CCss1 = ×e α =ee ωωω− since: sin CCII1−−eeejT jT/2 jT/2 2j − ω =−jeCs ×jT/2 × 1 CI 2sin()ωT/2 Cs 1 ωT/2 − jT/2ω =−ω × × e CjTI sin()ωT/2 ror se Er Ideal Integrator Magnitude Error Pha EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 4 DDI Switched-Capacitor Integrator C φ φ I 1 2 Vin φ - 1 Cs Vo + Example: Mag. & phase error for: sig 1- f max ./ fs = 1/12 Æ Mag. error = 1% or 0.1dB ω π π Phase error=- T/2= - f / fs= - /12 [radian] Æ 15 [degree] ω QintgÆ 1/( phase error @ ο in radian ) (Lecture 5 page 1) π Æ Qintg= -12/ = -3.8 2- f / fs=1/32 Æ Mag. error=0.16% or 0.014dB ω π π Phase error = T/2= - f / fs= - /32 [radian] Æ 5.6 [degree] π Qintg = -32/ = -10.2 DDI Integrator: Æ Magnitude error no problem Phase error major problem EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 5 LDI Switched-Capacitor Integrator C LDI (Lossless Discrete Integrator) Æ φ φ I 1 2 same as DDI but output is sampled ½ Vin φ clock cycle earlier - 2 LDI Cs Vo2 V − + o2 =−Cs ×z 1/2 = jTω (z)− , z e CI 1z− 1 Vin − ω =−CCse ×jT/2 = s × 1 −−+ωωω CCII1−−eeej T j T/2 j T/2 =−j Cs × 1 CI 2sin()ωT/2 Cs 1 ωT/2 =−ω × No Phase Error! CjTI sin()ωT/2 For signals at frequencies << sampling freq. Æ Magnitude error negligible Ideal Integrator Magnitude Error EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 6 Switched-Capacitor Integrator Parasitic Sensitivity C φ φ I 1 2 Vin - Vo Cp2 C Cs p3 + Cp1 Effect of parasitic capacitors: 1- Cp1 - driven by opamp o.k. 2- Cp2 - at opamp virtual gnd o.k. 3- Cp3 – Charges to Vin & discharges into CI Æ Problem parasitic sensitivity EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 7 Parasitic Insensitive Bottom-Plate Switched-Capacitor Integrator Sensitive parasitic cap. Æ Cp1 Æ rearrange circuit so that Cp1 does not charge/discharge φ 1=1 Æ Cp1 grounded φ 2=1 Æ Cp1 at virtual ground Cp2 Æ driven by a low impedance source φ φ CI 1 2 - C C s p1 Vo + Vi+ Cp2 Vi- Solution: Bottom plate capacitor integrator EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 8 Bottom Plate Switched-Capacitor Integrator φ φ φ CI 1 1 2 Vo1 - φ Cs 2 Vo + Vo2 Vi+ Vi- Output/Input z-Transform Vo1 Vo2 Note: on φ1 on φ2 − 1 Different delay from Vi+ & −1 2 Vi+ CCsszz Vi- to either output CC−−11 on φ1 II1z−− 1z Æ Special attention needed for input/output connections Vi- −1 −−CCssz12 on φ2 −− CCII1z−−11 1z EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 9 Bottom Plate Switched-Capacitor Integrator z-Transform Model φ φ CI φ 1 2 1 − −1 zz1 - 2 Vo1 −−C11φ 1z−−s 1z 2 Vo + Vo2 Vi+ −1 z12 − Input/Output−− z-transform Vi- 1z−−11 1z −1 Vi+ CCs I 2 −1 Vo1 z z 2 − −1 + 1 Vi- −CCs I 1z z 2 Vo2 LDI EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 10 LDI Switched-Capacitor Ladder Filter 1 +1 C C + s − s 2 z 2 CI CI z 1 − - + 2 − 1 z − 1 1 1 1 z 2 z 2 τ 1 sτ s 4 sτ5 −1 − −1 3 1z− 2 1z− + - + - z −1 1 − 1 − 1z − z 2 z 2 C Cs C 1 Cs − s − s + C CI CI z 2 CI I Delay around integrator loop is (z-1/2 . z+1/2 =1) Î LDI function EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 11 Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour • Opamp finite gain • Opamp finite bandwidth • Finite slew rate of the opamp • Non-linearities associated with opamp output/input characteristics EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 12 Effect of Opamp Non-Idealities Finite DC Gain φ φ CI 1 2 - Cs Vo + ≈− Cs 1 Vi+ H(s) fs DC Gain = a CI Cs 1 sf+×s Input/Output z-transform CaI Vi- −ω H(s) ≈ o s +×ω 1 o a ⇒ Qa≈ ÆFinite DC gain same effect in S.C. filters as for C.T. filters ÆIf DC gain not high enough Æ causes lowing of overall Q & droop in passband EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 13 Effect of Opamp Non-Idealities Finite Opamp Bandwidth V φ φ CI o settling 1 2 error - Cs Vo + φ Vi+ 2 Unity-gain-freq. Input/Output z-transform time Vi- = ft T=1/fs Assumption- Opamp Æ does not slew (will be revisited) Opamp has only one pole Æ exponential settling Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981. EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 14 Effect of Opamp Non-Idealities Finite Opamp Bandwidth V φ φ CI o settling 1 2 error - Cs Vo + φ Vi+ 2 Unity-gain-freq. Input/Output z-transform time Vi- = ft T=1/fs ⎡⎤−−C − ≈ 1e−+×kk eI Z 1 H(Z)H(Z)actual ideal ⎢⎥ ⎣⎦CCIs+ Cf where k =×π It × CCIss+ f fts→−−→Opamp unity gain frequency , f Clock frequency Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981. EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 15 Effect of Opamp Finite Bandwidth on Filter Magnitude Response |Τ| Τ| non-ideal /| ideal (dB) Example: For 1dB magnitude response deviation: fc /fs=1/32 Active RC 1- fc/fs=1/12 fc /fs=1/12 fc/ft~0.04 Æ ft>25fc 2- fc/fs=1/32 fc/ft~0.022 Æ ft>45fc 3- Cont.-Time fc/ft~1/700 Æ ft >700fc fc /ft EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 16 Effect of Opamp Finite Bandwidth on Filter Critical Frequency Example: Δω ω For maximum critical c / c frequency shift of <1% f /f =1/32 Active RC c s 1- fc/fs=1/32 fc/ft~0.028 fc /fs=1/12 Æ ft>36fc 2- fc/fs=1/12 fc/ft~0.046 Æ ft>22fc 3- Active RC C.T. filters fc/ft~0.008 Æ ft >125fc fc /ft Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of SwitchedCapacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981. EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 17 Opamp Bandwidth Requirements for Switched- Capacitor Filters Compared to Continuous-Time Filters • Finite opamp bandwidth causes phase lag at the unity-gain frequency of the integrator for both type filters Æ Results in negative intg. Q & thus increases overall Q and gain @ results in peaking in the passband of interest • For given filter requirements, opamp bandwidth requirements much less stringent for S.C. filters compared to cont. time filters Æ lower power dissipation for S.C. filters (at low freq.s only) • Finite opamp bandwidth causes down shifting of critical frequencies in both type filters – Since cont. time filters are usually tunedÆ tuning accounts for frequency deviation – S.C. filters are untuned and thus frequency shift could cause problems specially for narrow-band filters EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 18 Sources of Distortion in Switched- Capacitor Filters • Distortion induced by finite slew rate of the opamp • Opamp output/input transfer function non- linearity- similar to cont. time filters • Distortion incurred by finite setting time of the opamp • Capacitor non-linearity- similar to cont. time filters • Distortion due to switch clock feed-through and charge injection EECS 247 Lecture 11: S.C.