Operational Amplifier and Digital Electronics
Dr. M Ramegowda Associate Professor of Physics Govt. College (Autonomous), Mandya
Dr. M Ramegowda 2
Dr. M Ramegowda Chapter 1
The Differential Amplifier
1.1 The basic differential amplifier
Circuit diagram of the emitter coupled differential amplifier is shown in figure 1.1. It consists of two identical transistors Q1 and Q2. The emitters of the transistors are connected to −VEE through a common resistor RE. Collectors are connected to +VCC through equal collector s resistances RC . Two inputs v1 and v2 are applied to the bases of Q1 and Q2 through resistances R1 and R2, and the output vo is measured across two collectors as shown in the circuit diagram. VEE and RE form an approximate constant current source for the amplifier. This amplifier is very useful because
ó +VCC
ÿ
RC ¡ RC ¡ ¨vo
Q1 Q2
ÿ R1 ¡ ¡ R2 RE v1 ∼ ∼ v2 ¡
ý© ©ý
ñ −VEE Dr.Figure M 1.1: Basic Ramegowda difference amplifier
• it operates without input capacitors, means that it can work as a DC amplifier
• it provides voltage gain for differential signals on the inputs, vid = v1 − v2 and attenuating interfering common-mode signals, vcm = (v1 + v2)/2 • it provides the inverting and non-inverting inputs needed for operational amplifiers.
The zero signal emitter current is given by
VEE = IE = I1 + I2 (1.1) RE
3 4 CHAPTER 1. THE DIFFERENTIAL AMPLIFIER
ÿý RC ¡ RC ÿ ¨ ÿ¡ vo
↓ ic ic ↓ v1 1 2 v2 ð ©ÿ ©ÿ ò re ¡ re ¡ i i 1 ù ÿ2 ù
RE
¡
ý
Figure 1.2: Small signal model of Basic difference amplifier
A more complete analysis can be done using the small signal AC model for the circuit which is shown in the Fig. 1.2. When both inputs are at 0V , the current splits equally in the two branches. If v1 is raised slightly while holding v2 = 0V , i1 start to increase, and the voltage drop across RC of transistor Q1 increases. Hence vo = vc1 − vc2 becomes positive, so v1 is called non-inverting input. In the same way, raising v2 slightly with v1 grounded, increases the value of i2. This now increases vc2 and vo = vc1 − vc2 becomes negative, so v2 is called inverting input. When both v1 and v2 are applied, the amplifier works in the differential mode with input vid = v1 − v2. Then the gain of the amplifier is v A = o vid 1.2 Configurations of differential amplifier
Differential amplifier can be used in four modes 1. Dual input, balanced-output differential amplifier
2. Dual input, unbalanced-output differential amplifier
3. Single input, balanced-output differential amplifier 4. Single input,Dr. unbalanced-output M differential Ramegowda amplifier When both inputs v1 and v2 are applied, it is said to be dual-input and the output across the collectors of two transistors is taken as balanced-output. When one of the input is applied, it is said to be single-input and the output across the collector of one of the transistor with respect to ground is taken as unbalanced output. All the components in the two emitter biased circuits, which constitute a differential amplifier, must be matched in all respects for proper operation and the magnitude of the supply voltages +Vcc and −VEE must be equal. A multistage amplifier with a desired voltage gain can be formed using a direct connection between successive stages of differential amplifiers. The beauty of the direct connection between stages is that it removes the lower cutoff frequency imposed by the coupling capacitors. In instrumentation systems, differential amplifiers are widely used to compare two input signals. 1.3. ANALYSIS OF DUAL INPUT AND BALANCED OUTPUT DIFFERENTIAL AMPLIFIER5 1.3 Analysis of Dual input and balanced output differen- tial amplifier
The circuit of the dual input balanced output differential amplifier is shown in the Fig 1.3. The two input signals (dual input), v1 , and v2 are applied to the bases of transistors Q1 and Q2. The output vo is measured between the collectors of two transistors, which are at the same dc potential. Because of the equal dc potential at the two collectors with respect to ground, the output is referred to as a balanced output.
ó +VCC
ÿ
RC RC
¡ ¡ ¨vo
Q1 Q2
ÿ R1 ¡ ¡ R2 RE v1 ∼ v2 ∼ ¡
ý© ý©
ñ −VEE Figure 1.3: The dual input balanced output differential amplifier
In the analysis, r-parameters are used. The advantage of r-parameters are,
1. AC analysis of differential amplifiers with r-parameters is simpler, more straight forward, and less cumbersome.
2. There is no need to manipulate the r-parameters at different operating levels except for the re value.
3. The performance equations obtained are easy to remember since they are not complex or lengthy 4. ResultsDr. obtained using r-parameters M Ramegowda compare favorably with the actual results. 1.3.1 DC analysis
In the dc analysis it is customary to determine the operating point values (ICQ and VCEQ). The dc equivalent circuit can be obtained simply by reducing the input signals v1 and v2 to zero. The dc equivalent circuit thus obtained is shown in Fig. 1.4 Since both emitter-biased sections of the differential amplifier are symmetrical (matched in all respects), it require to determine ICQ and VCEQ for only one section. Then these ICQ and VCEQ values can be used for other transistor. By applying KVL to the base-emitter loop of the transistor Q1, we get
R1IB + VBE + 2IERE − VEE = 0 6 CHAPTER 1. THE DIFFERENTIAL AMPLIFIER
ó +VCC
ÿ
RC RC
¡ ¡ ¨vo
Q1 Q2
IB û û IB ÿ
R1 ¡ ¡ R2 ý RE ý
¡
ñ −VEE Figure 1.4: DC equivalent circuit of the dual input balanced output differential amplifier
IC Since IB = β and IC = IE,
R1IC /β + VBE + 2IC RE − VEE = 0
IC (R1/β + 2RE) = VEE − VBE VEE − VBE IC = 2RE + R1/β
Generally R1/β << RE, the above equation can be written as
VEE − VBE IC = (1.2) 2RE
Thus the quiescent current of transistors Q1 and Q2 are independent of the collector resistances. VBE = 0.6V for silicon transistors and VBE = 0.2V for germanium transistors. The collector-emitter voltage of the transistor Q1 is given by
VCE = VC − VE
From the Fig. 1.4 we can write, VC = VCC − IC RC and VE = −VBE. Therefore,
VCE = VCC − IC RC + VBE (1.3)
The quiescent collector current ICQ = IC and collector-emitter voltage VCEQ = VCE can be calculated by using the equations 1.2 and 1.3.
1.3.2 ACDr. analysis M Ramegowda
The ac equivalent circuit can be obtained by reducing VCC and VEE to zero. The ac equivalent circuit of Fig. 1.3 is shown in Fig. 1.5. Applying KVL to loop I and loop II in the Fig. 1.5, we get
v1 = R1ib1 + reie1 + RE(ie1 + ie2) (1.4)
v2 = R2ib2 + reie2 + RE(ie1 + ie2) (1.5)
Since ib is very small compared to ie, the equations 1.4 and 1.5 can be written as
(re + RE)ie1+ REie2 = v1 (1.6)
REie1+(RE + re)ie2 = v2 (1.7) 1.3. ANALYSIS OF DUAL INPUT AND BALANCED OUTPUT DIFFERENTIAL AMPLIFIER7
C1 E1 E2 C2 ÿ ð ú ÿ ò ð ø ÿ ð
re ie1 ie2 re ó B1 ó B2 i i b1 û b2 û I II RC R1 RE ¡ R2 RC ¡ ¡ ¡ ¡
v1 ∼ v2 ∼ ý ©ý ý ©ý ý
Figure 1.5: AC equivalent circuit of difference amplifier
The above equations can be written in the form of matrix equation as
re + RE RE ie1 v1 = (1.8) RE RE + re ie2 v2 Then we can write, ∆ i = 1 (1.9) e1 ∆ ∆ i = 2 (1.10) e2 ∆ where
re + RE RE ∆ = RE RE + re 2 2 = (RE + re) − (RE)
= (RE + re − RE)(RE + re + RE)
= re(2RE + re) (1.11)
v1 RE ∆1 = = v1(RE + re) − v2RE (1.12) v2 RE + re
re + RE v1 ∆2 = = (RE + re)v2 − REv1 (1.13) RE v2
It is considered that the voltage at the collector of Q2 is greater than the voltage at the collector of Q1. Therefore theDr. output voltage is M given by Ramegowda vo = −vc2 − (−vc1)
= vc1 − vc2
= ic1RC − ic2RC
= (ic1 − ic2)RC
Since ic ' ie,
vo = (ie1 − ie2)RC
On substituting the values for ie1 and ie2 by using the equations 1.9 and 1.10, we get ∆ − ∆ v = 1 2 R o ∆ C 8 CHAPTER 1. THE DIFFERENTIAL AMPLIFIER
On substituting the values of ∆, ∆1 and ∆2 by using equations 1.11, 1.12 and 1.13, we get
v1(RE + re) − v2RE − [(RE + re)v2 − REv1] vo = RC re(2RE + re) v1(2RE + re) − (2RE + re)v2 = RC re(2RE + re) (2RE + re)(v1 − v2) = RC re(2RE + re) RC = (v1 − v2) (1.14) re RC vo = vid (1.15) re
where vid = v1 − v2 The gain of the amplifier is v R A = o = C (1.16) vid re Thus a differential amplifier amplifies the difference between the two input signals and gain of the amplifier is independent of RE.
1.3.3 Differential input resistance It is the equivalent resistance measured at either input terminal with other terminal grounded.
v1 Ri1 = (1.17) i b1 v2=0
v1 = (1.18) i /β e1 ac v2=0
v1βac = (1.19) i e1 v2=0
Substituting the values of ie1 from equation 1.9, we get
v1βac∆ Ri1 = ∆1
Substituting the values of ∆ and ∆1 from equations 1.11 and 1.12, we get
v1βacre(2RE + re) Ri1 = vDr.1(RE + re) − v2RE M Ramegowda Since v2 = 0,
v1βacre(2RE + re) Ri1 = v1(RE + re)
Generally, RE re, 2RE + re ' 2RE and RE + re ' RE. Therefore
βacre(2RE) Ri1 = (RE)
Ri1 = 2βacre
Similarly input resistance Ri2 seen from the input signal source v2 is
Ri2 = 2βacre 1.3. ANALYSIS OF DUAL INPUT AND BALANCED OUTPUT DIFFERENTIAL AMPLIFIER9
1.3.4 Output resistance It is the equivalent resistance measured at either output terminal with respect to ground. From the Fig. 1.5, it can be clear that
Ro1 = Ro2 = RC
Dr. M Ramegowda 10 CHAPTER 1. THE DIFFERENTIAL AMPLIFIER
Dr. M Ramegowda Chapter 2
The Operational Amplifier
2.1 Introduction
An operational amplifier is a direct-coupled high-gain amplifier consisting of one or more differ- ential amplifiers followed by a level translator and an output stage. The output stage is generally a push-pull complementary-symmetry pair. An operational amplifier is available as a single integrated circuit package. It is a versatile device that can be used to amplify dc as well as ac input signals. It can be used for computing mathematical functions such as addition, subtraction, multiplication, division, differenciation and integration. Thus it is named as operational amplifier and is abbreviated as op-amp. It can be used for a variety of applications, such as ac and dc signal amplification, active filters, oscillators, comparators, regulators, etc. The block diagram of a typical op-amp is shown in the figure 2.1. It consists of four stages.
1. The input stage: It is the dual input, balanced output differential amplifier. This stage provides voltage gain of the amplifier and also establishes the input resistance of the op- amp.
2. The intermediate stage: It is the dual input, unbalanced output differential amplifier, and is driven by the output of the first stage.
Non-inverting
input úð ÿ ÿ úÿ ÿ úÿ ÿ úÿ ÿ ú Input Intermediate Level shifting Output úð ÿ ÿ úÿ Stage Stage Stage Stage vo Inverting Dr. M Ramegowda input Dual input Dual input Emitter follower Complementary balanced output unbalanced output using constant symmetry push-pull difference amplifier difference amplifier current bias power amplifier Figure 2.1: Block diagram of an op-amp
3. Level translator: Because of the direct coupling between input and intermediate stage, dc voltage at the output of the intermediate stage is well above the ground potential. Therefore, generally, a level translator (shifting) circuit is used after the intermediate stage to shift the dc level at the output of the intermediate stage downward to zero volts with respect to ground.
11 12 CHAPTER 2. THE OPERATIONAL AMPLIFIER
4. Output stage: The final stage is usually a push-pull complementary symmetry amplifier. The output stage increases the output voltage swing and raises the current supplying capability of the op-amp. It also provides low output resistance.
2.2 History of evolution of op-amp
The term operational amplifier was mentioned in a paper written by John R. Ragazzinni with the title Analysis of Problems in Dynamics in 1943. It was around 1947, operational amplifier concepts were originally advanced. In 1952 the first K2 − W tube version general purpose computing op-amp was introduced from George A. Philbrick Researches, and is shown in figure 2.2.
Figure 2.2: K2 − W tube version op-amp
The first solid-state monolithic op-amp, designed by Bob Widlar, in 1963 manufactured by Fairchild Semiconductors.
2.2.1 Development of solid-state monolithic op-amp
• 1963 - µA702,VCC = +12V,VEE = −6V,Ri = 40kΩ,A = 3600. It burns out when it was temporarily shorted.
• 1965 - µA709,VCC = +15V,VEE = −15V,Ri = 400kΩ,A = 4500. It is called first genera- tion op-ampDr. (also MC1537). M These are Ramegowda having number of disadvantages; no short circuit protection, latch-up problem, require external frequency compensation circuit.
• 1967 - LM101, with short circuit protection and frequency compensation.
• 1968 - µA741,VCC = +15V,VEE = −15V,Ri = 2MΩ,A = 200, 000. It is called second generation op-amp (also LM101, LM307, µA748,MC1558).
• 1974 - RC4558/LM324, low power consumption.
• 1975 - CA3130/LF 355, JFET’s at the input stage.
• 1976 - TL084, low bias current and high speed. 2.3. MANUFACTURERS OF OP-AMP ICS 13
• Most of the op-amps have been replaced over time, keeping the same model number, with cleaner and low-noise types.
2.3 Manufacturers of op-amp ICs
Fairchild µA741 National Semiconductor LM741 Motorola MC1471 RCA CA3741 Texas Instruments SN52741 Signetics N5741
Manufacturer Designations Fairchild µA AF National Semiconductor LM, LH, LF, TBA Motorola MC, MFC, RCA CA, CD Texas Instruments SN, ULN, ULS, ULX Intersil ICL, IH Siliconix, Inc. L Signetics N/S, NE/SE, SU Burr-Brown BB
Linear ICs are also available in different classes such as A, C, E, S, and SC. For example, 741, 741A, 741C, 741E, 741S, and 741SC are different versions of the op-amp. 741 is the military grade op-amp and 741C is the commercial grade op-amp. 741A and 741E are the improved versions of 741 and 741C. 741S and 741SC are the military and commercial grade op-amp with higher slew rate.
2.4 Analysis of op-amp circuit
Figure 2.3 shows the internal structure of IC MC1435 op-amp. The first stage is the dual input balanced output differential amplifier with transistors Q1 and Q2. It uses a constant current bias provided by transistorDr.Q and M associated Ramegowda resistors. It has inverting and non-inverting inputs 3 and hence can be driven with two inputs or a single input. This stage provides most of the voltage gain (Ad1 ∼ 100). The second stage is the dual input unbalanced output differential amplifier formed by transistors Q4 and Q5. It uses an emitter bias and it is driven by the outputs of the first differential amplifier. This stage also provides the voltage gain (Ad2 ∼ 20). The overall voltage gain is the
Ad = Ad1 × Ad2
The third stage is an emitter follower composed of transistor Q6 and 15kΩ resistor. It is driven by the single-ended output of the second differential amplifier. It has been noticed that voltage 14 CHAPTER 2. THE OPERATIONAL AMPLIFIER
VCC = +6V
} } ó } } }
| | | | | ÿ | | | | | | | | | | | | | | | I1 ù | | | | |
| 6.7kΩ 6.7kΩ | | | | 3.8kΩ | ¡ | | | | ¡ ÿ | | | | 400Ω | ÿ 3.39V ÿ ¡ }{ ÿ | | Q | | Non-inverting 6 ¡ | | 4.87V | | | input 4.87V | | | | | }{ ð }{ Q1 Q2 | Q4 Q5 | | | | | | | + ù IC7 | | | | | ÿ ÿ | | | | | 4.17V ÿ }{ | | | Q | 7 | | | | |
| | | | | I4 ù - | | | | | ð | | | | | | | | I | IB8 | Inverting 9.1kΩ E6 ù ú | | | | Q | 8 input | | | | | ¡ | | | | output | ÿ ò{ | Q | | | | 3 | | | | | | | | | |
| | | 15kΩ | |
| | | | 2kΩ | ¡ 3.3kΩ 5.5kΩ | | | | ¡ |
| ¡ | | | | ¡ | | | | |
| | | | | IE3 ù | | | | | ÿ | | | | |
| | | | | | | | | |
| | | | | ñ | | VEE = −6V | | | | | | | |
| | | | |
| | | | |
| | | | | { I Stage{ II Stage{ III Stage{ IV Stage {
Figure 2.3: Circuit of IC MC1435 op-amp
at the collector of Q5 increased by 1.47V due to direct coupling of stage I and stage II. The use of emitter follower reduces the dc level of the collector Q6 from 4.87 to 4.17 at the input terminal of the IV stage The fourth stage is the complementary transistor pair composed of Q7 and Q8. It is driven by the output of the emitter follower. It provides low impedance at the output terminal.
The internal structure of IC 741 op-amp is shown in the figure 2.4. 2.5 SchematicDr. symbol M Ramegowda The widely used op-amp symbol is shown in the figure 2.5. v1, v2, vo, +VCC and −VCC are measured with respect to ground. A represents large signal voltage gain.
2.6 IC package types, Pin identification and Tempera- ture ranges
2.6.1 Package types There are three basic types for linear IC packages. 2.6. IC PACKAGE TYPES, PIN IDENTIFICATION AND TEMPERATURE RANGES 15
ð +V Q Q Q Q 8 9 12 13 Q 14 Q ÿ 15 Inverting inputð Q1 Q2 + 27Ω k6
¡ Output ÿ ò Q3 Q4 40kΩ k Non-inverting 5 22Ω k7 input ¡ ð Q 18 ¡ - Q19 50kΩ 30pf R 10 ¡ Q ÿ 21 Q 7 Q20 300Ω ÿ Q Q 16 22 ÿ Q Q Q Offset 5 6 17 Q Q ð 10 11 null ÿ Q 23 50kΩ k3 ¡ 50kΩ k 9 Q24 1kΩ k1 1kΩ k2 R4, 5kΩ k11 50kΩ ¡ 100Ω k8 ¡ ¡ ¡ ¡ ¡ ò -V Offset nullñ
Figure 2.4: Circuit of IC 741 op-amp
1. The flat pack: The chip is enclosed in a rectangular ceramic case with terminal leads extending through the sides.
2. The metal can or transistor pack: The chip is encapsulated in a metal or plastic case.
3. Dual-in-line package (DIP): The chip is enclosed in a plastic or ceramic case as shown in the figure 2.6
Most general purpose op-amps come in 8-pin, 10-pin and 12-pin packages. 8-pin DIP is the most widely used package type, because it can be mounted easily. By keeping notch to the left, pin at the bottomDr. left is counted as M 1 and the sequence Ramegowda runs in anticlockwise as shown in figure 2.7. 2.6.2 Temperature ranges Military temperature range: −55oto + 125oC Industrial temperature range: −20oto + 85oC Commercial temperature range: 0oto + 70oC
2.6.3 Ordering and Device information The ordering information for µA741 mini DIP with commercial temperature range is as follows: 16 CHAPTER 2. THE OPERATIONAL AMPLIFIER
ó +VCC
v2 ð 3 7 þ6 vo A ò
2 ð 4 v1
ñ −VCC Figure 2.5: Schematic symbol for the op-amp with power supply
Figure 2.6: An op-amp IC with DIP
µA741 T C
Device type Package type(DIP-8pin) Commercial The ordering information for a Motorola IC is as follows:
MC34001 P 0o to 70o
Device type Package type(DIP-14pin) Temperature range Device identification is as follows:
Dr. MDevice Ramegowda type
LM741N
H 98 10
National semiconductor Year of manufacturing Week of the year 2.7. POWER SUPPLIES FOR OP-AMP 17 8 7 6 5
NC +VCC Output Offset null
µA741C
Offset Inv Non-inv null Input Input −VEE 1 2 3 4
Figure 2.7: Pin configuration of 741 IC
2.7 Power supplies for op-amp
Symbolically op-amp is represented with pin numbers and power supply as shown in the figure 2.5. Two power supplies required for op-amp IC are usually equal in magnitude (+15V and -15V) and these voltages must be referenced to a common ground point. These voltages can be applied by using two sources or by using single source as shown in the figure 2.8
Vs +VCC = V1 +VCC = ò ÿ ò 2 V C 1 R ÿ ý ¡ÿ ÿ ý ÿ VS
R V2 C ¡ ò ÿ ò V −VEE = V2 s −VEE = 2 Vs +VCC = D Vs ÿ ò 2 1 +VCC = ¢ ÿ ò 2 R ZD1 C §
ÿ ø ý VS ÿ ý
VS R ¡ C ZD2 § D2 ÿ ò ÿ ò −V = Vs −V = Vs Dr. MEE 2 RamegowdaEE 2 Figure 2.8: Power supplies for op-amp 18 CHAPTER 2. THE OPERATIONAL AMPLIFIER
Dr. M Ramegowda Chapter 3
Op-amp parameters
3.1 Input Parameters
1. Input offset voltage (Vio): Due to circuitry imbalance, even with zero input voltage there is some output dc voltage, called output offset voltage. So it is required to maintain zero output voltage to use the op-amp for any application. The dc voltage that must be applied to one of the input pins to maintain zero output voltage is called input offset voltage. For an ideal op-amp, the output offset voltage is zero.
ó +15V 3 ý 7 10kΩ þ6 Vo = 0V Vdc1 A ò
ý 2 4 10kΩ −15V Vdc2 ñ
Figure 3.1: Input offset voltage, Vio = Vdc1 − Vdc2
2. Input offset current (Iio): This is the difference of the two input bias currents when the output voltage is zero.
+15V IB1 ó ý ú 3 7 Vo = 0V þ6 ò A
2 ý ú 4 Dr. M Ramegowda IB2 ñ −15V
Figure 3.2: Input offset current, Iio = IB1 − IB2
3. Input bias current (IB): This is the average of the currents flowing into both inputs. Ideally, the two input bias currents are equal. I + I I = B1 B2 B 2
4. Input voltage range (vcm): It is the range of common-mode input voltage
19 20 CHAPTER 3. OP-AMP PARAMETERS
5. Input resistance (Ri): The resistance at either input terminal with the remaining input terminal grounded.
3.2 Output Parameters
1. Output resistance (Ro): It is the resistance at output terminal of the op-amp.
2. Output short-circuit current (Iosc): This is the maximum output current that the op-amp can deliver to a load.
3. Output voltage swing (vo max): This is the maximum output voltage that the op-amp can supply without saturation or clipping.
3.3 Dynamic Parameters
1. Open-loop voltage gain (A): The output to input voltage ratio of the op-amp without external feedback. v A = o vid
2. Closed-loop voltage gain (AF ): The output to input voltage ratio of the op-amp with external feedback.
vo AF = vi
3. Slew rate (SR): The time rate of change of the output voltage with the op-amp circuit having a voltage gain of unity. It is expressed in volt per microseconds.
dv SR = o V/µs dt
3.4 Other Parameters
1. SupplyDr. current (Is): This M is the Ramegowda current that the op-amp will draw from the power supply.
2. Common-mode rejection ratio (CMRR): It is the ratio of the differential voltage gain to the common-mode voltage gain, usually expressed in decibels(dB). It is the measure of the ability of the op-amp to reject signals that are simultaneously present at both inputs.
A CMRR = d Acm
3. Unity gain bandwidth: It is the bandwidth of the op-amp when the voltage gain is unity. It is also called gain-bandwidth product. 3.5. ABSOLUTE MAXIMUM PARAMETERS 21 3.5 Absolute Maximum Parameters
These are the parameters that the op-amp can safely tolerate without the possibility of destroy- ing it.
1. Supply voltage (Vs): The maximum voltage that can be safely used to feed the op-amp.
2. Power dissipation (Pd): It is the maximum power that the op-amp is able to dissipate at a given temperature.
3. Differential input voltage (vid): This is the maximum voltage that can be applied across the inverting and non-inverting inputs.
4. Common-mode voltage (vicm): The maximum input voltage that can be simultaneously applied to both inputs with using a single source with respect to ground.
5. Operating Temperature (Ta): This is the ambient temperature range for which the op-amp will operate within the manufacturer’s specifications.
6. Output short circuit duration: This is the amount of time that an op-amp’s output can be short circuited to either supply voltage.
3.6 Offset voltage compensating networks
There are number of ways to null the output offset voltage.
1. By connecting 10kΩ potentiometer between pin 1 and pin 5 with center taping to pin 4 as shown in the figure 3.3. By adjusting the resistance of the potentiometer, output offset voltage can be reduced to zero.
ó +VCC 3 7 Vo = 0 þ6 ò 741C
5 2 4 1 ñ −VCC ý ý ù Dr. M Ramegowda 10k Figure 3.3:
2. When op-amp is used in inverting mode, by connecting a resistance called offset minimizing resistance ROM = R1 k RF between the inverting input terminal and ground as shown in figure 3.4(a), offset voltage can be minimized.
3. By connecting 10kΩ potentiometer between pin 4 and pin 7 with center taping to pin 2 through a resistance as shown in the figure 3.4(b). By adjusting the resistance of the potentiometer output offset voltage can be reduced to zero. 22 CHAPTER 3. OP-AMP PARAMETERS
RF
ó +VCC +V R1 ó CC 2 3 ý 7 7 v V = 0 ÿ6 o 6 o ò þ ò 741C A R b 3 ø 2 4 Ra 4 ¡ vi ∼ −VCC R ñ −VCC c © ñ ¡
ROM = R1 k RF
¡ ý ý (a) (b) Figure 3.4: 3.7 The ideal op-amp
An ideal op-amp would exhibit the following electrical characteristics 1. Infinite voltage gain A.
2. Infinite input resistance Ri, so that almost any signal source can drive it and there is no loading of the preceding stage.
3. Zero output resistance Ro, so that the output can drive an infinite number of other devices. 4. Zero output voltage when input voltage is zero. 5. Infinite bandwidth, so that any frequency signal from 0 to ∞Hz can be amplified without attenuation. 6. Infinite common-mode rejection ratio, so that the output common-mode noise voltage is zero. 7. Infinite slew rate, so that output voltage changes occur simultaneously with input voltage changes. There are practical op-amps that can be made to approximate some of these characteristics using negative feedback arrangement. In particular, the input resistance, output resistance and bandwidth can be brought close to ideal values by this method.
3.8 IdealDr. voltage M transfer Ramegowda curve
By assuming output offset voltage to be zero, the graphic representation of the equation
vo = Avid = A(v1 − v2) is called an ideal voltage transfer curve. The output voltage vo is plotted against input difference voltage vid, keeping gain A constant. The output voltage cannot exceed the positive and negative saturation voltages. These satu- ration voltages are specified by an output voltage swing rating of the op-amp for given values of supply voltages. This means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter output voltage remains constant, as shown in figure 3.5. 3.9. EQUIVALENT CIRCUIT OF AN OP-AMP 23
vo
+Vsat < +VCC
v1 > v2
Slope = A
−vid +vid
v1 < v2
−Vsat < −VEE
Figure 3.5: Ideal voltage transfer curve
3.9 Equivalent circuit of an op-amp
The equivalent circuit is useful in analyzing the basic operating principles of op-amp and in observing the effects of feedback arrangements. The equivalent circuit of op-amp is shown in figure 3.6. From the equivalent circuit the output voltage is given by
+VCC
v2 −
Ro vo = Avid vid Ri ∼ Avid Dr.v1 M+ Ramegowda
−VEE Figure 3.6: Equivalent circuit of op-amp
vo = Avid = A(v1 − v2) (3.1)
That is the op-amp amplifies the difference between the two input voltages. Therefore the polarity of the output voltage depends on the polarity of the difference voltage. 24 CHAPTER 3. OP-AMP PARAMETERS 3.10 Features of IC 741 op-amp
The IC 741 having following features
1. Internal Frequency Compensation: Generally in an amplifier, when input signal frequency increases, gain of the amplifier decreases and phase shift between input and output in- creases. This change in phase shift is internally compensated in the op-amp by the inter- nally integrated capacitor and internal stray capacitance.
2. Short Circuit Protection.
3. Offset voltage null capability.
4. Excellent temperature stability.
5. High input voltage range.
6. No latch-up problem. (Latch-up problem means that the output voltage is latched up to some value and then op-amp fails to respond to change in input signal.
3.11 Parameters of IC µA741
The µA741 is a high performance operational amplifier with high input impedance, low output impedance, high open loop gain, internal frequency compensation, high common mode range and exceptional temperature stability. The µA741 is short-circuit protected and allow to null the offset voltage. The µA741 is manufactured by Fairchild Semiconductor. The maximum values of the parameters of µA741C op-amp is given in the table 3.1.
Parameter Value Input offset voltage 6 mV Input offset current 200 nA Input bias current 500 nA Input resistance 2 M Input capacitance 1.4µf Offset voltage adjustment range ±15 mV Input voltage range. ±13 V CMRR 90 dB Dr.Large M signal voltage Ramegowda gain 200,000 Output voltage swing ±14 V Output resistance 75 Ω Output short circuit current 25 mA Supply current 2.8 mA Power consumption 85 mW
Table 3.1: Parameters of µA741C op-amp at 25oC Chapter 4
Open-loop and closed-loop op-amps
4.1 Open-loop configuration
Amplifiers with no feedback are called the open-loop amplifiers. The op-amp in open-loop configuration is simply functions as a high-gain amplifier. There are three open-loop configurations of op-amp. 1. Differential amplifier 2. Inverting amplifier 3. Non-inverting amplifier
4.1.1 The differential amplifier
Figure 4.1 shows the open-loop differential amplifier with input signals vi1 and vi2, applied to the non-inverting and inverting input terminals respectively. Since the op-amp amplifies the difference between the two input signals, this configuration is called the differential amplifier.
ó +VCC
v1 û R1 vo þ ò vid A v2 ù R2
ñ −VEE vi1 ∼ ∼ vi2 Dr.ý© Mý© Ramegowda Figure 4.1: Open-loop differential amplifier
The op-amp is a versatile device because it amplifies both ac and dc input signals. This means that vi1 and vi2 could be either ac or dc voltages. The source resistances R1 and R2 are normally negligible compared to the input resistance Ri. Therefore, the voltage drops across these resistors can be assumed to be zero, which then implies that v1 = vi1 and v2 = vi2. Therefore the output voltage can be obtained as
vo = Avid = A(v1 − v2) = A(vi1 − vi2) In open-loop configuration of op-amp, A is commonly referred to as open-loop gain.
25 26 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
4.1.2 The inverting amplifier
Figure 4.2 shows the open-loop inverting amplifier in which input signal vi is applied to the inverting input terminal. The non-inverting input terminal is grounded.
ó +VCC v1 û v þ o ò vid A
v2 ù R ñ −VEE vi ∼ ý ©ý
Figure 4.2: Open-loop inverting amplifier
Since v1 = 0V and v2 = vi, the output voltage can be obtained as
vo = A(v1 − v2) = −Avi
The negative sign indicates that the output is out of phase with respect to input and hence it is called inverting amplifier.
4.1.3 The non-inverting amplifier
Figure 4.3 shows the open-loop non-inverting amplifier in which input signal vi is applied to the non-inverting input terminal. The inverting input terminal is grounded. Since v1 = vi and
ó +VCC
v1 û Ri vo þ ò vid A
ù v2 ∼ vi ©ý ý
ñ −VEE Dr.Figure M 4.3: Open-loop Ramegowda non-inverting amplifier v2 = 0V , the output voltage can be obtained as
vo = A(v1 − v2) = Avi
There is no negative sign in the output voltage expression, means that the output is in phase with the input and hence it is called non-inverting amplifier. Note: In open-loop configuration of op-amp vo = Avid. Since A is very large, any input signal slightly greater than zero drives the output to saturation level. Thus when the op-amp is operated in open-loop configuration, the output is either positive or negative saturation level and the frequency response is very poor shown in figure 4.4. So the open-loop configuration of op-amp is not used in linear application. 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 27 90
A(dB) 60
30
0
−30 1 10 102 103 104 105 106 f (Hz)
Figure 4.4: Frequency response of open-loop op-amp
4.2 Closed-loop configurations of op-amp
Amplifiers with feedback are called the closed-loop amplifiers.
4.2.1 Voltage-series feedback amplifier
Figure 4.5 shows the voltage series feedback amplifier in which input signal vi is applied to the non-inverting input terminal. The inverting input terminal is grounded through a resistance R1. The feedback circuit is composed of two resistors R1 and RF , and the feedback voltage is applied to inverting input terminal. This configuration is commonly called closed-loop non- inverting amplifier. Open-loop voltage gain A, closed-loop voltage gain AF and gain of the
ó +VCC
ÿ v1 û vo þ ò vid A
ÿù v2 Dr. M Ramegowda ñ −VEE vi ∼ }xyyyyyyyyyy z} { © } ÿ | RL | | û ¡ | RF |
vf | | | R1 | | | ¡ | | ù ÿý | |
| ø| {xyyyyyyyyyy z{ Feedback circuit Figure 4.5: Closed-loop non-inverting amplifier 28 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
feedback circuit β are given by
v A = o vid vo AF = vi v β = f vo
Figure 4.6 shows the simplified diagram of voltage series feedback amplifier. The input signal to the amplifier is
vid = vi − vf
That is, the feedback voltage opposes the input signal vi. Thus the feedback becomes negative. Hence the closed-loop non-inverting amplifier is the negative voltage series feedback amplifier
RF
ó +VCC R1 v ÿ f û vo ÿ ò vi − vf = vid A
ÿù vi ñ −VEE vi ∼ ©
ý ý
Figure 4.6: Closed-loop non-inverting amplifier
Closed-loop voltage gain From the figureDr. 4.6 we can write M Ramegowda
vid = (v1 − v2) = (vi − vf )
Therefore
vo = Avid = A(vi − vf ) (4.1)
where A is the open-loop gain. Again from the figure 4.6 we can write
voR1 vf = (4.2) R1 + RF 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 29
On substituting for Vf in equation 4.1, we get voR1 vo = A vi − R1 + RF AvoR1 vo + = Avi R1 + RF AR1 vo 1 + = Avi R1 + RF R1 + RF + AR1 vo = Avi R1 + RF
A(R1 + RF ) vo = vi R1 + RF + AR1 Therefore, the closed-loop gain AF can be obtained as
vo A(R1 + RF ) AF = = (4.3) vi R1 + RF + AR1 5 ∼ Generally the open-loop gain A is very large (∼ 10 ). AR1 >> R1+RF and R1+RF +AR1 = AR1 Thus A(R1 + RF ) AF = AR1 R1 + RF RF AF = = 1 + (4.4) R1 R1 That is gain of the voltage series feedback amplifier depends on the ratio of the external resistors R1 and RF . By setting the ratio R1 and RF gain of the amplifier can be controlled.
Closed-loop voltage gain in terms of feedback factor The feedback factor (gain of the feedback circuit) is given by v β = f vo
On substituting for vf by using equation 4.2, R β = 1 (4.5) R1 + RF Comparing equations 4.4 and 4.5, we get 1 β = (4.6) AF That is, gainDr. of the feedback circuit M is the Ramegowda reciprocal of the closed-loop voltage gain. For given values of R1 and RF the values of A and β are fixed. From the equation 4.3 we can write
A(R1 + RF ) AF = AR1 R1 + RF 1 + R1+RF A AF = 1 + AR1 R1+RF By using equation 4.5, we get A A = (4.7) F 1 + Aβ 30 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
Input resistance The input resistance with feedback is
vi vi viRi RiF = = = ii vid/Ri vid Since v v = o id A Rivi vi ARi RiF = = ARi = (4.8) vo/A vo AF
On substituting for AF from equation 4.7, we get
RiF = Ri(1 + Aβ) (4.9) Thus the input resistance of op-amp increases with feedback.
Output resistance figure 4.7 shows the equivalent circuit of op-amp with negative feedback. The output impedance can be defined as
vo RoF = (4.10) io +VCC
v1 +
Ro io vo vid Ri ∼ Avid
v2 −
−VEE
Dr. M RamegowdaRF R1
Figure 4.7: Equivalent circuit of op-amp with feedback
By applying Kirchoff’s voltage law to the output stage in the figure 4.7, we can write
−Avid − Roio + vo = 0 (4.11) vo − Avid io = (4.12) Ro 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 31
Since
vid = vi − vf
To measure output impedance vi should be reduced to zero. Therefore,
vid = −vf = −βvo
On substituting for vid in equation 4.11,
vo + Aβvo vo(1 + Aβ) io = = (4.13) Ro Ro On combining equations 4.10 and 4.13, we get R R = o (4.14) oF 1 + Aβ Thus output resistance of the op-amp decreases with feedback.
Bandwidth
If fo is the lower cutoff frequency called break frequency without feedback and A is the open-loop gain, the gain bandwidth product is called unity gain bandwidth. It is defined as the frequency at which gain of the amplifier is unity. That is
UGB = A fo (4.15)
If fF is the break frequency of op-amp with feedback and AF is the closed-loop gain, we can write
UGB = AF fF (4.16) On equating the equations 4.15 and 4.16,
A fo = AF fF Afo fF = AF
On substituting for AF by using equation 4.7
fF = fo(1 + Aβ) (4.17) That is bandwidth of the op-amp increases with feedback. The frequency response curve of closed-loop amplifierDr. is shown inM the figure Ramegowda 4.12 4.2.2 Voltage shunt feedback amplifier
Figure 4.8 shows the voltage shunt feedback amplifier in which input signal vi is applied to the inverting input terminal. The non-inverting input terminal is grounded. The feedback signal is applied to inverting input through feedback resistor RF . This configuration is commonly called closed-loop inverting amplifier. The input signal to the amplifier is
vid = v1 − v2 = 0 − v2 = −(vi − vf ) = vf − vi
That is the feedback signal opposes the input signal vi. Thus the feedback becomes negative. From the figure 4.8 we can see that vf acting parallel vi. Hence the closed-loop inverting amplifier is the negative voltage shunt feedback amplifier. 32 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
ó +VCC
IB1 ý ÿú v1 þû vo ò vid A
v2 ÿÿú ù iB2 R1 −VEE ñ i i i û F ù }xyyyyyyyyyy z} }{ | RL vi ∼ | | ¡ û | RF | © | |
vf | | | |
| | ÿù ÿ | |
| | ø ý {xyyyyyyyyyy z{ Feedback circuit
Figure 4.8: Closed-loop inverting amplifier
Closed-loop voltage gain
Figure 4.9 shows the simplified diagram of voltage shunt feedback amplifier. Open-loop voltage gain A, closed-loop voltage gain AF and gain of the feedback circuit β are given by
v A = o vid vo AF = vi v β = f vo
From the figure 4.9, we can write
ii = iF + iB2
Since input impedance Ri of op-amp is very high, input bias current is very small and can be neglected compare to iF . Therefore, ii = iF Dr. M Ramegowda(4.18) Again from the figure 4.9, equation 4.18 can be written as
v − v v − v i 2 = 2 o (4.19) R1 RF
Since
vo = Avid = A(v1 − v2) = −Av2
v v = − o 2 A 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 33
RF
iF û ó +VCC R1 iB2 ú ÿú v2 ii û v ÿ o ò vid A iB1 ùÿú v1 vi ∼ −VEE © ñ
ý ý
Figure 4.9: Closed-loop inverting amplifier
On substituting the value of v2 in equation 4.19, v + (v /A) −(v /A) − v i o = o o R1 RF vi vo 1 + A + = −vo R1 AR1 ARF v v R + R + AR i = − o F 1 1 R1 A R1RF ARF vi vo = − RF + R1 + AR1
The closed-loop gain AF can be obtained as
vo ARF AF = = − (4.20) vi R1 + RF + AR1 5 ∼ Generally the open-loop gain A is very large (∼ 10 ). AR1 >> R1+RF and R1+RF +AR1 = AR1 Thus
ARF RF AF = − = − (4.21) AR1 R1 That is, gain of the voltage shunt feedback amplifier depends on the ratio of the external resistors R1 and RF . The ratio of R1 and RF can be set to any value, even to less than one. Because of this property, closed-loop inverting amplifier can be found in majority of the applications. The negative signDr. shows that the output M is inverted. Ramegowda
Closed-loop voltage gain in terms of feedback factor From the equation 4.20 we can write
ARF AF = − AR1 R1 + RF 1 + R1+RF AR /(R + R ) = − F 1 F 1 + AR1 R1+RF AK = − (4.22) 1 + βA 34 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
where β = R1 is the gain of the feedback circuit and K = RF is called voltage attenuation R1+RF R1+RF factor On comparing equations 4.22 and 4.7, we can get AF of the inverting amplifier = KAF of the non-inverting amplifier. Since K < 1, the magnitude of the closed-loop gain of the inverting amplifier is less than the closed-loop gain of the non-inverting amplifier.
Inverting input terminal at virtual ground In the figure 4.9 non-inverting terminal is grounded and the input signal is applied to inverting terminal through R1. The input voltage in terms of gain can be written as v v = o id A Since open loop gain A is very large,
vid = v1 − v2 ∼ 0
Therefore
v1 ∼ v2
Since v1 is at grounded potential, v2 is approximately at grounded potential. Therefore inverting terminal is said to be virtually grounded.
Input resistance The feedback resistor is connected between input and output terminal. When the op-amp is designed with high AF , the feedback significantly changes the input impedance of the op-amp. To find the input impedance the feedback resistor is split into two component using Miller’s theorem as follows. From the figure 4.9, we can write
v2 − vo iF = (4.23) RF Since
vo = Avid = A(v1 − v2) = −Av2 Therefore Dr. M Ramegowda v2 + Av2 iF = RF (1 + A)v2 iF = RF v R 2 = F iF 1 + A
The ratio v2/iF is the component of the RF seen from the input side of the op-amp. Since v v = (v − v ) = −v = o (4.24) id 1 2 2 A 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 35
On substituting for v2 in equation 4.23, we get
(−vo/A) − vo iF = RF vo(1 + A) iF = − ARF
vo ARF = iF 1 + A
The ratio vo/iF is the component of the RF seen from the output side of the op-amp. The figure 4.10 shows the circuit consisting of two Miller components of the RF . From the figure
+VCC
v2 −
Ro io vo vid Ri ∼ Avid v1 +
RF R1 1+A
−VEE
∼ vi RF A 1+A
Figure 4.10: Inverting amplifier with Millerized feedback resistor 4.10, the inputDr. resistance with M feedback can Ramegowda be written as R R = R + F kR iF 1 1 + A i
Since A is very large,
R R F → 0, and F kR → 0 1 + A 1 + A i
Therefore,
RiF = R1 36 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
Output resistance Figure 4.11 shows the equivalent circuit of op-amp with negative feedback. The output impedance can be defined as vo RoF = (4.25) io
+VCC
v1 +
Ro io vo vid Ri ∼ Avid
v2 −
−VEE
RF R1
Figure 4.11: Equivalent circuit of op-amp with feedback
By applying Kirchoff’s voltage law to the output stage in the figure 4.11, we can write
−Avid − Roio + vo = 0 (4.26) vo − Avid io = (4.27) Ro Since vid = viDr.− vf M Ramegowda To measure output impedance vi should be reduced to zero. Therefore,
vid = −vf = −βvo
On substituting for vid in equation 4.26,
vo + Aβvo vo(1 + Aβ) io = = (4.28) Ro Ro On combining equations 4.25 and 4.28, we get R R = o (4.29) oF 1 + Aβ Thus output resistance of the op-amp decreases with feedback. 4.2. CLOSED-LOOP CONFIGURATIONS OF OP-AMP 37
Bandwidth
If fo is the lower cutoff frequency (called break frequency) without feedback and A is the open- loop gain, the gain bandwidth product is called unity gain bandwidth. It is defined as the frequency at which gain of the amplifier is unity. That is
UGB = A fo (4.30)
If fF is the break frequency of op-amp with feedback and AF is the closed-loop gain, we can write
UGB = AF fF (4.31)
On equating the equations 4.30 and 4.31,
A fo = AF fF Afo fF = AF Since A A = F 1 + Aβ
fF = fo(1 + Aβ) That is bandwidth of the op-amp increases with feedback. The frequency response curve of closed-loop amplifier is shown in the figure 4.12. For single break frequency op-amp, UGB f = o A Then UGB f = (1 + Aβ) F A By using equation 4.22, we can write
UGB(K) fF = Dr.AF M Ramegowda
RF AK where K = and AF = R1+RF 1+βA 38 CHAPTER 4. OPEN-LOOP AND CLOSED-LOOP OP-AMPS
60
A(dB) 40
20
0
−20 1 10 102 103 104 105 106 f (Hz)
Figure 4.12: Frequency response of closed-loop op-amp Dr. M Ramegowda Chapter 5
Applications of op-amp
Op-amp is used for variety of applications. These applications are classified into following categories. 1. General linear applications 2. Filter and oscillator applications 3. Comparator and detector applications 4. Special integrated circuit applications 5. Selected detector applications
5.1 General linear applications
When output signal of op-amp is of the same nature of the input signal and varies in accor- dance with the input signal with the limits set by the saturation level and slew rate, then the applications of op-amp in such conditions are called linear applications. AC amplifier, dc amplifier, summer, subtractor, instrumentation amplifier, current to voltage converter, voltage to current converter, integrator, differentiator, etc., are some of the examples for linear applications of op-amp.
5.1.1 Summing, Scaling and Averaging amplifiers The summing, scaling and averaging amplifiers can be constructed by using both inverting and non-inverting mode of op-amp. The figure 5.1 shows the inverting configuration of op-amp with three inputs Dr.va, vb and vc. Depending M on Ramegowdathe relationship between RF and input resistors R1, R2 and R3, the circuit can be used as summing, scaling and averaging amplifier. ROM is used to minimize the effect of input bias current on the output offset voltage. By applying Kirchoff’s laws to the inverting terminal, we can write
ia + ib + ic = iF + iB2
Since Ri is very large, iB1 ' 0, iB2 ' 0 and v1 ' v2 ' 0. Therefore,
ia + ib + ic = iF v v v v a + b + c = − o Ra Rb Rc RF RF RF RF vo = − va + vb + vc (5.1) Ra Rb Rc
39 40 CHAPTER 5. APPLICATIONS OF OP-AMP
RF R va a ð ú iF ia û ó +VCC Rb vb iB2 ú v2 ð ÿ ÿú ib û vo R v ÿ ò vc c id ð ú A iB1 = 0 ic ùÿú v1
ñ −VEE ROM = (RakRbkRckRF )
¡
ý
Figure 5.1: Summing, scaling or averaging amplifier
R R R If F 6= F 6= F Ra Rb Rc Then each input voltage is amplified by different factor. That is each input voltage is weighted differently at the output. Then the circuit shown in the figure 5.1 is called scaling or weighted amplifier.
If Ra = Rb = Rc = RF , then the equation 5.1, becomes
vo = − (va + vb + vc)
That is, the output is equal to negative sum of all the inputs. Hence the circuit shown in the figure 5.1 is called summing amplifier.
If Ra = Rb = Rc = R, then the equation 5.1, becomes
R v = − F (v + v + v ) o R a b c
R 1 If F = R 3 v + v + v v = − a b c o 3 That is the outputDr. is the average M of all the Ramegowda inputs. Hence the circuit shown in the figure 5.1 is called averaging amplifier.
5.1.2 Voltage to current converter Circuits in which output load current is proportional to input voltage are called voltage to current converters. The figure 5.2 shows the circuit of a voltage to current converter with a grounded load. The circuit behaves as the non-inverting amplifier with input VA, and equal input and feedback resistors. The output voltage of the amplifier is
R V = 1 + V = 2V (5.2) o R N N 5.1. GENERAL LINEAR APPLICATIONS 41
By applying Kirchoff’s current equation at node N, we get
I1 + I2 = IL V − V V − V i N + o N = I R R L Vi − 2VN + Vo = ILR
2VN = Vi + Vo − ILR (5.3)
R R ÿ
ý ó +VCC
v ÿ o A ÿ ò
ú I1 R −VEE ñ Vi VN ÿ ø I2 R ý ¡ RL
IL ýù
Figure 5.2: Voltage to current converter with grounded load
On combining equations 5.2 and 5.3, we get
Vo = Vi + Vo − ILR
Vi = ILR V I = i (5.4) L R
That is, load current IL depends on the input voltage Vi. Thus the circuit behaves as voltage to current converter. This circuit can be used in testing devices such as zeners and LEDs forming a grounded load provided that the load resistor ≤ R. 5.1.3 CurrentDr. to Voltage M converter Ramegowda Circuits in which output voltage is proportional to input current are called current to voltage converters. The figure 5.3 shows the circuit of a current to voltage converter with a passive transducer (Photocells or Photo diodes). It requires external voltage Vdc. For active transducer like photo voltaic cells (Solar cells) the dc voltage Vdc can be eliminated. Since strength of the current generated in the photo devices is very small, the op-amp with very low bias current such as µA741 is used (IB = 3nA). From the figure 5.3, we can write
Vo = −IoRF where Io = Vdc/R and R is the resistance of the transducer. That is the output voltage is proportional to the input current. Hence the circuit work as a current to voltage converter. 42 CHAPTER 5. APPLICATIONS OF OP-AMP
C ' 100pf
Passive Transducer R Io F ú ÿ ú
Io IB1 ' 0 ù ó +VCC
Vdc ý Vo ÿ ÿ A ò
IB2 ' 0 û −VEE ý ñ
Figure 5.3: Current to voltage converter
5.1.4 The Integrator A circuit in which the output voltage waveform is the integral of the input voltage wave form is called the integrator or integrating amplifier. In the inverting op-amp, if the feedback resistor RF is replaced by a capacitor CF , then the circuit acts as an integrator and is shown in the figure 5.4. From the figure 5.4 we can write
CF
iF û ó +VCC R1 iB2 v2 ú ÿú ii v ÿ o ò A iB1 ÿú v1 vi ∼ −VEE © ñ
ý ý Dr. MFigure 5.4: Ramegowda Integrating amplifier ii = iF + iB2
Since input impedance Ri of op-amp is very high, input bias current is very small and can be neglected compare to iF . Therefore,
ii = iF dQ i = F i dt d i = [C (v − v )] i dt F 2 o vi − v2 d = CF (v2 − vo) R1 dt 5.1. GENERAL LINEAR APPLICATIONS 43
Since A is very large, v1 ' v2 ' 0. Therefore,
vi d = CF (−vo) R1 dt
On integrating the equation both side with respect to t, we get
Z t Z t vi d dt = −CF (vo)dt 0 R1 0 dt Z t vi dt = −CF vo + K 0 R1 1 Z t K Therefore, vo = − vidt + R1CF 0 CF Z t 1 0 or vo = − vidt + K (5.5) R1CF 0
0 where K is the constant of integration and is proportional to the value of output voltage vo at time t = 0s. That is the output of integrator is directly proportional to the negative integral of the input voltage and inversely proportional to the time constant R1CF . So the sine wave input will produce the cosine wave output and the square wave input will produce the triangular wave output as shown in figure 5.5.
Since XCF decreases linearly with the frequency, the output of the integrator decreases linearly as shown in the figure 5.7. Therefore, in the practical integrator shown in figure 5.6, a resistor RF is connected across the feedback capacitor CF . Thus, RF limits the low-frequency gain and also minimizesDr. the variations inM the output Ramegowda voltage. The frequency response of the practical integrator is also shown in 5.7. In this figure, fb is the frequency at which the gain is 0dB and is given by
1 fb = 2πR1CF 44 CHAPTER 5. APPLICATIONS OF OP-AMP
Input wave form Input wave form 1V 1V
0V 0V T T 3T T T T 4 2 4 2
1V 1V
0V
1 ω V 0V
2 ω V −0.5V Output wave form Output wave form
Figure 5.5: Input and output wave forms of an integrator (R1CF = 1 and vi = 1V )
In the figure 5.7 the gain is constant for frequencies f to fa and after fa the gain decreases at a rate of 20dB/decade. In other words, between fa and fb the circuit of figure 5.6 acts as an integrator. fa is called the gain limiting frequency and is given by 1 fa = 2πRF CF
Generally, the value of fa and in turn R1CF and RF CF values should be selected such that fa < fb The integrator is most commonly used in analog computers, analog to digital converters (ADC) and inDr. signal wave shaping M circuits. Ramegowda 5.1. GENERAL LINEAR APPLICATIONS 45
RF
CF ÿ ÿ
iF û ó +VCC R1 iB2 v2 ú ÿú ii v ÿ o ò A iB1 ÿú v1 vi ∼ −VEE © ñ
ROM ¡
ý ý
Figure 5.6: Practical integrating amplifier
100 Basic integrator response
80 Practical integrator response A(dB) 60 40Dr. M Ramegowda 20
f f 0 a b 1 10 102 103 104 105 106 f (Hz)
Figure 5.7: Frequency response of integrator 46 CHAPTER 5. APPLICATIONS OF OP-AMP
5.1.5 The differentiator If the output waveform of an amplifier is the derivative of the input waveform, then it is called differentiation amplifier or differentiator. The differentiator may be constructed from a basic inverting op-amp by replacing input resistor R1 by a capacitor C1 as shown in the figure 5.8.
RF
iF û ó +VCC C1 iB2 ú ÿú v2 ii v ÿ o ò A iB1 ÿú v1 vi ∼ −VEE © ñ
ROM ¡
ý ý
Figure 5.8: Differentiating amplifier
From the figure 5.8 we can write
ii = iF + iB2
Since input impedance Ri of op-amp is very high, input bias current is very small and can be neglected compare to iF . Therefore,
ii = iF dQ = i dt F d v2 − vo C1 (vi − v2) = dt RF
Since A is very large, v1 ' v2 ' 0.
dvi vo Therefore, C1 = − dt RF dvi Dr.vo = −C M1RF Ramegowda dt
Thus the output Vo is equal to C1RF times the negative instantaneous rate of change of the input voltage vi. Since the differentiator performs the reverse of the integrator’s function, a cosine wave input will produce a sine wave output, or a triangular input will produce a square wave output and sine wave input will produce a cosine wave output, or a square wave input will produce pulsed output. The gain of the basic differentiator increases with increase in frequency at a rate of 20dB/decade because the input impedance XC1 decreases with increase in frequency. This makes the circuit unstable and also the circuit is very susceptible to high frequency noise. In the amplified output, this noise can completely override the differentiated output signal. Both the stability and the high frequency noise problems can be corrected by the addition of two components; R1 and CF , 5.1. GENERAL LINEAR APPLICATIONS 47
RF
CF ÿ ÿ
iF û ó +VCC C1 R1 iB2 ú ÿú v2 ii v ÿ o ò A iB1 ÿú v1 vi ∼ −VEE © ñ
ROM
¡
ý ý
Figure 5.9: Practical differentiating amplifier
as shown in figure 5.9. This circuit is the practical differentiator. The frequency response of basic and practical differentiator circuits is shown in the figure 5.11. Frequency up to fb, the gain increases at 20dB/decade and after fb the gain decreases at 20dB/decade. This 40dB/decade change in the gain is caused by the combination of R1C1 and RF CF . The gain limiting frequency fb is given by 1 1 fb = = 2πR1C1 2πRF CF
The circuit of figure 5.9 works fairly as a differentiator when input signal frequency f ≤ fa, where fa is the frequency at which the gain is 0dB and is given by 1 fa = 2πRF C1
Generally, the value of fb and in turn R1C1 and RF CF values should be selected such that
fa < fb < fc
where fc = unity gain-bandwidth. The differentiatorDr. is most commonly M used Ramegowda in wave shaping circuits to detect high frequency components in an input signal and also as a rate-of-change detector in FM modulators. 48 CHAPTER 5. APPLICATIONS OF OP-AMP
Input wave form Input wave form 1V 1V
0V 0V 3T T T 3T T T T 2 4 2 4 2
1V 1V
0.94V 2V
0V 0V
0.94V −2V Output wave form Output wave form
Figure 5.10: Input and output wave forms of a differentiator(RF C1 = 150µs and vi = 1V )
60 Basic differentiator response
A(dB) 40 20Dr. M RamegowdaPractical differentiator response 0
f f −20 a b 1 10 102 103 104 105 106 f (Hz)
Figure 5.11: Frequency response of differentiator 5.2. FILTERS 49 5.2 Filters
An electric filter is a frequency selective circuit that passes a specified band of frequencies and attenuates signals of other frequencies. Filters may be classified in number of ways:
1. Analog or Digital filters: Analog filters are designed to process analog signals, while digital filters process analog signals using digital techniques.
2. Passive or active filters: Filters constructed with passive components (resistors, capac- itors, and inductors) are called passive filters. Filters constructed with active components (transistors or op-amps in addition to resistors and capacitors) are called active filters.
3. Audio frequency (AF) or radio frequency (RF) filters: RC filters are used for audio or low frequency operation, whereas LC or crystal filters are employed at RF or high frequencies.
Active filters have some advantages over passive filters.
1. Gain and frequency adjustment flexibility.
2. No loading problem.
3. Economical
The most commonly used filters are low-pass filter, high-pass filter, band-pass filter, band-reject filter and All-pass filter. Each of these filters uses an op-amp as the active element, resistors and capacitors as the passive elements.
5.3 Butterworth filters
Consider a low pass active filter. The gain of the filter can be expressed as
1 Av = (5.6) Pn(s)
where Pn(s) isDr. a polynomial in M the variable Ramegowdas . A common approximation for the equation 5.6 uses the Butterworth polynomial Bn(s) as
Avo Av = (5.7) Bn(s) and with s = jω ,
2 2 | Avo | | Av | = 2n (5.8) 1 + (ω/ωo)
where | Avo | is the gain at the cut off frequency ωo . By using equations 5.7 and 5.8, we can write the magnitude of Bn(ω) as 50 CHAPTER 5. APPLICATIONS OF OP-AMP 1
A v Avo
0.1
n = 1 n = 3 n = 2 0.01 0.1 1 10 100 ω ωo
Figure 5.12: Frequency response of Butterworth low pass filter
s ω 2n Bn(ω) = 1 + (5.9) ωo
The butterworth response for various values of n is plotted in the figure 5.12. The curve approximates the ideal characteristics for higher value of n . Where n is called order of the filter. From the figure 5.12 it can be seen that, in the first-order low-pass filter the gain rolls off at the rate of 20 dB/decade and in the second-order low-pass filter the gain roll-off at the rate of 40 dB/decade and so on. By contrast, for the first-order high pass filter the gain increases at the rate of 20 dB/decade and so on.
5.4 First order low-pass Butterworth filter The circuit diagramDr. of first order M low-pass Ramegowda Butterworth filter shown in the figure 5.13. It uses a non-inverting op-amp and a RC network. The high cutoff frequency is determined by RC network. Applying voltage divider rule at the input terminal in the figure 5.13
(1/jωC)v v = i 1 R + (1/jωC) v = i (5.10) 1 + j2πfCR
The output voltage of the amplifier is
vo = AF v1 5.4. FIRST ORDER LOW-PASS BUTTERWORTH FILTER 51
R1 RF ÿ
ý
ó +VCC
v2 v ÿ o A ÿ ò
ÿ ÿ v1 R ñ −VEE Vi ∼
© C
ý ý
Figure 5.13: First order low pass butterworth filter
On substituting for v1 from equation 5.10, we get v v = A i o F 1 + j2πfCR v A o = F (5.11) vi 1 + j(f/fH ) where vo/vi is gain of the filter, and
RF AF = 1 + R1 is gain of the non-inverting amplifier (passband gain of the filter) and 1 f = H 2πRC is high cutoff frequency of the filter. The cutoff frequency is also called -3dB frequency, break frequency, or corner frequency. From the equation 5.11, we can write
v A o = F (5.12) p 2 vi 1 + j(f/fH ) and the phase angle f φ = − arctan (5.13) Dr.f M Ramegowda H From the equation 5.12, operation of the filter can be verified.
vo At f < fH , = AF vi
vo AF At f = fH , = √ = .707AF vi 2
vo At f > fH , < AF vi
The frequency response curve of the filter is shown in the figure 5.14. After fH the gains rolls off at the rate of −20 dB/decade . 52 CHAPTER 5. APPLICATIONS OF OP-AMP
v o vi
AF (AF − 3)dB −20 dB/decade
P assband Stopband f fH Figure 5.14: Frequency response of first order low pass butterworth filter
5.5 First order high-pass Butterworth filter
High-pass filters are formed simply by interchanging frequency determining resistors and ca- pacitors in low-pass filters. The circuit diagram of first order high-pass Butterworth filter is shown in the figure 5.15. It uses the non-inverting op-amp with a RC network. The low cutoff frequency is determined by RC network. Applying voltage divider rule at non-inverting input terminal in the figure 5.15 Rv v v = i = i 1 R + (1/jωC) 1 − (j/2πfCR)
R1 RF ÿ
ý
ó +VCC
v2 vo ÿÿ ò A C
ÿ v1 ñ −VEE ∼ vi R © ¡ Dr. M Ramegowda ý ý
Figure 5.15: First order high-pass butterworth filter
The output voltage of the amplifier is vo = AF v1 On substituting for v1 from equation 5.14, we get v v = A i o F 1 − (j/2πfCR) v A o = F (5.14) vi 1 − j(fL/f) 5.5. FIRST ORDER HIGH-PASS BUTTERWORTH FILTER 53
where vo/vi is gain of the filter, and
RF AF = 1 + R1
is gain of the non-inverting amplifier pass band gain of the filter and
1 f = L 2πRC is low cutoff frequency of the filter. From the equation 5.14, we can write
v A f o = F and φ = arctan L (5.15) p 2 vi 1 + j(fL/f) f
where φ is the phase angle at frequency f. From the equation 5.15, operation of the filter can be verified.
vo f < fL = < AF vi
vo AF f = fL = = √ = .707AF vi 2
vo f > fL = = AF vi
The frequency response curve of the filter is shown in the figure 5.14. Up to fL the gain increases at the rate of −20 dB/decade .
v o vi
−20 dB/decade
AF (AF − 3)Dr.dB M Ramegowda
Stopband P assband f fL
Figure 5.16: Frequency response of first order high-pass butterworth filter 54 CHAPTER 5. APPLICATIONS OF OP-AMP 5.6 THE 555 TIMER
One of the most versatile linear integrated circuits is the 555 timer. Signetics Corporation first introduced this device as SE/NE 555 in early 1970. The device has been used in a number of useful applications such as monostable and astable multivibrators, ac/dc converters, digital logic probes, waveform generators, analog frequency meters, temperature measurement and control devices, infrared transmitters, burglar and toxic gas alarms, voltage regulators, electric eyes, and many others. The IC 555 is a monolithic timing circuit that can produce accurate and highly stable time delays or oscillation. The timer basically operates in one of two modes: either as a monostable (one-shot) multivibrator or as an astable (free-running) multivibrator. The device is available as an 8-pin metal can, an 8-pin mini DIP, or a l4-pin DIP. The SE 555 is designed for the operating temperature range from - 55 to + 125C, while the NE 555 operates over a temperature range of 0 to + 70C. Figure 5.17 shows the pin configuration of 8-pin DIP IC NE/SE 555 timer and figure 5.18 shows the block diagram of SE/NE 555 timer. It consists of two comparators, a flip-flop, an inverter, a transistor and resistors. The flip-flop can work as, when S = 0,R = 1, then Q = 0 called set condition and when S = 1,R = 0, then Q = 1 called reset condition. The inverter at the output work as a buffer.
8 7 6 5
+VCC Discharge Threshold Control
555NE
Ground Trigger Output Reset 1 2 3 4 Figure 5.17: Pin configuration of IC 555NE
1. Pin 1: Ground. All voltages are measured with respect to this terminal.
2. Pin 2: Trigger. This is the inverting input terminal of the comparator 2. When the voltageDr. slightly less than M (1/3)VCC is Ramegowda applied to this pin, the comparator 2 output goes high, which reset the flip-flop (Q = 0), in turn output of the timer becomes high.
3. Pin 3: Output. This is the output terminal of the inverter, in which output voltage is measured at this pin with respect to ground.
4. Pin 4: Reset. This is the reset pin of the flip-flop in which the 555 timer can be reset (disabled) by applying a negative pulse to this pin. When the reset function is not in use, the reset terminal should be connected to +VCC to avoid any possibility of false triggering.
5. Pin 5: Control voltage. This is the inverting terminal of the comparator 1 in which an external voltage applied to this terminal changes the threshold as well as the trigger voltage. By applying a voltage on this pin or by connecting a pot between this pin and 5.7. THE 555 TIMER AS A MONOSTABLE MULTIVIBRATOR 55
VCC Reset 8 ó 4 ó
Comparator1 6 ð Threshold ñ R þò S C1 ¡ 5 ð ÿ Control 2 V 3 CC 3 Q ÿ ò R Output Flip-flop ¡ 1 V 3 CC ÿ Inverting Buffer þò R C2 R 2 ¡ ð Trigger
Comparator2 ÿ Q 1
1 7 ñ ñ Ground Discharge Figure 5.18: Block diagram of timer IC
ground, the pulse width of the output waveform can be varied. When not used, the control pin should be bypassed to ground with a 0.01µf capacitor to prevent any noise problems.
6. Pin 6: Threshold. This is the non-inverting input terminal of comparator 1. When the voltage at this pin is ≥ 2/3 VCC , the output of comparator 1 goes high, which set the flip-flop (Q = 1), in turn output of the timer becomes low.
7. Pin 7: Discharge. This pin is connected internally to the collector of transistor Q1. When Q = 0, transistor Q1 is off and acts as an open circuit to any external capacitor connected to it with respect to ground. When Q = 1, transistor Q1 is saturated and acts as a short circuit to the external capacitor connected to it with respect to ground.
8. Pin 8: +VCC . The supply voltage of +5V to +18V is applied to this pin with respect to ground.
The 555 timer has an adjustable duty cycle, its timing is from microseconds through hours. It has a high currentDr. output (200 M mA) and can Ramegowda drive TTL gates. It has a temperature stability of 50 parts per million (ppm) per degree celsius change in temperature. Like general-purpose op-amps, the 555 timer is reliable, easy to use, and low cost.
5.7 The 555 timer as a monostable multivibrator
A monostable multivibrator is also called a one-shot multivibrator. Figure 5.19 shows the timer IC configured for monostable operation.
1. When the output is low, the circuit is in a stable state, transistor Q1 is on and capacitor C is shorted out to ground. 56 CHAPTER 5. APPLICATIONS OF OP-AMP
2. When a triggering pulse of amplitude slightly less than 1/3 VCC is applied to the pin 2, the comparator 2 output goes high, which reset the flip-flop (Q = 0), in turn the output becomes high. At the same time the transistor Q1 get turned off and pin 7 is open for the capacitor C.
3. The capacitor C now starts charging through RA and the output remains in the high state till voltage across the capacitor increases to (2/3)VCC . When voltage across the capacitor is more than (2/3)VCC , comparator l output switches to high, which sets the flip-flop (Q = 1), in turn the transistor Q1 get turned on and the output becomes low.
4. When transistor Q1 is on, the capacitor C rapidly discharges through the transistor.
+VCC ò
ÿ ÿ
48 RA ¡
Trigger ÿ 7 2 ÿ ò
555NE
Output ÿ 6 3 ÿ ò
C 1 5 ÿÿ
0.01µf ÿý
Figure 5.19: Monostable multivibrator Dr. M Ramegowda 5.7. THE 555 TIMER AS A MONOSTABLE MULTIVIBRATOR 57 V2
VCC
0 V t
Vo ∼ tp = VCC
0 V t
VC 2 3 VCC
1 3 VCC t
Figure 5.20: Output signal of monostable multivibrator
The output remains low until a trigger pulse is again applied. Then the cycle repeats. Figure 5.20 shows the trigger input and output voltage waveforms. The pulse width of the trigger input must be smaller than the expected pulse width of the output waveform. When capacitor starts charging, voltage VC across the capacitor at any instant of time t is given by
t − R C VC = VCC 1 − e A
In the monostable operation capacitor can charged up to 2VCC /3. That is, when t = tp, the time during which the output is in high state, VC = 2VCC /3 . Therefore,
t 2 − p V = V 1 − e RAC 3 CC CC t − p 2 e RAC Dr.= 1 − M Ramegowda 3 tp e RAC = 3 t p = 2.303 log 3 RAC tp = 1.1RAC (5.16)
When the monostable multivibrator is triggered once, output will remain in the high state until the set time tp elapses. The output will not change its state even if an input trigger is applied again during this time interval tp. The circuit can be reset during timing cycle by applying a negative pulse to the reset terminal. The output will remain in the low state until a trigger is again applied. 58 CHAPTER 5. APPLICATIONS OF OP-AMP 5.8 The 555 timer as an astable multivibrator
It is also called a free-running multivibrator. Unlike the monostable multivibrator, this circuit does not require any external trigger to change the state of the output, hence the name free- running. The time during which the output is either high or low is determined by two resistors and a capacitor, which are externally connected to the 555 timer. Figure 5.21 shows the 555 timer connected as an astable multivibrator.
1. Let us consider transistor Q1 is off, capacitor C starts charging toward VCC through RA and RB. (Refer figure 5.18)
2. As soon as the voltage across the capacitor greater than 2VCC /3 comparator 1 output switches to high, which resets the flip-flop (Q = 1), in turn the transistor Q1 get turned on and at the same time output goes low.
3. When transistor Q1 is on, the capacitor C rapidly discharges through Q1 and RB.
4. When the voltage across C is less than VCC /3 comparator 2 output goes high, which sets the flip-flop (Q = 0), in turn the transistor Q1 get turned off and at the same time output goes high.
5. When transistor Q1 is off, again capacitor C starts charging towards +VCC through RA and RB. Then the cycle repeats.
The output voltage and capacitor voltage waveforms are shown in figure 5.21. The capacitor is periodically charged and discharged between VCC /3 and 2VCC /3.
+VCC ò
ÿ ÿ
48 RA
¡ ÿ 7
RB
Output ¡ ÿ ò
ÿ 3 6 555NE
ÿ 2 Dr. M Ramegowda 1 5 ÿ ÿ
C
0.01µf ÿý
Figure 5.21: Astable multivibrator 5.8. THE 555 TIMER AS AN ASTABLE MULTIVIBRATOR 59
Vo ∼ = VCC
0 V T t
VC td tc 2 3 VCC
1 3 VCC t Figure 5.22: Out put wave of Astable multivibrator
When the capacitor charges from 0V to VCC /3 in the time interval t1, then
1 − t1 V = V 1 − e (RA+RB )C 3 CC CC t1 3 e (RA+RB )C = 2 3 t = (R + R )C ln 1 A B 2
Similarly, when the capacitor charges from 0V to 2VCC /3 in the time interval t2, we can get
t2 = (RA + RB)C ln 3
The time tc that the capacitor charged from VCC /3 to 2VCC /3 is, 3 t = t − t = (R + R )C (ln 3 − ln ) c 2 1 A B 2 =Dr. (RA + RB)C ln 2 M Ramegowda = 0.69(RA + RB)C (5.17)
When the capacitor discharges from 2VCC /3 to 1VCC /3 through RB in the time interval td, we can write
t 1 2 − d V = V e RB C 3 CC 3 CC td = RBC ln 2 = 0.69RBC (5.18)
Then the time period T of oscillation is
T = tc + td = 0.69(RA + 2RB)C (5.19) 60 CHAPTER 5. APPLICATIONS OF OP-AMP and the frequency of oscillation is 1 1.45 f = = C (5.20) T (RA + 2RB)
Equation 5.20 indicates that the frequency f is independent of the supply voltage VCC . Often the term duty cycle is used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed as a percentage. That is t R + R % dutycycle, D = c × 100 = A B × 100 (5.21) T RA + 2RB
Dr. M Ramegowda Chapter 6
Digital Electronics
6.1 Boolean Algebra
The algebra used in the design and maintenance of logical circuits is called Boolean algebra. It was originated by George Boole (1815 - 1864) and adapted in the 1930’s for use in digital logic circuit
6.1.1 Basic laws 1.0+ A = A 2.1+ A = 1 3. A + A = A 4. A + A = 1 5.0 .A = 0 6.1 .A = A 7. A.A = A 8. A.A¯ = 0 9. A + B = B + A 10. A.B = B.A 11. A + (BDr.+ C) = (A + B) + MC Ramegowda 12. A.(B.C) = (A.B).C 13. A(B + C) = AB + AC 14. A + AC = A 15. A(A + B) = A 16.( A + B).(A + C) = A + BC 17. A + AB¯ = A + B 18. AB + BC + BC¯ = AB + C
61 62 CHAPTER 6. DIGITAL ELECTRONICS
6.1.2 Proof of Boolean laws using perfect induction 1. A + AC = A
A C AC A + AC 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 1
2. AB + BC + BC¯ = AB + C
A B C B AB BC BC AB+BC+BC AB + C 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 1
Similarly, using perfect induction all basic laws can be proved.
6.1.3 Types of Boolean expression Boolean expressions are of two types
1. Sum-of-products: It is the sum of all product terms.
• e.g. Y = AB + BC + BC • This form of expression is also called minterm form • AB, BC and BC are called minterms
2. Product-of-Sums: It is the product of all sum terms. • e.g.Dr.Y = (A + B).(B M+ C).(C + RamegowdaA). • This form of expression is also called maxterm form. • (A + B), (B + C), (C +A) are called maxterms.
6.1.4 DEMORGAN’S THEOREM 1. The compliment of a logical sum equals the logical product of compliments. i.e. A + B = A.B
2. The compliment of logical product equals the logical sum of compliments. i.e. A.B = A + B 6.1. BOOLEAN ALGEBRA 63
6.1.5 Proof of Demorgan’s theorem using perfect induction 1. A.B = A + B
A B A B A.B A.B A + B 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0
2. A + B = A.B
A B A B A.B A + B A.B 0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0
6.1.6 Dual nature of Boolean laws • DeMorgan’s theorem shows the basic duality of Boolean algebra.
• The postulates and theorems of Boolean algebra can be divided into two pairs.
• A + (B + C) = (A + B) + C is the dual nature of A.(B.C) = (A.B).C and 0 + A = A is the dual nature of 1.A = A
• Thus in any expression by changing logic 0 to logic 1 and by changing (+) sign to (.) sign dual nature of Boolean expression can be realised.
• In proving basic laws, it is necessary to prove only one law, the dual of that law follows necessarily.
• If X + XY = X is proved, then we can directly write X(X + Y ) = X
6.1.7 Constructing circuits from boolean expression Example 1.Dr.Consider the minterm M Boolean Ramegowda expression Y = A.B + A.B Step1. In the above expression, it is clear that it requires two input OR gate with inputs A.B and A.B to get output Y.
Step2. In the input side there are two minterms with one inverted variables, so it requires two AND gates with one inverter.
Consider the Boolean equation Y = A.B + A.B
A.B ≥1 step1 Y = A.B + A.B A.B 64 CHAPTER 6. DIGITAL ELECTRONICS
A step2 ô & A.B ô ÿ ≥1 B Y = A.B + A.B
& 1 A.B B
By using old gates diagram
A.B step1 Y = A.B + A.B A.B
A step2 ô A.B ô ÿ B Y = A.B + A.B
1 A.B B
6.1.8 Boolean expression from truth table Boolean expressions are a convenient method of describing how a logic circuit operates.
The truth table is another precise method of describing how a logic circuit works.
Consider the following truth table which generates logical 1 output only for two of the eight possible combinations of inputs A, B, and C
Inputs Output Boo.Expn A B C Y 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 Dr.1 M0 1 Ramegowda1 Y = A.B.C 1 1 0 1 Y = A.BC 1 1 1 0
The two combinations that generates output are to be read as A and not B and C and A and B and not C. Thus output Y = A.B.C + A.BC .
6.1.9 Simplifying boolean expressions Consider the Boolean expression Y = A.B + A.B + A.B. To construct logic circuit it requires one three input OR gate and three two input AND gates with two inverters 6.2. THE BINARY SYSTEM 65
A ÿô
A.B ô ÿ B
1 A.B Y = A.B + A.B + A.B B
1 A A.B
Step 2. Now get the output by using the truth table
A B A B AB AB AB Y = AB + AB + AB 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 1
Clearly we can see that the output Y is the output of OR gate. Thus we can write Y = A + B. Therefore AB + AB + AB = A + B
6.2 The Binary System
As we know, the decimal system uses the digits 0-9 to represent numbers. It uses ten digits, so its base is taken as 10. Any larger number can be generated by using the digits 0-9. e.g., 387 = 3 × 102 + 8 × 101 + 7 × 100. The binary system works under the same principles as the decimal system, only it operates in base 2 rather than base 10. Instead of using the digits 0-9 in decimal system, we only use 0-1 in binary system. Any larger number can be generated by using the digits 0-1. e.g., 101 = 1 × 22 + 0 × 21 + 1 × 20.
24 23 22 21 20 1 0 1 1 0 Dr.0 1 1 M Ramegowda 6.2.1 Conversion of binary to decimal and decimal to binary
Consider a binary number (1101)2. It can be expressed as
3 2 1 0 (1101)2 = 1 × 2 + 1 × 2 + 0 × 2 + 1 × 2 = 8 + 4 + 0 + 1 = (13)10
i.e., the binary number (1101)2 is equal to decimal number (13)10. Consider a decimal number (13)10. Divide this number by base of the binary, 2 and tabulate the remainder. Again divide the quotient by 2 and tabulate the remainder. Continue the process until remainder becomes 0 or 1. The last remainder becomes most significant number in the binary and first remainder becomes least significant number in the binary. 66 CHAPTER 6. DIGITAL ELECTRONICS
2 13 2 6 1 - LS 2 3 0 2 1 1 2 0 1 - MS
6.2.2 Binary arithmetic Binary arithmetic works the same way as in the decimal system. Decimal Binary Carry 00110 1. Binary addition 27 11011 19 10011 46 101110
Decimal Binary 28 11101 2. Binary subtraction 11 01011 17 10010
Decimal Binary 14 × 5 1 1 1 0 1 ×101 70 1 1 1 0 1 3. Binary multiplication 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1
Decimal Binary 9 1001 27/3 11) 11011 4. Binary division 11 00011 11 00
6.2.3 Negation in the Binary System The computerDr. uses a fixed number M of bits Ramegowdaor binary digits. An 8 − bit number is 8 digits long. For this section, we will work with 8 − bits. The simplest way to indicate negation is signed magnitude. In signed magnitude, the left-most bit is not actually part of the number, but is just the equivalent of a +/− sign. 0 indicates that the number is positive, 1 indicates negative. In 8 − bits, 00001100 would be 12. To indicate −12, we would simply put a 1 rather than a 0 as the MSB. Hence −12 = 10001100.
6.2.4 One’s and Two’s complement numbers In one’s complement, positive numbers are represented as usual in regular binary. However, negative numbers are represented differently. To negate a number, replace all zeros with ones, and ones with zeros - flip the bits. Thus, 12 would be 00001100, and −12 would be 11110011. 6.2. THE BINARY SYSTEM 67
As in signed magnitude, the leftmost bit indicates the sign (1 is negative, 0 is positive). To compute the value of a negative number, flip the bits and translate as before. By adding 00000001 to the one’s complement number, we get two’s compliment number. Twelve would be represented as 00001100, and −12 as 11110011+00000001 = 11110100. Hence negative numbers are represented using compliment numbers.
6.2.5 Subtraction using one’s complement number. 1. Get the 1’s compliment of subtrahend.
2. Add the complimented subtrahend to minuend.
3. If there no end over carry, re-compliment the sum to get the result and the result will be negative.
4. If there is an end over carry, add the carry to LSB to get the result and the result will be positive.
Example 1: 12 - 5 = 7
Binary of 12 00001100 Binary of 5 00000101 1’s compliment of 5 11111010
Add 1’s compliment of 5 to 12 12 00001100 - 5 11111010 100000110 Add carry to LSB 00000001 7 00000111
Example 2: 5 - 7 = -2
Binary of 5 00000101 Binary of 7 00000111 1’s compliment of 7 11111000
Add 1’s compliment of 7 to 5 5 00000101 - 7 11111000 Dr. M Ramegowda11111101 Compliment the sum -2 00000010
6.2.6 Subtraction using two’s complement number. 1. Get the 2’s compliment of subtrahend.
2. Add the complimented subtrahend to minuend.
3. If there no end over carry, re-compliment the sum to get the result and the result will be negative.
4. If there is an end over carry, leave the carry to get the result and the result will be positive. 68 CHAPTER 6. DIGITAL ELECTRONICS
Example 1: 12 - 5 = 7
Binary of 12 00001100 Binary of 5 00000101
1’s compliment of 5 11111010 Add 00000001 to get 1’s compliment 00000001 2’s compliment of 5 11111011
Add 2’s compliment of 5 to 12 12 00001100 - 5 11111011 100000111 Leave carry 7 00000111
Example 2: 5 - 7 = -2
Binary of 5 00000101 Binary of 7 00000111
1’s compliment of 7 11111000 Add 00000001 to get 2’s compliment 00000001 2’s compliment of 7 11111001
Add 2’s compliment of 7 to 5 5 00000101 - 7 11111001 11111110 1’s compliment of the sum 00000001 Add 00000001 to get 2’s compliment 00000001 -2 00000010
6.2.7 Hexadecimal number Any binary number is arranged in group of four for the application purposes. The arrange- ment of four bits from 0001 to 1111 give the sixteen numbers and the number system is called Hexadecimal number system.
Binary Hexadecimal Decimal Binary Hexadecimal Decimal Dr.0001 M1 Ramegowda1 1010 A 10 0010 2 2 1011 B 11 0011 3 3 1100 C 12 0100 4 4 1101 D 13 0101 5 5 1110 E 14 0110 6 6 1111 F 15 0111 7 7 0001 0001 10 16 1000 8 8 0001 0010 11 17 1001 9 9 0001 0011 12 18 6.3. GATES 69
The higher numbers can be represented as
Binary Hexadecimal Decimal 0010 1111 2F 47 0101 0000 50 80 0001 0011 AD 18
6.2.8 Conversion of hexadecimal to decimal and decimal to hexadec- imal
Consider a hexadecimal number (AD)H . It can be expressed as
1 0 1 0 (AD)H = A × 16 + D × 16 = 10 × 16 + 13 × 16 = 160 + 13 = (173)10
i.e., the hexadecimal number (AD)H is equal to decimal number (173)10. Consider a decimal number (3359)10. Divide this number by base(16) of the hexadecimal and tabulate the remainder. Again divide the quotient by 16 and tabulate the remainder. Continue the process until remainder becomes less than the base. The last remainder becomes most significant number in the hexadecimal and first remainder becomes least significant number in the hexadecimal.
16 3359 16 29 F - LS 16 1 D 0 1 - MS
Hence (3359)10 = (1DF )H
6.3 Gates
6.3.1 Logic families There are several different families of logic gates. Each family has its capabilities and limitations.
1. Diode Logic (DL): Diode logicDr. gates use diodes M to perform Ramegowda AND and OR logic functions. Diodes have the property of easily passing an electrical current in one direction, but not the other. Thus, diodes can act as a logical switch. Diode logic gates are very simple and inexpensive, and can be used effectively in specific situations. However, they cannot be used extensively, as they tend to degrade digital signals rapidly. In addition, they cannot perform a NOT function, so their usefulness is quite limited.
2. Resistor-Transistor Logic (RTL): Resistor-transistor logic gates use transistors to com- bine multiple input signals, which also amplify and invert the resulting combined signal. Often an additional transistor is included to re-invert the output signal. This combination provides clean output signals and either inversion or non-inversion as needed. 70 CHAPTER 6. DIGITAL ELECTRONICS
RTL gates are almost as simple as DL gates, and remain inexpensive. They also handy because both normal and inverted signals are often available. However, they do draw a significant amount of current from the power supply for each gate. Another limitation is that RTL gates cannot switch at the high speeds used by today’s computers, although they are still useful in slower applications. 3. Diode-Transistor Logic (DTL): In DTL gates, diodes perform the logical AND or OR function and then amplifying the result with a transistor. It can avoid some of the limitations of RTL gates. DTL takes diode logic gates and adds a transistor to the output, in order to provide logic inversion and to restore the signal to full logic levels. 4. Transistor-Transistor Logic (TTL): The physical construction of integrated circuits made it more effective to replace all the input diodes in a DTL gate with a transistor, built with multiple emitters. The result is transistor-transistor logic, which became the standard logic circuit in most applications. TTL integrated circuits were adapted slightly to handle a wider range of requirements, but their basic functions remained the same. These devices comprise the 7400 family of digital ICs. 5. Emitter-Coupled Logic (ECL): Also known as Current Mode Logic (CML), ECL gates are specifically designed to operate at extremely high speeds, by avoiding the ”lag” inher- ent when transistors are allowed to become saturated. Because of this, these gates uses substantial amounts of electrical current to operate correctly. 6. CMOS Logic: One factor is common to all of the logic families listed above is the use of significant amounts of electrical power. Many applications, especially portable, battery- powered ones, require that the use of power be absolutely minimized. To accomplish this, the CMOS (Complementary Metal-Oxide-Semiconductor) logic family was developed. This family uses enhancement-mode MOSFETs as its transistors, and is so designed that it requires almost no current to operate. CMOS gates are, severely limited in their speed of operation. Nevertheless, they are highly useful and effective in a wide range of battery-powered applications.
6.3.2 Gate characteristics Most logic families share a common characteristic 1. Fan-in: The number of standard loads drawn by an input to ensure reliable operation. Most inputs have a fan-in of 1. 2. Fan-out:Dr.The number of M standard loads Ramegowda that can be driven by an output, without causing the output voltage to shift out of its legal range of values. 3. Input and output levels: Generally 0V-0.4V is represents as logic 0 state and 0.4V-5V represent as logic 1 state. 4. Propagation delay: When input is changed, the time require to change the output from 1 state to 0 state and viceversa is called propagation delay. For TTL gates t(pLH) = 22ns and t(pHL) = 15ns. 5. Noice immunity: The ability of a gate to withstant input noice. 6. Power dissipation: The dissipation of the power per gate when output changes by high state to low state and viceversa. 6.3. GATES 71
6.3.3 DTL Gates 1. DTL NAND Gate: Figure 6.2 shows an 3-input DTL NAND gate. It consists of a single transistor Q configured as an inverter, which is driven by a current that depends on the inputs to the three input diodes D1 − D3.
When all the input are high, diodes D1 − D3 are not conducting, all the current from Vcc through R will go through DA and DB and into the base of the transistor. Then the transistor is turn on and Vo = 0V .
Figure 6.1: DTL NAND gate
If any of the diodes D1 − D3 gets an input voltage of logic 0, it gets forward-biased and starts conducting. This conducting diode shunts almost all the current from R, limiting the transistor base current. This forces the transistor to turn off, bringing up the output voltage Vo = Vcc (logic 1). 2. DTL NOR Gate: Figure ?? shows an 3-input DTL NAND gate. It consists of a single transistor Q configured as an inverter, which is driven by a current that depends on the inputs to the three input diodes D1 − D3.
When all the input are low, diodes D1 − D3 are not conducting. Then the transistor is turn off and output is high.
If any of the diodes D1 − D3 gets an input voltage of logic 1, it gets forward-biased and starts conducting.Dr. The transistor M turns Ramegowda on, and output voltage Vo = 0V (logic 0). Advantages of DTL gates
1. These are having better noise margin than RTL gates.
2. High fan out.
3. More economical.
Disadvantages of DTL gates
1. Switching speed is low.
2. Noice margin is poor. 72 CHAPTER 6. DIGITAL ELECTRONICS
Figure 6.2: DTL NOR gate
6.3.4 TTL gates 1. TTL NAND Gate: Figure 6.3 shows a basic 2-input TTL NAND gate with a totem-pole output. When both inputs are high, base-emitter junctions of Q1 and Q2 becomes reverse-
ó VCC
ÿ
R6
ÿ¡ R1 R2 R3
¡ ¡ ¡ ÿ Q6 Q5
A ð ÿ R Q3 5 Y Q ÿ ò 1 ¡ B ð ÿ Q Q4 2
R4
¡ ÿý
Figure 6.3: TTL NAND gate with totem-pole output
biased,Dr. causing current to M flow through RamegowdaR1 and R2 to the base of Q3, which is driven into saturation. When Q3 starts conducting, the Q4 also driving into saturation. The output voltage Vo = 0V (logic 0). Since Q3 starts conducting, the base of Q6 becomes grounded, then Q6 is cut-off. When Q6 is cut-off, Q5 will also in cut-off. No current will flow from Vcc to the output, keeping it at logic 0.
When one of the input is low, base-emitter junction of Q1 (or Q2) becomes forward-biased, causing current through R1 (or R2) flow into the base-emitter junction of Q1 (or Q2) to ground. Due to this Q3 becomes cut off and the base of Q6 appears with VCC , which driving Q6 into saturation. When Q6 conducts, the base of Q5 appears with positive potential, which drives Q5 to conduct. When Q3 is cut-off, Q4 becomes cut-off and output voltage Vo = VCC (logic 1). Also, since Q4 is in cut-off, current will flow from VCC to the output through Q5, keeping it at logic 1. 6.3. GATES 73
Thus the transistor Q3 always provides complementary inputs to the bases of Q4 and Q5, such that Q4 and Q5 always operate in opposite regions. Then the output is called totem pole output. By using one inverter at the output terminal of the NAND gate, AND gate can be obtained and is shown in the figure 6.4.
ó VCC
ÿ
R6
ÿ¡ R1 R2 R3 R7
¡ ÿ ¡ ¡ ¡ Q6 Q5 Y ÿ ò A ð ÿ R Q3 5 Q1 ÿ Q7 ¡
B ð ÿ Q Q4 2
R4 ¡
ÿý
Figure 6.4: TTL AND gate with totem-pole output
2. TTL NOR Gate: Figure 6.5 shows the two input TTL NOR gate. When both inputs are low, base-emitter junction of Q1 and Q2 becomes forward-biased, causing current through R1 and R2 flow into the base-emitter junctions of Q1 and Q2 to ground. Due to this Q3 and Q4 becomes cut off and the base of Q5 appears with ground potential, which driving Q5 to cut-off. The current will flow from VCC to the output through R5 and out put becomes logic 1.
ó VCC
ÿ
R1 R2 R3 ¡ R5 ¡ ¡ ¡
ÿ
A ð Q Q3 Q4 1 ÿ Dr. M Ramegowda B Y ð ÿ ò Q 2 ÿ Q5
R4
¡ ÿý
Figure 6.5: TTL NOR gate with totem-pole output
When one of the input is high, base-emitter junction of Q1 (or Q2) becomes reverse-biased, causing current through R1 (or R2) flow into the bases of Q3 (or Q4), which drives Q3 74 CHAPTER 6. DIGITAL ELECTRONICS
(or Q4) to saturate. Then base of Q5 appears with VCC , which driving Q5 to saturate. The current will flow from VCC to ground through R5 and out put appears with grounded potential (logic 0). By using one inverter at the output terminal of the NOR gate, OR gate can be obtained and is shown in the figure 6.6.
ó VCC
ÿ
R1 R2 R3 R5 R6
¡ ¡ ¡ ¡ ¡
ÿ
A ð Q Q3 Q4 1 Y ÿ ÿ ò
B ð Q Q6 2 ÿ Q5
R4 ¡
ÿý
Figure 6.6: TTL OR gate
6.4 Flip-flops
The basic circuit for storing information in a digital machine is called a flip-flop. There are two characteristics for a flip-flops.
1. The flip-flop is a bistable device, that is, a circuit with only two stable states, which we designate the0 state and the1 state.
2. It has two output signals, one of which is the complement of the other.
The flip-flop circuit can remember, or store, a binary bit of information because of its bistable characteristic.Dr. The flip-flop responds M to inputs. Ramegowda If an input causes it to go to its other state, it will remain in the previous state, until some signal causes it to go to the other state. The ability of the flip-flop to retain its state is the basis for information storage and calculating sections of a digital computer.
6.5 S R flip-flop
The logic circuit and logic symbol for the R-S flip-flop is drawn in figure 6.7. Notice that the R-S flip-flop has two inputs, labelled S and R. The two outputs are labelled Q and Q. The letters S and R at the inputs of the R-S flip-flop are often referred to as the set and reset inputs. The truth table in Table 6.1 gives the operation of the R-S flip-flop. When both S and R inputs are 0, both outputs go to a logic 1. This is called a prohibited state for the flip-flop and is not 6.5. S R FLIP-FLOP 75
Figure 6.7: Logic circuit and Logic symbol of S R Flip-flop used. The second line of the truth table shows that when input S is 0 and R is 1, the Q output is set to logic 1. This is called the set condition. The third line shows that when input R is 0 and S is 1, output Q is reset (cleared) to 0. This is called the reset condition. The Line 4 in the truth table shows both inputs (R and S) at 1. This is the idle or at rest condition and leaves Q and Q in their previous complementary states. This is called the hold condition. From Table 1, it may be observed that it takes a logical 0 to activate the set (set Q to 1). It also takes a logical 0 to activate the reset, or clear (clear Q to 0). Because it takes a logical 0 to activate, it is called the low active device. It is indicated with the bubbles at the inputs.
Mode of operation Inputs Outputs Effect on output Q S R Q Q Prohibited 0 0 1 1 Prohibited - Do not use Set 0 1 1 0 For setting Q to 1 Reset 1 0 0 1 For setting Q to 0 Hold 1 1 Q Q Depends on previous State
Table 6.1: Truth table of S R Flip-flop
The R-S flip-flop is most commonly known as a latch and is listed under this heading in IC catalogs.
6.5.1 Clocked S R flip-flop The logic circuitDr. and logic symbol M for a clocked Ramegowda R -S flip-flop is shown in figure 6.8. It has one extra input labelled as CLK (for clock). The operation of the clocked R-S flip-flop is shown in the figure 6.9. The flip-flop is in the hold condition during clock pulse 1. When S (set) input is moved to 1, the output Q is not yet set to 1 until the clock pulse 2 rises from 0 to 1. Pulses 3 and 4 have no effect on output Q. During pulse 3 the flip-flop is in its set mode, while during pulse 4 it is in its hold mode. When the input R is preset to 1, the output still remains in its hold mode. The rising edge of clock pulse 5, the output Q is reset (or cleared) to 0. The flip-flop is in the reset mode during both clock pulses 5 and 6. The flip-flop is in its hold mode during clock pulse 7; therefore, the normal output Q remains at 0. Notice that the outputs of the clocked R-S flip-flop change only on a clock pulse. The clocked R-S flip-flop operates synchronously with the clock. 76 CHAPTER 6. DIGITAL ELECTRONICS
Figure 6.8: Logic circuit and Logic symbol of clocked S R Flip-flop
Figure 6.9: Wave diagram for an S R Flip-flop
Synchronous operation is very important in most digital circuits, where each step must happen in an exact order. Another characteristic of the clocked R-S flip-flop is that once it is set or reset it stays that way even the inputs are changed. This is a memory characteristic, which is extremely valuable in many digital circuits.
6.6 TheDr. D Flip-flop M Ramegowda
The logic symbol for the D flip-flop is shown in figure 6.10. It has only one data input (D) and a clock input (CLK). The outputs are labelled as Q and Q. The D flip-flop is often called a delay flip-flop, because the data at input D is delayed one clock pulse from getting to output Q (see Qn+1 column). A simplified truth table for the D flip-flop is shown in Table 6.2. A D flip-flop may be formed from a clocked R-S flip-flop by adding an inverter, as shown in Fig. 6.10. The D flip-flop is often called a delay flip-flop, because the data at input D is delayed one clock pulse from getting to output Q (see Qn+1 column) as shown in the truth table. A D flip-flop may be formed from a clocked R-S flip-flop by adding an inverter, as shown in figure 6.10. 6.7. J K FLIP-FLOP 77
Figure 6.10: Logic symbol of D Flip-flop
Input Outputs D Qn+1 0 0 1 1
Table 6.2: Truth table of D Flip-flop
6.7 J K Flip-flop
The logic circuit and symbol for the J-K flip-flop is illustrated in figure 6.11. The inputs labeled as J and K are the data inputs. The input labeled as CLK is the clock input. Outputs Q and Q are the usual normal and complementary outputs on a flip-flop.
FigureDr. 6.11: Logic circuitM and Logic Ramegowda symbol of commercial J K Flip-flop
A truth table for the J-K flip-flop is shown in table 6.3. When both J and K inputs are 0, the flip-flop is in the hold mode and the data inputs have no effect on the outputs. The outputs hold the last data present. Lines 2 and 3 of the truth table show the reset and set conditions for the output Q. Line 4 illustrates the useful toggle position of the J-K flip-flop. When both data inputs J and K are at 1, repeated clock pulses cause the output to turn off-on-off-on-off-on, and so on. This off-on action is like a toggle switch and is called toggling. The J-K flip-flop is considered to be universal flip-flop. Its unique feature is the toggle mode of operation, which is useful in designing counters. When the J-K flip-flop is wired for use only in the toggle mode, it is commonly called a T flip-flop. 78 CHAPTER 6. DIGITAL ELECTRONICS
Mode of operation Inputs Outputs CLK J K Q Q Effect on Q Hold 1 0 0 No change Disable Reset 1 0 1 0 1 Reset to 0 Set 1 1 0 1 0 Set to 1 Toggle 1 1 1 Toggle Change to opposite state
Table 6.3: Truth table of J K Flip-flop
J-K flip-flops are available in both TTL and CMOS IC form. Typical CMOS J-K flip-flops are the 74HC76, 74AC109, and 4027 ICs.
6.8 Shift Registers
Register is a group of memory cells. The register can be used to simply store information for later use. A shift register is the one which modifies the contents by shifting data to right or left. The term latch may be used to describe the register used to store data. There are two important characteristics of a shift register: 1. It is a temporary memory and thus holds the numbers on the display (even if the keyboard number is released)
2. It shifts the numbers to the left on the display each time when a new digit on the keyboard is pressed. These memory and shifting characteristics make the shift register extremely valuable in most digital electronic systems.
6.8.1 Classification of Shift Registers Shift registers are classified into four groups. 1. Serial in - serial out shift register.
2. Serial in - parallel out shift register. 3. ParallelDr. in - serial out shift M register. Ramegowda 4. Parallel in - parallel out shift register.
Figure 6.12: Serial in - serial out shift register 6.9. SERIAL IN - SERIAL OUT SHIFT REGISTER 79
Figure 6.13: Serial in - parallel out shift register
Figure 6.14: Parallel in - serial out shift register
6.9 Serial in - serial out shift register
The wiring diagram of four bits serial in - serial out shift register using D flip-flops is shown in the figure 6.16. Let 0 is put onto the data input line, making D = 0 for FFA. When the first clock pulse is applied, FFA is RESET and output of FFA becomes 0. When the 1 is applied to the data input, making D = 1 for FFA and D = 0 for FFB. When the second clock pulse occurs, the 1 on the data input is shifted into FFA and the 0 that was in FFA is shifted into FFB. The next 0 in the binary number is now put onto the data-input line, and a clock pulse is applied. The 0 is entered into FFA, the 1 stored in FFA is shifted into FFB, and the 0 stored in FFB is shifted into FFC. TheDr. last bit in the binary M number, Ramegowda 1, is now applied to the data input, and a clock pulse is applied. This time the 1 is entered into FFA, the 0 stored in FFA is shifted into FFB, the 1 stored in FFB is shifted into FFC, and the 0 stored in FFC is shifted into FFD. This completes the serial entry of the four-bit number into the shift register, where it can be stored for any length of time. If we want to get the data out of the register, they must be shifted out serially and taken off the QD output. After CLK4 in the data entry operation described above, the right-most 0 in the number appears on the QD output. When clock pulse CLK5 is applied, the second bit appears on the QD output. CLK6 shifts the third bit to the output, and CLK7 shifts the fourth bit to the output. The operation can also be realized using the truth table 6.4. 80 CHAPTER 6. DIGITAL ELECTRONICS
Figure 6.15: Parallel in - parallel out shift register
Figure 6.16: Serial in - serial out shift register
6.10 Serial in - parallel out shift register
The wiring diagram of four bits serial in - parallel out shift register using D flip-flops is shown in the figure 6.17. Let 0 is put onto the data input line, making D = 0 for FFA. When the first clock is applied, FFA is RESET and output of FFA becomes 0. When the 1 is applied to the data input, making D = 1 for FFA and D = 0 for FFB. When the second clock pulse occurs, the 1 on the data input is shifted intoDr. FFA and the 0 M that was in Ramegowda FFA is shifted into FFB. The next 0 in the binary number is now put onto the data-input line, and a clock pulse is applied. The 0 is entered into FFA, the 1 stored in FFA is shifted into FFB, and the 0 stored in FFB is shifted into FFC. The last bit in the binary number, 1, is now applied to the data input, and a clock pulse is applied. This time the 1 is entered into FFA, the 0 stored in FFA is shifted into FFB, the 1 stored in FFB is shifted into FFC, and the 0 stored in FFC is shifted into FFD. This completes the serial entry of the four-bit number into the shift register, where it can be stored for any length of time and can be read The operation can also be realized using the truth table 6.5 6.10. SERIAL IN - PARALLEL OUT SHIFT REGISTER 81
Inputs Clock Output Clear Data pulse 0 0 0 0 1 1 0 0 1 1 1 0 1 1 2 0 1 0 3 0 1 1 4 1 1 1 5 1 0 1 6 0 1 1 7 0 1 1 8 0 1 0 9 0 1 1 10 1 1 1 11 1
Table 6.4: Truth table of serial in - serial out shift register
Dr. M Ramegowda
Figure 6.17: Serial in - parallel out shift register 82 CHAPTER 6. DIGITAL ELECTRONICS
Inputs Clock Outputs Clear Data pulse A B C D 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 2 1 1 0 0 1 0 3 0 1 1 0 1 1 4 1 0 1 1 1 1 5 1 1 0 1 0 1 6 0 0 0 0 1 1 7 1 0 0 0 1 1 8 1 1 0 0 1 0 9 0 1 1 0 1 1 10 1 0 1 1 1 1 11 1 1 0 1
Table 6.5: Truth table of serial in - parallel out shift register Dr. M Ramegowda