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Brain-Like Computing – Technologies and Architectures Brain-like Computng – Technologies and Architctures Prof. Pinaki Mazumder University of Michigan Ann Arbor, MI 48105 Acknowledgement: National Science Foundation (CCF & ECCS) 1 EVOLUTION OF NEUROMORPHIC COMPUTING: Perceptron (’60) Gartner Hype Cycle (10 E 2 neurons) Neural Net (’90) (10 E 3 Neurons) Neuromporphic Hardware (’00) • Memristor (10 E 5 neurons) • Spintronics • MQW Devices Multi-level • Nanoscale CMOS Nanocrossbar (10 E 7 neurons) Designed by Mazumder Group 1992 Perceptron Mark 1 Hopfield Net Chip TrueNorth (IBM) ~ 1 M Neurons Mazumder Group’s Neuromorphic Research Self-Healing VLSI Design Learning based VLSI Chips (1989-1996) (2010-2016) Hopfield Neural Net as Algorithmic STDP Learning for Position Detector Hardware for Spare Allocation by STDP Learning for Virtual Bug Navigation Node Cover over Bipartite Graph STDP Learning for XOR/Edge Detection • IEEE Trans. on CAS, 1993 Q-Learning for Maze Search Algorithm on • IEEE Trans. on CAS, 1993 • IEEE Trans. on Computer, 1996 Memristor Array Reinforcement Learning/Actor-Critic NN Cellular Neural Networks for Optimal Nonlinear Control Applications (2008-2013) • Color Image Processing • Velocity Tuned Filter • Memristor/RRAM based CNN • RTD+HEMT based CNN • Proceedings of the IEEE, 2012 • IEEE Trans. on VLSI, 2009 • Nano Letters Journal, 2010 • IEEE Trans. on Nanotechnology, 2008 • IEEE Trans. on Computer, 2016 • IEEE Trans. on Neural Nets, 2014 • IEEE Nanotechnology, 2011 • IEEE Trans. on Nanotechnology, 2013 • IEEE Nanotechnology, 2014 • ACM Journal on Emerging Technologies • IEEE Cellular Neural Networks, 2012 in Computing Systems, 2013 Neuromorphic Self-Healing Memory Design using Memristor Array Product Code (SEC), Augmented PC (DEC) à Requires Muxes (~8%) Hamming Code (SEC) à Higher Overhead Projective Geometry Code (DEC/TED) à Galois Field Decoding, … BCH & Reed Solomon (DEC) à Decoding complexity is high High Density a-Si Based Nano-Crossbar 1kb crossbar array Jo et al. Nano Lett., 9, 870 (2009). From Prof. Wei Lu’s Research It is Scalable and CMOS Compatible. p-Si Group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ag 1 Fabbed by 2 3 < 50 kΩ Wei Lu’s 4 Group at 5 Univ. of 6 7 50 ~ 150 k Ω Michigan 8 9 Defects ! & More Defects!! 10 11 400 cells & 31 defects=8% 150 ~ 300 kΩ 12 13 14 15 300 k ~ 1 MΩ 16 17 18 19 20 Not Written Compaction of Faulty Array & Find Vertex Cover in Bipartite Graph R1 C1 R2 C3 Find Vertex Cover: Mazumder & Yih, IEEE Trans. on CAD, 1992 [R1, R2; C1, C3] Defective Cells are Edges in Bipartite Graph Unrestricted Vertex Cover Problem can Be solved in Polynomial Time by Bipartite Graph Matching Algorithm. However, Restricted Vertex Cover Problem is NP-complete. Neuromorphic Self-Healing for Any Type of Memory Array With BISR 100% Without BISR 20% M.D. Smith & P. Mazumder, IEEE Trans. on Computers, Vol. 45, No. 1, Jan. 1996, pp. 109-115. 10,000 trans. Fusion of Sensing & Processing Nanoscale Cellular Neural Network (CNN) by Using Quantum Tunneling Devices & Memristor Array Fig. 2 Schematic view of the pyramid-shape In Ga As quantum dot. 0.5 0.5 3-D Confined Quantum Box Array Memristor Array Metal Metal a-Si a-Si p-Si p-Si UNIVERSITY OF Low Resistance High Resistance MICHIGAN State (LRS) State (HRS) start 3D-SBEM-TIS 0.2 0.1 Save mass (e and h), band Define quantum 3 0.0 Φ alignment, doping dot structure distribution in files -0.1 100 -0.2 80 60 20 40 40 X Axis 60 20 Y Axis 80 100 Calculate 2D wave 2D wave function function in xy IEEE Trans. on Nanotech, 2008 plane 2.5 2.0 Solve 1D 1.5 Schrodinger (z) χ equation (in z 1.0 direction) To Pixel 0.5 0.0 0 1 2 3 4 5 6 z (nm) Using boundary Transmission rate condition to get 3D T(E) S-Matrix Edge Detection T = T ( N ) ⋅T ( N −1) ⋅⋅⋅T (2) ⋅T (1) Integrate T(E) over Tunneling current all possible energy Vertical Line Detection UNIVERSITY OF MICHIGANend (C) 2015 Professor Pinaki Mazumder Analog Programmable Nano-Architecture for Static and Dynamic Image Processing 10-3 10-5 10-7 -9 Input (I) Current (A) 10 10-11 0 1 2 3 Voltage (V) Center (C) Output (O) Memristor RTD IEEE Trans. On Nanotechnology, 2013 (a) (b) Qdot + Memristor Chip Analog Programmable Unconventional Computing IEEE Trans. On Nanotechnology, 2013 2 2 2 2 Qdot + Memristor Chip Edge Detection HLD & VLD Molecular Computer? Spike Timing Dependent Plasticity (STDP) Learning Networks using Memristors Biological Neuron Model Ionic Transport in Biological Neuron & its Silicon Implementation Hodgkin-Huxley Model Spike Timing Dependent Plasticity (STDP) Learning Networks Pre Post Synaptic Weight 15 Previous Approach of STDP Implementation On Crossbar with Constant Amplitude Programming pulses with different pulse widths 100 µs Conductance change after each pulse 1. Digitally Controlled 2. Constant Amplitude 3. Temporal Correlation Position Detector Application • Split up area into a 5x5 grid • Each grid has one neuron that is connected to an adjacent neuron through STDP synapse • Detect a light source at any position on the grid • No post-processing circuitry necessary • k-Winner-Take-All (k-WTA) implementation 17 STDP Neural Circuit for Position Detector Bases Memristor CMOS Design Design Synaptic area < (0.5µm x 17µm x 16µm 0.5µm) Synaptic Density Ø 4 devices/µm2 0.0037 devices/ x1000 µm2 Neuron area 20µm x 10µm 8µm x 12µm Neuron Density 0.005 devices/ 0.0104 devices/ µm2 µm2 x2 Volatility Nonvolatile Volatile Ebong, and Mazumder, Proceedings of the IEEE, Feb. 2012. STDP Circuits for XOR/Edge Detector Inhibitory =20 MΩ Excitatory = 5.6 MΩ) S Input = 011110; Output = 010010 n23 = n12 XOR n14 = 1 when n12=0 & n14=1 n23 = n12 XOR n14 = 0 when n12=1 & n14=1 Basic Neuromorphic Functions: WTA, XOR, Edge Detector Were implemented Using STDP learning scheme IEEE Nano 2011 Reinforcement Learning Networks Memristor Based Q-Learning Network CMOS Digital Actor-Critic Network Proceedings of the 14th IEEE International Conference on Nanotechnology Toronto, Canada, August 18-21, 2014 Proceedings of the 14th IEEE International Conference on Nanotechnology Toronto, Canada, IterativeAugust 18-21, 2014 Architecture for Value Iteration using Memristors IterativeIdongesit Architecture E. Ebong, Member, for Value IEEE and Iteration Pinaki Mazumder, usingFellow, Memristors IEEE Idongesit E. Ebong, Member, IEEE and Pinaki Mazumder, Fellow, IEEE Abstract— Memristors promise higher device density and de- Section IV provides simulation results and discussion, and signAbstract flexibility.— Memristors Besides promise utilizing higher memristors device for density digital and memory, de- SectionSection IV providesV concludes simulation the paper. results and discussion, and signanother flexibility. promising BesidesProceedings utilizingavenue of forthe memristors 14th adoption IEEE for is digital the advancement memory, Section V concludes the paper. anotherof neural promising network avenueInternational circuits for Conference capable adoption on Nanotechnology of is learning. the advancement Neural net- II. Q-LEARNING AND MEMRISTOR MODELING of neural network circuitsToronto, Canada, capable August of18-21, learning. 2014 Neural net- II. Q-LEARNING AND MEMRISTOR MODELING workwork implementations implementations with with memristors memristors have have been been proposed, proposed, including memristor synaptic training methodologies. This Q-learningQ-learning algorithm algorithm [8] is [8] provided is provided in (1). in Equation (1). Equation (1) (1) including memristor synaptic training methodologies. This ˜ ˜ workwork highlights highlights applications applications ofIterative a of neural a neural learning Architecture learning methodology methodology forprovides Valueprovides the Iteration the update update for using the for estimated the Memristors estimated Q-value Q-value (Q) at (Q the) at the current state (s ) and action taken at the current state (a ). inspiredinspired by by Q-learning. Q-learning. Memristors Memristors are are used used as analog as analog storage storage current statet (st) and action taken at the current statet (at). elements to store a large Q-table. The method is qualified with elements to store a large Q-table. The method is qualified with↵t is↵ ais learning a learning parameter, parameter, and r andt isr theis reward. the reward. In this In form this form a maze problem in order to show thatIdongesit the proposed E. Ebong, networkMember,of IEEE Q-learning,t and Pinaki the Mazumder, model of theFellow, environment IEEEt does not need to cana be maze used problem to learn in to order approximate to show an that optimal the proposedpath to solving network be accurate.of Q-learning, Therefore the model after learning, of the environment the exact reward does values not need to thecan maze be used problem. to learn Brief to results approximate highlighting an optimal the methodology path to solving do not affect the overall behavior of the network [9]. onthe a maze maze problem problem. and Brief discussion results on highlighting generating the random methodology keys be accurate. Therefore after learning, the exact reward values are provided. This workAbstract combines— Memristors model-free promise higherreinforcement device density and de- Section IV provides simulation results and discussion, and on a maze problemsign and flexibility. discussion Besides on utilizing generating memristors random for digital keys memory,do notSection affect V concludes the overall the paper. behavior of the network [9]. learning with neural networks. ˜ ˜ are provided. Thisanother work promising combines avenue model-free for adoption reinforcement is the advancementQ (st,at) Q (st,at) (1 ↵t(st,at)) + ↵t (st,at) rt of neural network circuits capable of learning. Neural net- II. Q-LEARNING⇥ AND− MEMRISTOR MODELING ⇥ learning with neuralI.work networks. INTRODUCTION implementations with memristors have been proposed, + ↵ (s ,a ) max Q˜ (s ,a ) Q˜ (s ,aQ-learning) tQ˜ algorithm(ts ,at ) [8](1 is provided↵ (ts+1 in,a (1).t))+1 Equation + ↵ (s (1),a ) r including memristor synaptic training methodologies.
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