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(SMC) MODULE of RC4 STREAM CIPHER ALGORITHM for Wi-Fi ENCRYPTION

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(SMC) MODULE of RC4 STREAM CIPHER ALGORITHM for Wi-Fi ENCRYPTION InternationalINTERNATIONAL Journal of Electronics and JOURNAL Communication OF Engineering ELECTRONICS & Technology (IJECET),AND ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) IJECET ISSN 0976 – 6472(Online) Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME: http://www.iaeme.com/IJECET.asp © I A E M E Journal Impact Factor (2015): 7.9817 (Calculated by GISI) www.jifactor.com VHDL MODELING OF THE SRAM MODULE AND STATE MACHINE CONTROLLER (SMC) MODULE OF RC4 STREAM CIPHER ALGORITHM FOR Wi-Fi ENCRYPTION Dr.A.M. Bhavikatti 1 Mallikarjun.Mugali 2 1,2Dept of CSE, BKIT, Bhalki, Karnataka State, India ABSTRACT In this paper, VHDL modeling of the SRAM module and State Machine Controller (SMC) module of RC4 stream cipher algorithm for Wi-Fi encryption is proposed. Various individual modules of Wi-Fi security have been designed, verified functionally using VHDL-simulator. In cryptography RC4 is the most widely used software stream cipher and is used in popular protocols such as Transport Layer Security (TLS) (to protect Internet traffic) and WEP (to secure wireless networks). While remarkable for its simplicity and speed in software, RC4 has weaknesses that argue against its use in new systems. It is especially vulnerable when the beginning of the output key stream is not discarded, or when nonrandom or related keys are used; some ways of using RC4 can lead to very insecure cryptosystems such as WEP . Many stream ciphers are based on linear feedback shift registers (LFSRs), which, while efficient in hardware, are less so in software. The design of RC4 avoids the use of LFSRs, and is ideal for software implementation, as it requires only byte manipulations. The RC4 algorithm will be implemented by FPGA using VHDL software platform. Key words: VHDL simulation, RC4 stream cipher, SRAM module, State machine diagram I. INTRODUCTION TO RC4 STREAM CIPHER Cryptographic algorithms that can provide fast implementation, small size, low complexity, and high security for resource-constrained devices such as wireless sensor devices are imperative. Conventional cryptographic algorithms are very complex and consume significant amount of energy when used by resource constrained devices for the provision of secure communication, and public key algorithms are still not feasible in sensor networks for several reasons including limited storage and excessive energy usage [1]. Therefore, security schemes should rely on a symmetric key 79 International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME cryptography especially when systems have limited hardware resources. There are a number of stream cipher algorithms presented to implement high performance software including IDEA, ORYX, LEVIATHAN, MUGI, RC4, Helix, SEAL, SOBER, and SNOW. RC4 is a proprietary stream cipher which was designed in 1987 by Ron Rivest. RC4 is widely used in security software based on stream cipher including one in the encryption of traffic to and from secure web sites such as Transport Layer Security (TLS), Secure Socket Layer (SSL), and Wired Equivalent Privacy (WEP) implementations. RC4 is fast in comparison to other algorithms and it has a simple design hardware implementation [2]. For instance, RC4 is five times faster than Data Encryption Standard (DES) and fifteen times faster than Triple-DES [3]. RC4 has been used as the data encryption algorithm for many applications and protocols. Some of the protocols and applications using RC4 include the Wi-Fi, Skype, and Bit Torrent, to name a few. Several efficient approaches to the implementation of RC4 have been proposed [4]. II. PROPOSED BLOCK DIAGRAM OF RC4 STREAM CIPHER The block diagram of the proposed architecture is shown in Figure1below. The block diagram can be divided in to 6 different sub modules as shown and these sub modules are i)The payload data processor and controller ii) SMC iii) Key set up and key stream generation block iv) K- Stream serializer v) KRAM(256× 8) vi) Multiplexer. As it is not possible to present all the simulation results in a single paper, it is divided in to three parts and first two parts are already presented in [5] and [6]. So, these modules are not discussed further in this paper. This paper deals with simulation of SRAM (256× 8) module, State Machine Controller (SMC) modules and an analysis of RC4 algorithm state machine diagram. Fig 1 Simulated module of Wi-Fi Encryption architecture III. SIMULATION OF SRAM(256× 8) MODULE The module SRAM is similar to KRAM. It is used to store the data from 0 to 255 at the address from 0 to 255 i.e. same data is assigned to the same memory location. The address is assigned by the output of Addr1.In this if MemWr is 1 and MemRd is 0, then data is written in to the RAM and if if MemWr is 0 and MemRd is 1, then data is read out one by one from the RAM. Data is 80 International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME given in parallel form and is read out in parallel form. Fig 2 shows the simulated module of SRAM and Fig 3 shows the simulated waveforms of SRAM . Fig 2 Simulated module of SRAM Fig 3 Simulated waveforms of SRAM IV ANALYSIS OF RC4 ALGORITHM STATE MACHINE DIAGRAM Different states of state machine diagram are explained briefly here. Fig 4 shows RC4 Algorithm state machine diagram. 4.1 Idle state: Data is at original state. 4.2 Initial state: In this state, first we fill the SRAM and KRAM. To fill both the RAM, the data is given directly to the KRAM for filling the data randomly as a DataBus and address is given by Addr1. The data at SRAM is filled with the help of Addr1 which gives the address and at the same 81 International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME time, same data comes from the DataMux and are loaded at the same address. Addr1 gives the location from 0 to 255(as cnt255) in both the RAM. The output of Addr1 is given to the----- Fig 4 RC4 Algorithm state machine diagram ---KRAM that gives the address for DataBus of KRAM. The input of SRAM (as Addr[7:0]) show address and Data fill linearly from DataIn as S0=0, S1=1,S2=2,-------S255=255.The initial state exists till the SRAM/KRAM fill completely( all 255 locations).After filling, initialOver=1, and state go to Addr2Cal state. 4.3 Addr2Cal state: In this state, Mux gives the KeyDataOut as MuxOut by selecting the Scl=1, and SRAM gives the data through DataOut to DataDMux and SellDataOut select this DataOut as SR1 [7:0] and load this value in S_Reg1 and all these values from A2, SR1 and MuxOut are added. 4.4 Addr2Ld state: In this state, the output of Adder 1(Adder 1Out) is loaded in to the Addr2 register. 4.5 SJ State: Loaded value at Addr2 gives j value. This j value is the address, which is selected by SelAddr(3:0) of AddrMux. The output of AddrMux gives address of SRAM. The value of that location is obtained as DataOut, selected by DatMux as SR2 [7:0] and stored at S_Reg2 as SJ. 4.6 Swap SI : In this state, the address is taken from Addr2, which is selected by AddrMux as Addr[7:0] and the data is loaded on this address of SRAM as DataIn by selecting Reg2[7:0] through DataMux. 4.7 Swap SJ: In this state, the address is taken from Addr1, which is selected by AddrMux as Addr[7:0] and the data is loaded on this address of SRAM as DataIn by selecting Reg1[7:0] through DataMux. All process like Addr2Cal, Addr2Ld, SJ, Swap SI and Swap SJ occurred 255 times. When Keysetupover=1, Flag=1, then it goes to Addr2Gen state. 4.8 Addr2Gen state: At this state, again we obtained the value of J by KeySetup phase. 4.9TCal state: When Swap SJ is complete, flag will be high and reaches the TCal state. 82 International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp. 79-85 © IAEME 4.10Kbyte state: The data was given to FIFO in the initial state is now loaded in to DataSerializer. 4.11 Encryption state: The key data byte from K_StreamSerializer and plaintext from DataSerializer comes out serially in the form of bits. IV. STATE MACHINE CONTROLLER (SMC) MODULE This is considered as the heart of the whole architecture. Fig 5 shows the State Machine Controller (SMC) module. By this, we can control all the modules .This state machine will work whenever InitialOver and KeySetUpOver are high. This means that all the modules will work step by step. First it controls Addr, SRAM and KRAM. When enable is high means that it was writing key data in it. Then it is going to the another state i.e. Adder 2Ld. In this state, adder will add the given input and it is given to the SRAM and this process run up to 256 times. In this process, swapping of key data bytes is performed. Then it goes to Adder 2Gen.In this state, it takes the data from S_Reg and gives it to the Adder i.e in Adder 2Ld.It adds the given input and then gives it to the SRAM with the help of AddrMux, which swap it and then gives it to the K_SteamSerilizer.
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