A GPS-Locked Frequency Source for LF
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Technical Feature AA GPS-LockedGPS-Locked FrequencyFrequency SourceSource forfor LFLF by Andy Talbot, G4JNT * he low-cost GPS-locked frequency up or down to maintain the long-term fre- 192 before the sequence repeats, which is source described here is designed quency. The output would then be continu- completely predictable. However, for this Tspecifically for low data-rate signal- ously hunting just above or just below the description, we will continue with a frequency ling on the LF bands. Phase noise and short- nearest 10Hz step. that is a multiple of 256Hz, so the ideal count term frequency stability preclude its general The problem with this design was when stays a constant. If the frequency departs use at HF or above; for these frequencies, the LC oscillator drifted by more than one slightly from its correct value, the residual other, more conventional, frequency stand- step, ie >10Hz; the locked frequency would count will steadily increase or decrease by ards are preferable, based around crystal then slowly move in jumps of 10Hz. There the magnitude of the frequency error and, if oscillators of inherently higher stability. were numerous improvements to the origi- not corrected, the counter will eventually For locking a frequency source to the nal design in the following years, several wrap round. 1 pulse per second (PPS) signal from a GPS adding more bits and resolution to the fre- What we now do, is to read the count receiver, a conventional synthesiser or phase- quency counter allowing a higher inherent every second, then drive a charge pump locked loop (PLL) approach is impractical. drift, but Huff and Puff gradually died out as circuit in a direction such as to correct the The only reference frequency is at 1Hz, so a frequency synthesisers took over. frequency. Software in a 16F84 PIC proces- PLL would need to have a bandwidth consid- sor, using the trigger pulse from the GPS, erably less than this, meaning that the loop CIRCUIT DESCRIPTION reads the latched counter value and calcu- would only lock up after many tens of minutes THIS DESIGN APPLIES the Huff and Puff lates an error value from the expected count or hours. Furthermore, the stability of the technique to a simple un-ovened VCXO to every second. For multiples of 256Hz, this basic oscillator element - the Voltage Con- maintain a source frequency that hunts ei- merely involves subtracting a constant, trolled Oscillator or VCO - would have to be ther side of a specified 1Hz multiple, but which can conveniently be a value of 128 - such that is did not drift by more than 1Hz uses an extended 8-bit frequency counter to half the counter length. If other frequencies during a time comparable with the loop band- avoid the possibility of the locked frequency are wanted, the ‘correct’ value will incre- width, otherwise lock could never be achieved. drifting in jumps of 1Hz. The VCXO operates ment by the frequency, modulo 256, every A high-stability VCO is needed and, for a at 4.194304MHz (222Hz), for reasons that second. The sign and magnitude of the error design operating at a few megahertz, the will be described later, but any frequency value obtained is then a measure of the required stability would be less than 1 part that is a multiple of 1Hz may be employed; phase (and hence frequency) error and is per million, (PPM). Voltage-controlled crys- it is also easier to understand the concept if used as follows : tal oscillators (VCXOs) to this accuracy, a frequency that is an exact multiple of Port A3 on the PIC is normally maintained also usually temperature-controlled, are 256Hz is initially chosen. Refer to the circuit at a high impedance, by setting it as an input. available, but are expensive and only occa- diagram, Fig 1. Every second, except for the single case sionally appear on the second-hand surplus A straightforward crystal oscillator is built where the error value is zero, this port is set market as part of test equipment. Brooks with CMOS gates, with a varicap connected as an output and strobed high or low, de- Sheera, W5OJM, has designed an excel- across the crystal to shift its frequency pending on the sign of the frequency / phase lent GPS-locked high-stability frequency either side of nominal by a few tens of hertz. error. The duration of the strobe pulse is source using such an oscillator, which was Choose the varicap and coupling capaci- proportional to the magnitude of the error so described in QST, July 1998. This does tors to ensure that it is not possible to pull the that an error count of 128 leads to a strobe require several hours to achieve lock up and frequency more than 128Hz over the full pulse of 640ms, either high or low, down to is the sort of precision test equipment that input voltage swing of 0 - 5V. This oscillator the minimum resolution of 5ms for an error should be left running continuously and not drives a synchronous 8-bit counter made count of one. This strobe pulse is then taken be turned off every day. from a pair of 74HC161 chips, the eight via an RC network to drive the varicap on the However, where short term stability is of outputs from which are connected to a VCXO. The RC constants were determined less importance, another technique can be 74HC374, 8-bit D-type latch. This is trig- by a combination of experience, trial and used. The source described here is based gered by the rising edge of the 1PPS (pulse error, serendipity and luck to give an accept- roughly on the old ‘Huff and Puff’ stabiliser, per second) signal from a GPS receiver so able compromise between lock-up time, first described by Klaus Spaargaren, that, each second, the output of the latch chirp and pull in range. To assist lock-up, the PA0KSB, in 1973. This design stabilised a contains the lowest significant eight bits of PIC software after turn-on applies a precise ‘good’ LC-tuned VCO to give it crystal oscil- the count. This counter overflows many square-wave to the charge pump for 20 lator stability, in steps of 10Hz. In essence, times for each counting interval but, for any seconds, to force the capacitor to mid- the design used a 1-bit frequency counter - frequency that is an exact multiple of 256Hz, voltage, and the frequency near to the nomi- a single flip-flop clocked by pulses divided the counter will overflow to the same point nal operating frequency. The loop then has down to 10Hz from a crystal oscillator. De- each time, and the count latched by each only to make minor corrections to get the pending on whether the VCO frequency seconds pulse will then be a constant correct frequency and phase (the counter was high or low of the appropriate 10Hz number. If the frequency is not a multiple of mid-point). The use of a three-state high- step, the output of the flip-flop ends up at a 256Hz, but is still an exact 1Hz multiple, the impedance port which is only briefly pulled 1 or 0 and is applied via a low pass filter to a count will change from one second to the high or low considerably reduces the re- varicap on the LC oscillator, which is ramped next in a predictable manner. For example, sidual chirp over that of a continuously * 15 Noble Road, Hedge End, Southampton SO30 0PH. a 5MHz signal would give successive counts changing low-impedance connection, as in E-mail: [email protected] (assuming a start at zero) of 00, 64, 128, the original PA0KSB concept. 46 RadCom ♦ October 2002 Technical Feature As an additional aid to debugging, the always averages out the clockwise and anti- second signalling element, the net phase error value is output from the PIC as an clockwise rotations to zero. The error value shift is very close to zero. An LED flashes RS232 signal at 1200 baud. The format is a transmitted from the RS232 port usually sta- with the 1PPS signal, and the duration of decimal number ranging from -128 to 127, bilised at a small positive number rather than flash is related to the width of the charge followed by a space, for display on a stand- zero. The reason for this is not clear, but may pump pulse. Therefore, when locked, the ard ASCII terminal. be due to leakage around the charge pump LED gives a short flash but, during the lock- circuitry, or rectification of the RF in the up phase, the flash is of varying duration and, PERFORMANCE varicap causing a constant offset. Its effect if the GPS pulse is not present, the LED does WITH THE RC VALUES and varicap speci- does not appear to be important to operation. not flash at all. fied, and after the 20s initialisation period, the Without programming-in the 20s initialisation loop was fully-stabilised after running for about period, there were times, depending on the CONSTRUCTION two minutes. The frequency as measured on initial random starting count, when the loop AND SETTING UP a counter was exact, when using a 10s would fail to lock up at all, and other times THE CIRCUIT LAYOUT is not critical, apart counter gating time. By monitoring the output when lock would occur after a few minutes. from that around the VCXO. Here, wires on a vectorscope referenced to a high stabil- By using the output as a clock for my need to be as short as possible and the loop ity source, every second, on average, the AD9850 DDS module, the output frequency filter components need to be mounted close phase would rapidly rotate by a value be- is divided down and the phase blip is reduced to the varicap to avoid picking up interfer- tween 180 to 500° (0.5 to 1.5 cycles), then by the same proportion.