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System Controller Hardware and Embedded Software for the Petite Amateur Navy Satellite (Pansat)

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System Controller Hardware and Embedded Software for the Petite Amateur Navy Satellite (Pansat) NPS ARCHIVE 1997 HORNING, J. I NAVAL POSTGRADUATE SCHOOL Monterey, California THESIS SYSTEM CONTROLLER HARDWARE AND EMBEDDED SOFTWARE FOR THE PETITE AMATEUR NAVY SATELLITE (PANSAT) by James Anthony Horning September 1997 Thesis Advisor: Rudolf Panholzer Co-Advisor: Randy L. Wight Approved for public release; distribution is unlimited. / 'X LIBRARY "<TGRADUAT£SCHOOL 'feKBYCA 93943*101 REPORT DOCUMENTATION PAGE Form Approved OMB No. 0704-0188 Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instruction, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302, and to the Office of Management and Budget, Paperwork Reduction Project (0704-0188) Washington DC 20503. 1 . AGENCY USE ONLY (Leave 2. REPORT DATE 3 . REPORT TYPE AND DATES blank) September 1997 COVERED Master's Thesis 4. TITLE AND SUBTITLE System Controller Hardware and Embedded 5. FUNDING NUMBERS Software for the Petite Amateur Navy Satellite (PANSAT) 6. AUTHOR(S) Horning, James Anthony 7 . PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING Naval Postgraduate School ORGANIZATION Monterey CA 93943-5000 REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSORING/MONITORING AGENCY REPORT NUMBER 1 . SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. 12a. DISTRIBUTION/AVAILABILITY STATEMENT 12b. DISTRIBUTION CODE Approved for public release; distribution is unlimited. 1 3 . ABSTRACT (maximum 200 words) This thesis documents the design of the hardware and embedded software of a digital computer that provides autonomous control of the PANSAT spacecraft. The system was designed for use during a two year mission in a low earth orbit. The computer uses an Intel M80C186XL running at 7.3728 MHz, 512 kbytes of error-detection and correction RAM, 64 kbytes of ROM, and standard CMOS components to provide a general purpose microcomputer. The purpose of the computer is to control all subsystems of the spacecraft, perform analog-to-digital conversions, orchestrate duplicate hardware components to provide redundancy, and upload new software from a ground station. The hardware system was built on printed circuit boards which were manufactured by the Space System Academic Group and tested for proper operation. The embedded software was coded using 80186 Assembler and the C programming language, tested for proper operation, and placed into ROM as firmware. 14. SUBJECT TERMS PANSAT, Digital Computer, Embedded System, Device Drivers, 15. NUMBER OF Spacecraft Control PAGES 302 16. PRICE CODE 17. SECURITY CLASSIFI- 18. SECURITY CLASSIFI- 19. SECURITY CLASSIFI- 20. LIMITATION OF CATION OF REPORT CATION OF THIS CATION OF ABSTRACT Unclassified PAGE ABSTRACT UL Unclassified Unclassified NSN 7540-01-280-5500 Standard Form 298 (Rev. 2-89) Prescribed by ANSI Std. 239-18 298-102 Approved for public release; distribution is unlimited. SYSTEM CONTROLLER HARDWARE AND EMBEDDED SOFTWARE FOR THE PETITE AMATEUR NAVY SATELLITE (PANSAT) James Anthony Horning Naval Postgraduate School B.S.C.S., California Polytechnic - San Luis Obispo, 1989 Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL 9U0LEYKNOX LIBRARY NAVAL POSTGRADUATE SCHOOL 93943-5101 : 'EY CA ABSTRACT This thesis documents the design of the hardware and embedded software of a digital computer that provides autonomous control of the PANSAT spacecraft. The system was designed for use during a two year mission in a low earth orbit. The computer uses an Intel M80C186XL running at 7.3728 MHz, 512 kbytes of error-detection and correction RAM, 64 kbytes of ROM, and standard CMOS components to provide a general purpose microcomputer. The purpose of the computer is to control all subsystems of the spacecraft, perform analog-to-digital conversions, orchestrate duplicate hardware components to provide redundancy, and upload new software from a ground station. The hardware system was built on printed circuit boards which were manufactured by the Space System Academic Group and tested for proper operation. The embedded software was coded using 80186 Assembler and the C programming language, tested for proper operation, and placed into ROM as firmware. VI TABLE OF CONTENTS I. INTRODUCTION 1 A. Purpose 1 B. Scope 1 II. BACKGROUND INFORMATION 3 A. THE PANSAT PROJECT 3 B. MISSION LIFE AND OPERATING ENVIRONMENT : 4 1. Thermal Environment 4 2. Operational Environment 5 3. Radiation Environment 5 C. RADIATION EFFECTS ON ELECTRONICS 5 1. Single Event Effects 5 2. Single Event Effects Experienced by PANSAT 6 D. DOCUMENTATION CONVENTIONS 6 1. Numbering 6 2. Signal Names 6 3. Logic Expressions 6 4. Software Flow Diagrams 7 III. PANSAT ELECTRONICS AND SOFTWARE OVERVIEW 9 A. DESIGN CONSTRAINTS AND TRADEOFFS 9 B. PANSAT SUBSYSTEM HARDWARE GENERAL DESCRIPTION 10 C. SYSTEM CONTROLLER ORGANIZATIONAL OVERVIEW 11 1. Hardware Organization 12 2. Software Organization 14 IV. SYSTEM CONTROLLER HARDWARE 17 A. MICROPROCESSOR 17 1. Reset Circuitry and Timing 17 2. Input Clock 17 3. Interrupts and Direct Memory Access 18 4. Memory and Chip Selects 19 5. Timers 20 B. POWER SENSING AND REGULATION 20 1. Power On Detection 20 2. DC-DC Conversion 22 C. PERIPHERAL DATA BUS 23 1. Programmable Peripheral Interface 23 2. Peripheral Control Bus (PCB) 23 3. Modem Control Interface 24 4. CPU Signal Isolation and Latching 25 5. Signal Timing to Modem Board 26 D. MEMORY 26 l.ROM 29 2. Error Detection and Correction 29 a. Existing Design 29 b. Modifications of the Write Back Control 29 vii 1 c. Modification of the Reset Circuitry 30 d. Modification of the EDAC Error Acknowledge 3 e. Modification of the Transceiver Enables 31 E. ANALOG-TO-DIGITAL CONVERSION 31 1. A/D Converter 32 2. Analog Switch 32 3. Voltage Clamping and Low-pass Filter 33 4. Wiring 33 5. Connector 33 6. Temperature Sensing IC 34 F. SERIAL COMMUNICATIONS 34 1. Serial Communications Controller 34 2. RS-232 Drivers and Receivers 36 3. Connector 36 V. SYSTEM CONTROLLER SOFTWARE DRIVERS 37 A. DESCRIPTION 37 B. HIERARCHY AND MODULE RELATIONSHIPS 38 C. STARTUP 38 1. Hardware Initialization 39 2. Memory Check and Clear 40 3. Data Relocation 40 4. Floatingpoint Emulation 41 5. C Runtime 41 D. CPU SUPPORT 42 1. Timers and Interrupts 42 a. Timers 42 b. Interrupt Priority Structure 43 2. EDAC (Setup and RAM Wash) 44 a. Initial RAM Clearing 45 b. RAM Wash 45 c. Processing a Single Bit Error 46 d. Processing a Dual Bit Error 46 E.MAIN 46 F. PROGRAMMABLE PERIPHERAL INTERFACE 48 1. EDAC Control 48 2. Peripheral Control Bus 48 3. PPI Control Interface 48 4. Peripherals of the Control Bus 48 5. Reading from the Control Bus 49 6. Writing to the Control Bus 49 7. Software Interface 49 a. Application Programming Interface 49 b. Timing Requirements 50 G. ELECTRICAL POWER SUBSYSTEM 50 1. EPS Port Organization 50 2. EPS Cell Voltage Multiplexing 51 a. Low Battery Cell Voltage Selections 51 b. Medium Battery Cell Voltage Selections 51 c. High Battery Cell Voltage Selections 51 3. EPS Cell Voltage and Current Multiplexing 51 H. SERIAL COMMUNICATIONS 52 1. Modem Control 52 2. RF Control 52 vni . 3. SCC Drivers 53 a. Asynchronous Services 54 b. Synchronous Services 54 I. TELEMETRY 54 1. Scheduling of the LM12H458 54 2. LM12H458 Setup and Interrupt Service Routines 55 3. Data Gathering - Temperature Multiplexers 57 4. Data Conversion 57 a. Battery Current Conversion 57 b. Spacecraft Bus Current Conversion 58 c. Battery Voltage Conversions 58 d. Thermistors 59 e. Temperature Sensors (ICs) 59 5. Data Recording 59 J. MASS STORAGE INTERFACE 60 1 Hardware Interface Via the PCB 60 2. Software Interface 61 a. Reading and Writing Requirements 62 b. API Functions 62 c. Timing Requirements 63 VI. SYSTEM CONTROLLER HIGH-LEVEL SOFTWARE 65 A. DESCRIPTION 65 B. SERIAL COMMUNICATIONS - Serial Test Port Interface 65 C. BATTERY CHARGE MONITOR 67 l.BCM Top Level 67 2. Battery Use Eligibility And Preference 69 3. Determine Online Battery 71 4. Determine Target Battery 73 5. Charging Methods 75 a. Overcharge 75 b. Recharge 76 6. Battery Mode 77 D. GROUND STATION COMMAND INTERFACE 78 1. Command Packet Protocol 78 2. Commands 79 a. Confirm 79 b. Control 79 c. Execute 79 d. Get Parameters 79 e. Load 79 f Map 79 g Reset..., 80 h. Set Parameters 80 i. Status 80 j. Status Log Clear 80 k. Status Log Read 80 I. Venf> 80 m. Unknown 81 3. Loading Sequence 81 E. SCENARIO CHECKS 82 VII. RESULTS, RECOMMENDATIONS, AND CONCLUSION 83 A. RESULTS 83 IX 1. Printed Circuit Board 83 2. Use of In-Circuit Emulator 83 3. Software 84 4. Testing 85 B. RECOMMENDATIONS 85 C. CONCLUSION 85 APPENDIX A. HARDWARE SCHEMATICS 87 APPENDIX B. SYSTEM CONTROLLER CONNECTOR PIN-OUTS 93 APPENDIX C. CIRCUIT BOARD BILL OF MATERIALS 97 APPENDIX D. PERIPHERAL CONTROL BUS PROGRAMMABLE PERIPHERAL INTERFACE PORT CONFIGURATION 101 APPENDIX E. ELECTRICAL POWER SYSTEM PORT CONFIGURATION...103 APPENDIX F. A/D ACQUISITION 107 APPENDIX G. THERMISTOR TEMPERATURE CONVERSIONS 109 APPENDIX H. SPACECRAFT COMMAND ENCODING 113 APPENDIX I. SOFTWARE GENERATION FACILITIES 115 APPENDIX J. SOFTWARE SOURCE CODE 119 APPENDIX K. TEST PLANS 285 LIST OF REFERENCES 289 INITIAL DISTRIBUTION LIST 291 I. INTRODUCTION A. Purpose The purpose of this thesis is to document the design of a system that implements the digital computer of the Petite Amateur Navy Satellite (PANSAT).
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