LTC3550 Dual Input USB/AC Adapter Li-Ion with 600mA Buck Converter

FEATURES DESCRIPTIO U ■ Charges Single-Cell Li-Ion Battery from Wall The LTC®3550 is a standalone linear charger with a 600mA Adapter and USB Inputs monolithic synchronous buck converter. It is capable of ■ Automatic Input Power Detection and Selection charging a single-cell Li-Ion battery from both wall adapter ■ Charge Current Programmable Up to 950mA from and USB inputs. The charger automatically selects the Wall Adapter Input appropriate power source for charging. ■ Adjustable Output, High Effi ciency 600mA Internal thermal feedback regulates the battery charge Synchronous DC/DC Converter current to maintain a constant die temperature during high ■ No External MOSFET, Sense Resistor or Blocking power operation or high ambient temperature conditions. Diode Needed The fl oat voltage is fi xed at 4.2V and the charge currents ■ Thermal Regulation Maximizes Charge Rate Without are programmed with external resistors. The LTC3550 Risk of Overheating* terminates the charge cycle when the charge current ■ Preset Charge Voltage with ±0.6% Accuracy drops below the programmed termination threshold after ■ Programmable Charge Current Termination the fi nal fl oat voltage is reached. With power applied to ■ 1.5MHz Constant Frequency Operation (Step-Down both inputs, the LTC3550 can be put into shutdown mode Converter) reducing the DCIN supply current to 20μA, the USBIN ■ 18μA USB Suspend Current in Shutdown supply current to 10μA, and the battery drain current to ■ “Power Present” Status Output less than 2μA. ■ Charge Status Output ■ Automatic Recharge The DC/DC converter switching frequency is internally ■ Available in a Thermally Enhanced, Low Profi le set at 1.5MHz, allowing the use of small surface mount

(0.75mm) 16-Lead (5mm × 3mm) DFN Package inductors and capacitors. U , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S *Protected by U.S. patents, includng 6522118, 6700364, 6580258, 5481178, 6304066, 6127815, 6498466, 6611131

■ Cellular Telephones U

TYPICAL APPLICATIO Complete Charge Cycle (1100mA Battery) Dual Input Battery Charger and DC/DC Converter 1000 800 600 2.2µH V OUT 400

SW 1.2V CHARGE 600mA 200 COUT CURRENT (mA) 0 LTC3550 10µF CONSTANT VOLTAGE 22pF 301k 4.2 CER WALL 4.0 DCIN VFB ADAPTER 3.8 USBIN = 5V RUN 301k TA = 25°C USB BATTERY 3.6 USBIN V 800mA (WALL) VOLTAGE (V) RIDC = 1.24k PORT CC 3.4 µ 500mA (USB) RIUSB = 2k 1 F IUSB BAT 5.0 2k 4.7µF 2.5 1% IDC ITERM

4.2V DCIN 1µF GND 2k + 0 1.24k SINGLE-CELL 1% VOLTAGE (V) 1% Li-Ion BATTERY 0 0.5 1.01.5 2.0 2.5 3.0

3550 TA01 TIME (HR) 3550 TA02 3550fa 1

LTC3550

WW U W W

ABSOLUTE AXI U RATI GS PACKAGE/ORDER IUU FOR ATIO (Note 1) DCIN, USBIN ...... –0.3V to 10V TOP VIEW EN, C⎯H⎯R⎯G,⎯ P⎯W⎯R,⎯ HPWR ...... –0.3V to 10V USBIN 1 16 DCIN BAT, IDC, IUSB, ITERM ...... –0.3V to 7V IUSB 2 15 BAT ITERM 3 14 IDC VCC ...... –0.3V to 6V PWR 4 13 HPWR RUN, V ...... –0.3V to V 17 FB CC CHRG 5 12 EN SW (DC) ...... –0.3V to (V + 0.3V) CC V 6 11 RUN DCIN Pin Current (Note 2) ...... 1A FB VCC 7 10 SW USBIN Pin Current (Note 2) ...... 700mA GND 8 9 GND BAT Pin Current (Note 2) ...... 1A DHC PACKAGE × P-Channel SW Source Current (DC) ...... 800mA 16-LEAD (5mm 3mm) PLASTIC DFN θ N-Channel SW Source Current (DC) ...... 800mA TJMAX = 125°C, JA = 40°C (NOTE 4) Peak SW Sink and Source Current ...... 1.3A EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB Operating Temperature Range (Note 3) ... –40°C to 85°C ORDER PART NUMBER DHC PART MARKING Maximum Junction Temperature ...... 125°C LTC3550EDHC 3550 Storage Temperature Range ...... –65°C to 125°C Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDCIN = 5V, VUSBIN = 5V, VCC = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ● VDCIN Wall Adapter Input Supply Voltage 4.3 8 V ● VUSBIN USB Port Input Supply Voltage 4.3 8 V ● VCC Buck Regulator Input Supply Voltage 2.5 5.5 V

VEN EN Input Threshold Voltage 0.4 0.7 1.0 V

REN EN Pull-Down Resistance 1.2 2 5 MΩ ● VRUN RUN Threshold Voltage 0.3 1 1.5 V ● IRUN RUN Leakage Current ±0.01 ±1 µA ⎯⎯⎯⎯ VC⎯H⎯R⎯G⎯ CHRG Output Low Voltage IC⎯H⎯R⎯G⎯ = 5mA 0.35 0.6 V ⎯⎯⎯ VP⎯W⎯R⎯ PWR Output Low Voltage IP⎯W⎯R⎯ = 5mA 0.35 0.6 V

VHPWR HPWR Input Threshold Voltage 0.4 0.7 1 V ● RHPWR HPWR Pull-Down Resistance 125 MΩ

VUVDC DCIN Undervoltage Lockout Voltage From Low to High 4.0 4.15 4.3 V Hysteresis 200 mV

VUVUSB USBIN Undervoltage Lockout Voltage From Low to High 3.8 3.95 4.1 V Hysteresis 200 mV

VASD-DC VDCIN – VBAT Lockout Threshold Voltage VDCIN from Low to High, VBAT = 4.2V 140 180 220 mV VDCIN from High to Low, VBAT = 4.2V 20 50 80 mV

VASD-USB VUSBIN – VBAT Lockout Threshold VUSBIN from Low to High, VBAT = 4.2V 140 180 220 mV Voltage VUSBIN from High to Low, VBAT = 4.2V 20 50 80 mV

3550fa 2 LTC3550

ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDCIN = 5V, VUSBIN = 5V, VCC = 3.6V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Charger

IDCIN DCIN Supply Current ● Charge Mode (Note 5) RIDC = 10k 250 800 µA Standby Mode Charge Terminated ● 50 100 µA Shutdown Mode ENABLE = 5V 20 40 µA

IUSBIN USBIN Supply Current ● Charge Mode (Note 6) RIUSB = 10k, VDCIN = 0V 250 800 µA Standby Mode Charge Terminated ● 50 100 µA Shutdown Mode VDCIN = 0V, ENABLE = 0V 18 36 µA Shutdown Mode VDCIN > VUSBIN 10 20 µA

VFLOAT Regulated Output (Float) Voltage IBAT = 1mA 4.175 4.2 4.225 V IBAT = 1mA, 0°C < TA < 85°C 4.158 4.2 4.242 V

IBAT BAT Pin Current ● Constant-Current Mode RIDC = 1.25k 760 800 840 mA ● Constant-Current Mode RIUSB = 2.1k 450 476 500 mA ● Constant-Current Mode RIDC = 10k or RIUSB = 10k 93 100 107 mA Standby Mode Charge Terminated –3 –6 µA Shutdown Mode Charger Disabled –1 –2 µA Sleep Mode DCIN = 0V, USBIN = 0V ±1 ±2 µA

VIDC IDC Pin Regulated Voltage Constant-Current Mode 0.95 1.0 1.05 V

VIUSB IUSB Pin Regulated Voltage Constant-Current Mode 0.95 1.0 1.05 V ● ITERMINATE Charge Current Termination Threshold RITERM = 1k 90 100 110 mA ● RITERM = 2k 45 50 55 mA ● RITERM = 10k 8.5 10 11.5 mA ● RITERM = 20k 4 5 6 mA

ITRIKL Trickle Charge Current VBAT < VTRIKL; RIDC = 1.25k 60 80 100 mA VBAT < VTRIKL; RIUSB = 2.1k 30 47.5 65 mA

VTRIKL Trickle Charge Threshold Voltage VBAT Rising 2.8 2.9 3V Hysteresis 100 mV

ΔVRECHRG Recharge Battery Threshold Voltage VFLOAT – VRECHRG, 0°C < TA < 85°C 65 100 135 mV tRECHRG Recharge Comparator Filter Time VBAT from High to Low 3 6 9 ms tTERMINATE Termination Comparator Filter Time IBAT Drops Below Termination Threshold 0.8 1.5 2.2 ms tSS Soft-Start Time IBAT = 10% to 90% Full-Scale 175 250 325 µs

RON-DC Power FET On-Resistance (Between 400 mΩ DCIN and BAT)

RON-USB Power FET On-Resistance (Between 550 mΩ USBIN and BAT)

TLIM Junction Temperature in Constant- 105 °C Temperature Mode Switching Regulator

VFB Regulated Feedback Voltage TA = 25°C 0.5880 0.6 0.6120 V 0°C ≤ TA ≤ 85°C 0.5865 0.6 0.6135 V ● –40°C ≤ TA ≤ 85°C 0.5850 0.6 0.6150 V ● ΔVFB Reference Voltage Line Regulation 0.04 0.4 %/V

IPK Peak Inductor Current VCC = 3V, VFB = 0.5V 0.75 1 1.25 A

VLOADREG Output Voltage Load Regulation 0.5 %

3550fa 3 LTC3550

ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDCIN = 5V, VUSBIN = 5V, VCC = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IS VCC Supply Current (Note 7) Active Mode VFB = 0.5V, ILOAD = 0A 300 400 µA Sleep Mode VFB = 0.62V, ILOAD = 0A 20 35 µA Shutdown VRUN = 0V, VCC = 5.5V 0.1 1 µA fOSC Oscillator Frequency VFB = 0.6V 1.2 1.5 1.8 MHz VFB = 0V 210 kHz Ω RPFET RDS(ON) of P-Channel FET 0.4 Ω RNFET RDS(ON) of N-Channel FET 0.35

ILSW SW Leakage Current 0.01 ±1 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Supply Current includes IDC and ITERM pin current (approx- may cause permanent damage to the device. Exposure to any Absolute imately 100μA each) but does not include any current delivered to the Maximum Rating condition for extended periods may affect device battery through the BAT pin (approximately 100mA). reliability and lifetime. Note 6: Supply Current includes IUSB and ITERM pin current (approx- Note 2: Guaranteed by long term current density limitations. imately 100μA each) but does not include any current delivered to the Note 3: The LTC3550E is guaranteed to meet the performance battery through the BAT pin (approximately 100mA). specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C Note 7: Dynamic supply current is higher due to the gate charge being operating temperature range are assured by design, characterization and delivered at the switching frequency. correlation with statistical process controls. Note 4: Failure to solder the exposed backside of the package to the PC board will result in a thermal resistance much higher than 40°C/W. See Thermal Considerations.

3550fa 4

LTC3550 UW

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Regulated Charger Output (Float) Regulated Charger Output (Float) IDC Pin Voltage vs Temperature Voltage vs Charge Current Voltage vs Temperature (Constant-Current Mode) 4.26 4.220 1.008 VDCIN = VUSBIN = 5V VDCIN = VUSBIN = 5V 4.24 4.215 1.006

4.22 4.210 1.004

4.20 4.205 1.002 VDCIN = 8V (V) (V) 4.18 4.200 (V) 1.000 IDC FLOAT FLOAT V V V V = 4.3V 4.16 4.195 0.998 DCIN RIDC = RIUSB = 2k RIDC = 1.25k 4.14 4.190 0.996

4.12 4.185 0.994

4.10 4.180 0.992 0 100 200 300 400 500 600 700 800 –50 –25 05025 75 100 –50 –25 025 50 75 100 CHARGE CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)

3550 G01 3550 G02 3550 G03

IUSB Pin Voltage vs Temperature IUSB Pin Voltage vs Temperature (Constant-Current Mode) (Constant-Current Mode) Charge Current vs IDC Pin Voltage 1.008 0.208 900 HPWR = 5V HPWR = 0V VDCIN = 5V 1.006 0.206 800 700 1.004 0.204 RIDC = 1.25k 600 1.002 0.202 V = 8V RIDC = 2k VUSBIN = 8V USBIN 500 (V) (V)

1.000 0.200 (mA) IUSB IUSB 400 BAT V V VUSBIN = 4.3V I 0.998 VUSBIN = 4.3V 0.198 300 0.196 0.996 200 RIDC = 10k 0.994 0.194 100

0.992 0.192 0 –50 –25 025 50 75 100 –50 –25 025 50 75 100 0 0.20.4 0.60.8 1.0 1.2 ° TEMPERATURE ( C) TEMPERATURE (°C) VIDC (V)

3550 G04 3550 G43 3550 G05 Charge Current vs IUSB Pin Voltage P⎯W⎯R⎯ Pin I-V Curve C⎯H⎯R⎯G⎯ Pin I-V Curve 900 35 35 VUSBIN = 5V VDCIN = VUSBIN = 5V VDCIN = VUSBIN = 5V T = –40°C T = –40°C 800 30 A 30 A RIUSB = 1.25k 700 T = 25°C T = 25°C 25 A 25 A 600 TA = 90°C TA = 90°C RIUSB = 2k 500 20 20 (mA) (mA) (mA) 400

PWR 15 15 BAT CHRG I I I 300 10 10 200 RIUSB = 10k 5 5 100

0 0 0 0 0.20.4 0.60.8 1.0 1.2 0 1235467 03512 467 VIUSB (V) VPWR (V) VCHRG (V)

3550 G06 3550 G07 3550 G08

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LTC3550 UW

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Charge Current Charge Current vs Ambient Temperature vs DCIN Voltage Charge Current vs Battery Voltage 1000 900 1000 ONSET OF ONSET OF THERMAL REGULATION THERMAL REGULATION 800 800 800 RIDC = 1.25k 700 600 600 (mA) (mA) (mA) 600

R = R = 2k BAT BAT BAT IDC IUSB I I I 400 400 500

200 R = 1.25k 200 VDCIN = VUSBIN = 5V 400 IDC VDCIN = VUSBIN = 5V VBAT = 4V VBAT = 4V θ = 40°C/W θ ° JA θJA = 40°C/W JA = 40 C/W RIDC = 1.25k 0 300 0 –50–25 0 2550 75 100 125 4.0 4.55.0 5.5 6.0 6.5 7.0 7.5 8.0 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 TEMPERATURE (°C) VDCIN (V) VBAT (V)

3550 G10 3550 G11 3550 G12

DCIN Power FET On-Resistance USBIN Power FET On-Resistance EN Pin Threshold Voltage vs Temperature vs Temperature (On-to-Off) vs Temperature 550 800 900 V = 4V VBAT = 4V BAT VDCIN = VUSBIN = 5V IBAT = 200mA 750 IBAT = 200mA 500 850 700

450 650 800 ) ) Ω Ω 600 (m (m

400 (mV) 750

550 EN V DS(ON) DS(ON) R 350 R 500 700

450 300 650 400

250 350 600 –50 –25 0 2550 75 100 125 –50–25 0 2550 75 100 125 –50–25 0 2550 75 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

3550 G13 3550 G14 3550 G15

DCIN Shutdown Current USBIN Shutdown Current HPWR Pin Threshold Voltage vs Temperature vs Temperature (Rising) vs Temperature 50 45 900 VDCIN = VUSBIN = 5V 45 40 40 850 35 VDCIN = 8V 35 VUSBIN = 8V 30 800 30 A) A) µ µ 25 (mV) ( ( 25 750 VDCIN = 5V 20 DCIN V = 5V HPWR I 20 USBIN USBIN I V 15 15 700 VDCIN = 4.3V 10 10 VUSBIN = 4.3V 650 5 5 ENABLE = 5V ENABLE = 0V 0 0 600 –50–25 0 2550 75 100 –50–25 0 2550 75 100 –50–25 0 2550 75 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

3550 G16 3550 G17 3550 G44

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LTC3550 UW

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, unless otherwise noted.

HPWR Pin Pull-Down Resistance EN Pin Pull-Down Resistance Undervoltage Lockout Threshold vs Temperature vs Temperature vs Temperature 2.8 2.8 4.25

4.20 2.6 2.6 DCIN UVLO 4.15 2.4 2.4 ) 4.10 Ω ) Ω (M (V)

2.2 (M 2.2 4.05 UV EN V HPWR R

R 4.00 2.0 2.0 USBIN UVLO 3.95 1.8 1.8 3.90

1.6 1.6 3.85 –50–25 0 2550 75 100 –50–25 0 2550 75 100 –50 –25 05025 75 100 ° TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE ( C)

3550 G45 3550 G19 3550 G18

Recharge Threshold Voltage Battery Drain Current Charge Current During Turn-On vs Temperature vs Temperature and Turn-Off 4.16 5 VBAT = 4.2V VDCIN, VUSBIN (NOT CONNECTED) 4.14 4 IBAT 500mA/DIV 4.12 3 (V) V = V = 4.3V A) DCIN USBIN µ 4.10 ( 2 BAT

V = V = 8V I RECHRG DCIN USBIN V 4.08 1 ENABLE 5V/DIV

4.06 0

4.04 –1 –50 –25 025 50 75 100 –50 –25 0255075 100 VDCIN = 5V 100µs/DIV TEMPERATURE (°C) TEMPERATURE (°C) RIDC = 1.25k

3550 G20 3550 G21 3550 G22 Buck Regulator Effi ciency Buck Regulator Effi ciency Buck Regulator Effi ciency vs VCC vs Output Current vs Output Current 100 95 95 VOUT = 1.8V VOUT = 1.5V 95 IOUT = 100mA IOUT = 10mA 90 VCC = 2.7V 90 90 VCC = 2.7V 85 IOUT = 1mA 85 85 VCC = 4.2V 80 IOUT = 600mA VCC = 4.2V 80 80 75 VCC = 3.6V VCC = 3.6V 75 75 70 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) IOUT = 0.1mA 65 70 70 60 65 65 55 VOUT = 1.8V 50 60 60 2 3 4 5 6 0.11 10 100 1000 0.11 10 100 1000 VCC (V) OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 3550 G24 3550 G25 3550 G23

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LTC3550 UW

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Buck Regulator Effi ciency Buck Regulator Reference Oscillator Frequency vs Output Current Voltage vs Temperature vs Temperature 100 0.614 1.70 VOUT = 2.5V VCC = 3.6V VCC = 3.6V 95 1.65 VCC = 2.7V 0.609 90 1.60 VCC = 3.6V 0.604 85 1.55 VCC = 4.2V 80 0.599 1.50

75 1.45 EFFICIENCY (%)

0.594 FREQUENCY (MHz) 1.40 70 REFERENCE VOLTAGE (V) 0.589 65 1.35

60 0.584 1.30 0.11 10 100 1000 –50 –25 0 2550 75 100 125 –50 –25 0 2550 75 100 125 OUTPUT CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C)

3550 G26 3550 G27 3550 G28 Buck Regulator Output Voltage Oscillator Frequency vs VCC vs Load Current RDS(ON) vs VCC 1.8 1.844 0.7 VCC = 3.6V 1.834 1.7 0.6

1.824 0.5 1.6 MAIN ) SWITCH 1.814 Ω

( 0.4 1.5 1.804 DS(ON) 0.3 SYNCHRONOUS R 1.4 SWITCH FREQUENCY (MHz)

OUTPUT VOLTAGE (V) 1.794 0.2

1.3 1.784 0.1

1.2 1.774 0 2 34 56 0 100200 300 400 500 600 700 800 900 0 1 234657 VCC (V) LOAD CURRENT (mA) VCC (V) 3550 G29 3550 G30 3550 G31

Buck Regulator Switches RDS(0N) Buck Regulator Supply Buck Regulator Supply Current vs Temperature Current vs VCC vs Temperature 0.7 50 50 V = 1.875V VCC = 3.6V VCC = 2.7V OUT 45 I = 0A 45 VOUT = 1.875V 0.6 LOAD VCC = 3.6V ILOAD = 0A VCC = 4.2V 40 40 A) A)

0.5 µ µ 35 35

) 30 Ω 30

( 0.4 25 25

DS(ON) 0.3 20

R 20

0.2 15 15 SUPPLY CURRENT ( SUPPLY CURRENT ( 10 10 0.1 MAIN SWITCH 5 5 SYNCHRONOUS SWITCH 0 0 0 –50 –25 0 2550 75 100 125 2 3 4 5 6 –50 –25 0 25 50 75 100 125 ° TEMPERATURE (°C) VCC (V) TEMPERATURE ( C)

3550 G32 3550 G33 3550 G34

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LTC3550 UW

TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Switch Leakage Current vs Temperature Switch Leakage Current vs VCC 300 120 VCC = 5.5V RUN = 0V RUN = 0V 250 100 SYNCHRONOUS SWITCH 200 80

150 60 MAIN SWITCH 100 40 SWITCH LEAKAGE (nA) SWITCH LEAKAGE (pA) MAIN SWITCH 50 20 SYNCHRONOUS SWITCH

0 0 –50 –25 0 2550 75 100 125 0 1 23456 TEMPERATURE (°C) VCC (V)

3550 G35 3550 G36

Burst Mode Operation Start-Up from Shutdown Load Step

RUN SW VOUT 2V/DIV 5V/DIV 100mV/DIV VOUT AC COUPLED V 1V/DIV OUT I 100mV/DIV L 500mA/DIV AC COUPLED I I LOAD L 500mA/DIV I 200mA/DIV LOAD 500mA/DIV

3550 G37 µ 3550 G38 V = 3.6V 20µs/DIV 3550 G39 VCC = 3.6V 4µs/DIV VCC = 3.6V 40 s/DIV CC V = 1.8V VOUT = 1.8V VOUT = 1.8V OUT I = 0mA TO 600mA ILOAD = 50mA ILOAD = 600mA LOAD

Load Step Load Step Load Step

V VOUT OUT VOUT 100mV/DIV 100mV/DIV 100mV/DIV AC COUPLED AC COUPLED AC COUPLED

IL I IL L 500mA/DIV 500mA/DIV 500mA/DIV

I ILOAD LOAD ILOAD 500mA/DIV 500mA/DIV 500mA/DIV

µ 3550 G40 V = 3.6V 20µs/DIV 3550 G41 3550 G42 VCC = 3.6V 20 s/DIV CC VCC = 3.6V 20µs/DIV V = 1.8V VOUT = 1.8V OUT VOUT = 1.8V I = 100mA TO 600mA ILOAD = 50mA TO 600mA LOAD ILOAD = 200mA TO 600mA

3550fa 9 LTC3550

PI FU CTIO SUUU

USBIN (Pin 1): USB Input Supply Pin. Provides power to VFB (Pin 6): Voltage Feedback Pin. Receives the feedback the battery charger. The maximum supply current is 650mA. voltage from an external resistor divider across the buck This should be bypassed with a 1µF capacitor. regulator output.

IUSB (Pin 2): USB Charge Current Program and Monitor VCC (Pin 7): Buck Regulator Input Supply Pin. Must be Pin. The charge current can be set by connecting a resis- closely decoupled to GND (Pins 8, 9) with a 2.2µF or tor, RIUSB, to ground. When charging in constant-current greater ceramic capacitor. mode, this pin servos to 1V. The voltage on this pin can GND (Pins 8, 9): Ground. be used to measure the charge current delivered from the USB input using the following formula: SW (Pin 10): Buck Regulator Switch Node Connection to Inductor. This pin connects to the drains of the internal VIUSB IBAT = •1000 main (top) and synchronous (bottom) power MOSFET RIUSB switches. ITERM (Pin 3): Termination Current Threshold Program RUN (Pin 11): Buck Regulator Run Control Input. Forcing Pin. The current termination threshold, ITERMINATE, can be this pin above 1.5V enables the regulator. Forcing this pin set by connecting a resistor, RITERM, to ground. ITERMINATE below 0.3V shuts it down. In shutdown, all buck regulator is set by the following formula: functions are disabled drawing <1µA supply current from VCC. Do not leave RUN fl oating. = 100V ITERMINATE EN (Pin 12): Charger Enable Input. A logic low on this pin RITERM enables the charger. If this input is left fl oating, an internal When the charge current, IBAT, falls below the termination 2MΩ pull-down resistor defaults the LTC3550 to charge threshold, charging stops and the C⎯H⎯R⎯G⎯ output becomes mode. Pull this pin high to disable the charger. high impedance. HPWR (Pin 13): USB High/Low Power Mode Select Input. This pin is internally clamped to approximately 1.5V. Driv- Used to control the amount of current drawn from the ing this pin to voltages beyond the clamp voltage should USB port. A logic high on the HPWR pin sets the charge be avoided. current to 100% of the current programmed by the IUSB P⎯W⎯R⎯ (Pin 4): Open-Drain Status Output. pin. A logic low on the HPWR pin sets the charge current When the DCIN or USBIN pin voltage is suffi cient to to 20% of the current programmed by the IUSB pin. An Ω begin charging (i.e., when the supply is greater than internal 2M pull-down resistor defaults the charger to the undervoltage lockout threshold and at least 180mV its low current state. above the battery terminal), the P⎯W⎯R⎯ pin is pulled low by IDC (Pin 14): Wall Adapter Charge Current Program and an internal N-channel MOSFET. Otherwise, P⎯W⎯R⎯ is high Monitor Pin. The charge current is set by connecting a impedance. The output is capable of sinking up to 10mA, resistor, RIDC, to ground. When charging in constant- making it suitable for driving an LED. current mode, this pin servos to 1V. The voltage on this C⎯H⎯R⎯G⎯ (Pin 5): Open-Drain Charge Status Output. When pin can be used to measure the charge current using the the LTC3550 is charging, the C⎯H⎯R⎯G⎯ pin is pulled low by following formula: an internal N-channel MOSFET. When the charge cycle is V I = IDC •1000 completed, C⎯H⎯R⎯G⎯ becomes high impedance. This output BAT RIDC is capable of sinking up to 10mA, making it suitable for driving an LED. BAT (Pin 15): Charger Output. This pin provides charge current to the battery and regulates the fi nal fl oat voltage to 4.2V.

3550fa 10 LTC3550

PI FU CTIO SUUU DCIN (Pin 16): Wall Adapter Input Supply Pin. Provides Exposed Pad (Pin 17): GND. The exposed backside of the power to the battery charger. The maximum supply package is ground and must be soldered to the PCB ground current is 950mA. This should be bypassed with a 1µF for electrical connection and maximum heat transfer. capacitor.

BLOCK DIAGRA W

DCIN BAT USBIN 16 15 1

CC/CV CC/CV REGULATOR REGULATOR FREQ OSC 6 VFB SHIFT SLOPE COMP

+ +

HPWR 13 + RHPWR I 0.6V

DC USB TH EA 4.15V – SOFT- SOFT- – 3.95V – START START BURST 10mA MAX DCIN UVLO USBIN UVLO PWR 4 CLAMP + +

7 VCC BAT – – BAT 10mA MAX CHRG 5 – + 5Ω ICOMP + 4.1V S Q LOGIC RECHARGE – R Q RECHRG RS LATCH ANTI- BAT SHOOT-

SWITCHING THRU 10 SW TRICKLE – DC_ENABLE USB_ENABLE + TDIE LOGIC THERMAL AND

TRICKLE CHARGER CONTROL BLANKING

CHARGE REGULATION + + CIRCUIT

TERM 105°C

2.9V – I RCMP–

EN 12

R + 100mV EN IBAT IBAT IBAT TERMINATION /1000 /1000 /1000 –

3 14 2 11 ITERMIDC IUSB RUN 8, 9, 17 3550 BD GND RITERM RIDC RIUSB

3550fa 11 LTC3550

OPERATIOU The LTC3550 consists of two main blocks: a lithium-ion Lithium-Ion Battery Charger battery charger and a high-effi ciency buck converter that A charge cycle begins when the voltage at either the DCIN pin can be powered from the battery. The charger is designed or USBIN pin rises above the UVLO threshold level and the to effi ciently manage charging of a single-cell lithium-ion charger is enabled through the EN pin. When either input is battery from two separate power sources: a wall adapter supplying power, logic low enables the charger and logic high and USB power bus. The internal P-channel MOSFETs disables it (a 2MΩ pull-down defaults the charger to the can supply up to 950mA from the wall adapter source charging state). The DCIN input draws 20µA when the and 500mA from the USB power source. The fi nal fl oat charger is in shutdown. The USBIN input draws 18µA voltage accuracy is ±0.6%. during shutdown if no power is applied to DCIN, but draws The buck converter uses a constant frequency, current only 10µA when VDCIN > VUSBIN. mode step-down architecture. Both the main (P-channel Once the charger is enabled, it enters constant-current MOSFET) and synchronous (N-channel MOSFET) switches mode, where the programmed charge current is supplied for the buck converter are internal. The LTC3550 requires to the battery. When the BAT pin approaches the fi nal no external diodes or sense resistors. fl oat voltage (4.2V), the charger enters constant-voltage

STARTUP

DCIN POWER APPLIED ONLY USB POWER APPLIED POWER SELECTION

DCIN POWER USBIN POWER REMOVED REMOVED OR DCIN POWER TRICKLE CHARGE APPLIED TRICKLE CHARGE MODE MODE BAT < 2.9V BAT < 2.9V 1/10th FULL CURRENT 1/10th FULL CURRENT

CHRG STATE: PULLDOWN CHRG STATE: PULLDOWN

BAT > 2.9V BAT > 2.9V

2.9V < BAT CHARGE CHARGE 2.9V < BAT MODE MODE FULL CURRENTÞHPWR = HIGH FULL CURRENT 1/5 FULL CURRENTÞHPWR = LOW

CHRG STATE: PULLDOWN CHRG STATE: PULLDOWN

IBAT < ITERMINATE IBAT < ITERMINATE IN VOLTAGE MODE IN VOLTAGE MODE

STANDBY STANDBY MODE MODE

BAT < 4.1V NO CHARGE CURRENT NO CHARGE CURRENT BAT < 4.1V CHRG STATE: Hi-Z CHRG STATE: Hi-Z

EN EN SHUTDOWN EN DRIVEN HIGH DRIVEN HIGH SHUTDOWN EN MODE DRIVEN LOW MODE DRIVEN LOW m IDCIN DROPS TO 20 A IUSBIN DROPS TO 18mA

CHRG STATE: Hi-Z DCIN POWER USBIN POWER CHRG STATE: Hi-Z REMOVED REMOVED OR DCIN POWER 3550 F01 APPLIED Figure 1. LTC3550 State Diagram of a Charge Cycle 3550fa 12 LTC3550

OPERATIOU mode and the charge current begins to decrease. Once In Burst Mode operation, the peak current of the inductor is the charge current drops below the programmed termina- set to approximately 200mA regardless of the output load. tion threshold (set by the external resistor RITERM), the Each burst event can last from a few cycles at light loads internal P-channel MOSFET is shut off and the charger to almost continuously cycling with short sleep intervals enters standby mode. at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned In standby mode, the charger sits idle and monitors the off, reducing the quiescent current to 20µA. In this sleep battery voltage using a comparator with a 6ms fi lter time state, the load current is being supplied solely from the (t ). A charge cycle automatically restarts when the RECHRG output capacitor. As the output voltage droops, the EA battery voltage falls below 4.1V (which corresponds to ap- amplifi er’s output rises above the sleep threshold signaling proximately 80% to 90% battery capacity). This ensures the BURST comparator to trip and turn the top MOSFET that the battery is kept near a fully charged condition and on. This process repeats at a rate that is dependent on eliminates the need for periodic charge cycle initiations. the load demand. Figure 1 uses a state diagram to describe the behavior of the LTC3550 battery charger. Dropout Operation 600mA Step-Down Regulator As the input supply voltage decreases to a value approach- ing the output voltage, the duty cycle increases toward the The LTC3550 regulator uses a constant frequency, current maximum on-time. Further reduction of the supply voltage mode step-down architecture. Both the top (P-channel forces the main switch to remain on for more than one cycle MOSFET) and bottom (N-channel MOSFET) switches are until it reaches 100% duty cycle. The output voltage will internal. During normal operation, the internal top power then be determined by the input voltage minus the voltage MOSFET is turned on each cycle when the oscillator sets drop across the P-channel MOSFET and the inductor. the RS latch, and is turned off when the current com- parator, ICOMP, resets the RS latch. The peak inductor An important detail to remember is that at low input supply current at which ICOMP resets the RS latch, is controlled voltages, the RDS(ON) of the P-channel switch increases by the output of error amplifi er EA. When the load current (see Typical Performance Characteristics). Therefore, increases, it causes a slight decrease in the output voltage the user should calculate the power dissipation when (VOUT), relative to the internal reference, which in turn the LTC3550 is used at 100% duty cycle with low input causes the EA amplifi er’s output voltage to increase until voltage (See Thermal Considerations in the Applications the average inductor current matches the new load cur- Information section). rent. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, Short-Circuit Protection as indicated by the current reversal comparator IRCMP, or When the regulator output is shorted to ground, the fre- the beginning of the next clock cycle. quency of the oscillator is reduced to about 210kHz, one seventh the nominal frequency. This frequency foldback ® Burst Mode Operation ensures that the inductor current has more time to decay, The LTC3550 buck regulator is capable of Burst Mode thereby preventing runaway. The oscillator’s frequency operation in which the internal power MOSFETs operate will progressively increase to 1.5MHz when VFB rises intermittently based on load current demand. above 0V.

Burst Mode is a registered trademark of Linear Technology Corporation. 3550fa 13 LTC3550

OPERATIOU Battery Charger Power Source Selection Low-Battery Charge Conditioning (Trickle Charge) The LTC3550 can charge a battery from either the wall This feature ensures that deeply discharged batteries are adapter input or the USB port input. The charger automati- gradually charged before applying full charge current . If cally senses the presence of voltage at each input. If both the BAT pin voltage is below 2.9V, the LTC3550 supplies power sources are present, the charger defaults to the wall 1/10th of the full charge current to the battery until the adapter source provided suffi cient power is present at the BAT pin rises above 2.9V. For example, if the charger is DCIN input. “Suffi cient power” is defi ned as: programmed to charge at 800mA from the wall adapter • Supply voltage is greater than the UVLO threshold. input and 500mA from the USB input, the charge current during trickle charge mode would be 80mA and 50mA, • Supply voltage is greater than the battery voltage by respectively. 50mV (180mV rising, 50mV falling). Table 1 describes the behavior of the PWR status output. Thermal Limiting An internal thermal feedback loop reduces the programmed Table 1. Power Source Selection charge current if the die temperature attempts to rise VUSBIN > 3.95V and VUSBIN < 3.95V or above a preset value of approximately 105°C. This feature V > BAT + 50mV VUSBIN < BAT + 50mV USBIN protects the LTC3550 from excessive temperature and VDCIN > 4.15V and Charger Powered from Charger Powered VDCIN > BAT + 50mV Wall Adapter Source; from Wall Adapter allows the user to push the limits of the power handling USBIN Current < 25µA Source ⎯⎯⎯ ⎯⎯⎯ capability of a given circuit board without risk of damag- PWR: LOW PWR: LOW ing the device. The charge current can be set according VDCIN < 4.15V or Charger Powered from No Charging to typical (not worst-case) ambient temperature with the VDCIN < BAT + 50mV USB Source; P⎯W⎯R:⎯ LOW P⎯W⎯R:⎯ Hi-Z assurance that the charger will automatically reduce the current in worst case conditions. DFN package power considerations are discussed further in the Applications Status Indicators Information section. The charge status output (C⎯H⎯R⎯G)⎯ has two states: pull- down and high impedance. The pull-down state indicates Charge Current Soft-Start and Soft-Stop that the LTC3550 is in a charge cycle. Once the charge The battery charger includes a soft-start circuit to minimize cycle has terminated or the LTC3550 is disabled, the pin the inrush current at the start of a charge cycle. When a state becomes high impedance. The pull-down state is charge cycle is initiated, the charge current ramps from strong enough to drive an LED and is capable of sinking zero to full-scale current over a period of 250µs. Likewise, up to 10mA. internal circuitry ramps the charge current from full-scale The power supply status output (P⎯W⎯R)⎯ has two states: pull- to zero in approximately 30µs when the charger shuts down down and high impedance. The pull-down state indicates or self terminates. This minimizes the transient current load that power is present at either DCIN or USBIN. If no power on the power supply during start-up and shutdown. is applied at either pin, the P⎯W⎯R⎯ pin is high impedance, indicating that the LTC3550 lacks suffi cient power to charge the battery. The pull-down state is strong enough to drive an LED and is capable of sinking up to 10mA.

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APPLICATIO S I FOR ATIOWU Figure 2 shows the basic LTC3550 application circuit. Charge current out of the BAT pin can be determined at External component selection is driven by the charging any time by monitoring the IDC or IUSB pin voltage and requirements and the buck regulator load requirements. using the following equations:

VIDC L1 VOUT I = •,(arg1000 ch ing from wall adapter)) SW 1.2V BAT 600mA RIDC LTC3550 CF R2 COUT WALL V DCIN V = IUSB ADAPTER FB IBAT •,(arg1000 ch ing from USB sup pll y , RUN R1 RIUSB = USB HPWR HIGH) USBIN V PORT CC C2 IUSB BAT VIUSB RIUSB I = •,(arg200ch in ggfromUSBsup ply , C BAT IDC ITERM IN 4.2V RIUSB = C1 GND + SINGLE HPWR LOW) R R IDC ITERM CELL Li-Ion BATTERY

3550 F02 Programming Charge Termination

Figure 2. LTC3550 Basic Circuit The charge cycle terminates when the charge current falls below the programmed termination threshold during con- Programming and Monitoring Charge Current stant-voltage mode. This threshold is set by connecting an external resistor, R , from the ITERM pin to ground. The charge current delivered to the battery from the wall ITERM The charge termination current threshold (ITERMINATE) is adapter supply is programmed using a single resistor from set by the following equation: the IDC pin to ground. 100V 100V 1000V 1000V R ==,I R ==, I ITERM I TERMINATE R IDC I CHRG() DC R TERMINATE ITERM CHRG() DC IDC The termination condition is detected by using an internal Similarly, the charge current from the USB supply is fi ltered comparator to monitor the ITERM pin. When the programmed using a single resistor from the IUSB pin ITERM pin voltage drops below 100mV* for longer than to ground. Setting HPWR pin to its high state will select tTERMINATE (typically 1.5ms), charging is terminated. The 100% of the programmed charge current, while setting charge current is latched off and the LTC3550 enters HPWR to its low state will select 20% of the programmed standby mode. charge current. When charging, transient loads on the BAT pin can cause 1000V the ITERM pin to fall below 100mV for short periods of R ==()HPWR HIGH IUSB I time before the DC charge current has dropped below the CHRG() USB programmed termination current. The 1.5ms fi lter time ===1000V (tTERMINATE) on the termination comparator ensures that ICHRG() USB ()HPWR HIGH RIUSB transient loads of this nature do not result in premature 200V charge cycle termination. Once the average charge current I = ()HPWR= LOW drops below the programmed termination threshold, the CHRG() USB R IUSBB LTC3550 terminates the charge cycle and stops providing any current out of the BAT pin. In this state, any load on the BAT pin must be supplied by the battery.

*Any external sources that hold the ITERM pin above 100mV will prevent the LTC3550 from terminating a charged cycle.

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Buck Regulator Inductor Selection Table 2. Representative Surface Mount Inductors PART VALUE DCR MAX DC SIZE For most applications, the value of the inductor will fall in Ω × × the range of 1µH to 4.7µH. Its value is chosen based on NUMBER (µH) ( MAX) CURRENT (A) W L H (mm) Sumida 1.5 0.043 1.55 3.8 × 3.8 × 1.8 the desired inductor current. Large value inductors CDRH3D16 2.2 0.075 1.20 lower ripple current and small value inductors result in 3.3 0.110 1.10 4.7 0.162 0.90 higher ripple currents. Higher VCC or VOUT also increases the ripple current as shown in Equation 1. A reasonable Sumida 2.2 0.116 0.950 3.5 × 4.3 × 0.8 CMD4D06 3.3 0.174 0.770 starting point for setting ripple current is ΔIL = 240mA 4.7 0.216 0.750 (40% of 600mA). Panasonic 3.3 0.17 1.00 4.5 × 5.4 × 1.2 ELT5KT 4.7 0.20 0.95 V ⎛ V ⎞ ∆ =−OUT OUT × × IL •1⎜ ⎟ (1) Murata 1.0 0.060 1.00 2.5 3.2 2.0 fLO • ⎝ VCC ⎠ LQH32CN 2.2 0.097 0.79 4.7 0.150 0.65 The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple CIN and COUT Selection current to prevent core saturation. Thus, a 720mA rated In continuous mode, the source current of the top MOSFET inductor should be enough for most applications (600mA is a square wave of duty cycle VOUT/VCC. To prevent large + 120mA). For best effi ciency, choose a low DC-resistance voltage transients, a low ESR input capacitor sized for the inductor. maximum RMS current must be used. The maximum RMS The inductor value also has an effect on Burst Mode opera- capacitor current is given by: tion. The transition to low current operation begins when VVV()− the inductor current peaks fall to approximately 200mA. ≅ OUT CC OUT Δ CIN required I RMS I OMAX Lower inductor values (higher IL) will cause this to occur VCC at lower load currents, which can cause a dip in effi ciency (2) in the upper range of low current operation. In Burst Mode This formula has a maximum at V = 2V , where I operation, lower inductance values will cause the burst CC OUT RMS = I /2. This simple worst-case condition is commonly frequency to increase. OUT used for design because even signifi cant deviations do not Inductor Core Selection offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of Different core materials and shapes will change the life. This makes it advisable to further derate the capaci- size/current and price/current relationship of an induc- tor, or choose a capacitor rated at a higher temperature tor. Toroid or shielded pot cores in ferrite or permalloy than required. Always consult the manufacturer if there materials are small and don’t radiate much energy, but is any question. generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which The selection of COUT is driven by the required effective style inductor to use often depends more on the price vs series resistance (ESR). size requirements and any radiated fi eld/EMI requirements Typically, once the ESR requirement for COUT has been than on what the LTC3550 requires to operate. Table 2 met, the RMS current rating generally far exceeds the shows some typical surface mount inductors that work IRIPPLE(P-P) requirement. The output ripple ΔVOUT is well in LTC3550 applications. determined by:

⎛ 1 ⎞ ∆≅∆+VIESROUT L ⎜ ⎟ (3) ⎝ 8fCOUT ⎠

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≤ ≤ where f = operating frequency, COUT = output capacitance 0.6V VOUT 5.5V and ΔI = ripple current in the inductor. For a fi xed output L R2 voltage, the output ripple voltage is highest at maximum VFB input voltage since ΔI increases with input voltage. L LTC3550 R1 Aluminum electrolytic and solid tantalum capacitors are GND both available in surface mount confi gurations. In the case 3550 F03 of tantalum, it is critical that the capacitors are surge tested Figure 3. Setting the LTC3550 Output Voltage for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give limiting the effi ciency and which change would produce the lowest ESR for a given volume. Other capacitor types the most improvement. Effi ciency can be expressed as: include Sanyo POSCAP, Kemet T510 and T495 series, and Effi ciency = 100% – (L1 + L2 + L3 + ...) Sprague 593D and 595D series. Consult the manufacturer where L1, L2, etc. are the individual losses as a percent- for other specifi c recommendations. age of input power. Using Ceramic Input and Output Capacitors Although all dissipative elements in the circuit produce Higher capacitance values, lower cost ceramic capacitors losses, two main sources usually account for most of are now becoming available in smaller case sizes. Their the losses in LTC3550 circuits: VCC quiescent current 2 high ripple current, high voltage rating and low ESR make and I R losses. The VCC quiescent current loss dominates them ideal for switching regulator applications. Because the effi ciency loss at very low load currents whereas the the LTC3550’s control loop does not depend on the output I2R loss dominates the effi ciency loss at medium to high capacitor’s ESR for stable operation, ceramic capacitors load currents. In a typical effi ciency plot, the effi ciency can be used freely to achieve very low output ripple and curve at very low load currents can be misleading since small circuit size. the actual power lost is of no consequence as illustrated When choosing the input and output ceramic capacitors, in Figure 4. choose the X5R or X7R dielectric formulations. These 1. The VCC quiescent current is due to two components: dielectrics have the best temperature and voltage charac- the DC bias current as given in the Electrical Charac- teristics of all the ceramics for a given value and size. teristics and the internal main switch and synchronous

Output Voltage Programming 1 The output voltage is set by a resistive divider according to the following formula: 0.1

⎛ ⎞ 0.01 =+R2 VVOUT 06. ⎜ 1 ⎟ (4) ⎝ R1⎠ 0.001

The external resistive divider is connected to the output, POWER LOSS (W) allowing remote voltage sensing as shown in Figure 3. 0.0001

Effi ciency Considerations 0.00001 0.1 1 10 100 1000 The effi ciency of a switching regulator is equal to the output LOAD CURRENT (mA) 3550 F04 power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is Figure 4. Power Lost vs Load Current

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APPLICATIO S I FOR ATIOWU switch gate charge currents. The gate charge current In most applications the buck regulator does not dissi- results from switching the gate capacitance of the pate much heat due to its high effi ciency. The majority of internal power MOSFET switches. Each time the gate the LTC3550 power dissipation occurs when charging a is switched from high to low to high again, a packet of battery. Fortunately, the LTC3550 automatically reduces charge, dQ, moves from VCC to ground. The resulting the charge current during high power conditions using dQ/dt is the current out of VCC that is typically larger a patented thermal regulation circuit. Thus, there is no than the DC bias current. In continuous mode, IGATECHG need to design for worst-case power dissipation scenarios = f(QT + QB) where QT and QB are the gate charges of because the LTC3550 ensures that the battery charger the internal top and bottom switches. Both the DC bias power dissipation never raises the junction temperature and gate charge losses are proportional to VCC and above a preset value of 105°C. In the unlikely case that thus their effects will be more pronounced at higher the junction temperature is forced above 105°C (due to supply voltages. abnormally high ambient temperatures or excessive buck 2. I2R losses are calculated from the resistances of the regulator power dissipation), the battery charge current will be reduced to zero and thus dissipate no heat. As an added internal switches, RSW, and external inductor RL. In continuous mode, the average output current fl owing measure of protection, even if the junction temperature through inductor L is “chopped” between the main reaches approximately 150°C, the buck regulator’s power switch and the synchronous switch. Thus, the series switches will be turned off and the SW node will become resistance looking into the SW pin is a function of both high impedance. top and bottom MOSFET RDS(ON) and the duty cycle The conditions that cause the LTC3550 to reduce charge (DC) as follows: current through thermal feedback can be approximated by RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) considering the power dissipated in the IC. The approxi- mate ambient temperature at which the thermal feedback The R for both the top and bottom MOSFETs can DS(ON) begins to protect the IC is: be obtained from the Typical Performance Characteristics 2 curves. Thus, to obtain I R losses, simply add RSW to RL TA = 105°C – TRISE and multiply the result by the square of the average output T = 105°C – (P • θ ) current. Other losses including C and C ESR dissipa- A D JA IN OUT θ tive losses and inductor core losses generally account for TA = 105°C – (PD(CHARGER) + PD(BUCK)) • JA (5) less than 2% total additional loss. Most of the charger’s power dissipation is generated from the internal charger MOSFET. Thus, the power dissipation Thermal Considerations is calculated to be: The battery charger’s thermal regulation feature and the P = (V – V ) • I (6) buck regulator’s high effi ciency make it unlikely that enough D(CHARGER) IN BAT BAT power will be dissipated to exceed the LTC3550 maximum VIN is the charger supply voltage (either DCIN or USBIN), junction temperature. Nevertheless, it is a good idea to VBAT is the battery voltage and IBAT is the charge cur- do some thermal analysis for worst-case conditions. rent. The junction temperature, TJ, is given by: TJ = TA + TRISE Example: An LTC3550 operating from a 5V wall adapter where TA is the ambient temperature. The temperature (on the DCIN input) is programmed to supply 650mA rise is given by: full-scale current to a discharged Li-Ion battery with a TRISE = PD • θJA voltage of 3V. where PD is the power dissipated and θJA is the thermal The charger power dissipation is calculated to be: resistance from the junction of the die to the ambient PD(CHARGER) = (5V – 3V) • 650mA = 1.3W temperature.

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APPLICATIO S I FOR ATIOWU For simplicity, assume the buck regulator is disabled and an example, a correctly soldered LTC3550 can deliver over dissipates no power (PD(BUCK) = 0). For a properly soldered 800mA to a battery from a 5V supply at room temperature. DHC16 package, the thermal resistance (θJA) is 40°C/W. Without a good backside thermal connection, this number Thus, the ambient temperature at which the LTC3550 would drop to much less than 500mA. charger will begin to reduce the charge current is: Battery Charger Stability Considerations TA = 105°C – (1.3W • 40°C/W) The constant-voltage mode feedback loop is stable without T = 105°C – 52°C A any compensation provided a battery is connected to the TA = 53°C charger output. When the charger is in constant-current The LTC3550 can be used above 53°C ambient, but the mode, the charge current program pin (IDC or IUSB) is in charge current will be reduced from 650mA. Assum- the feedback loop, not the battery. The constant-current ing no power dissipation from the buck converter, the mode stability is affected by the impedance at the charge approximate current at a given ambient temperature can current program pin. With no additional capacitance on be approximated by: this pin, the charger is stable with program resistor val- ues as high as 20k (ICHG = 50mA); however, additional 105°CT – I = A capacitance on these nodes reduces the maximum allowed BAT θ (7) (–VVIN BAT )• JA program resistor value. Using the previous example with an ambient temperature Checking Regulator Transient Response of 60°C, the charge current will be reduced to approxi- The regulator loop response can be checked by looking mately: at the load transient response. Switching regulators take 105°°CC– 60 45°C several cycles to respond to a step in load current. When IBAT = = (–)•/5340VV° CW80°CA / a load step occurs, VOUT immediately shifts by an amount Δ = equal to ( ILOAD • ESR), where ESR is the effective series IBATT 563mA resistance of COUT. ΔILOAD also begins to charge or dis- Because the regulator typically dissipates signifi cantly less charge COUT, which generates a feedback error signal. The power than the charger (even in worst-case situations), regulator loop then acts to return VOUT to its steady state the calculations here should work well as an approxima- value. During this recovery time VOUT can be monitored tion. However, the user may wish to repeat the previous for overshoot or ringing that would indicate a stability analysis to take the buck regulator’s power dissipation into problem. For a detailed explanation of switching control account. Equation (7) can be modifi ed to take into account loop theory, see Application Note 76. the temperature rise due to the buck regulator: A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The 105°−CT –A ( P D() BUCK •θ JA ) IBAT = (8) discharged bypass capacitors are effectively put in paral- (–VVIN BAT )•θ JA lel with COUT, causing a rapid drop in VOUT. No regulator For optimum performance, it is critical that the exposed can deliver enough current to prevent this problem if the metal pad on the backside of the LTC3550 package is load switch resistance is low and it is driven quickly. The properly soldered to the PC board ground. When correctly only solution is to limit the rise time of the switch drive soldered to a 2500mm2 double sided 1oz copper board, the so that the load rise time is limited to approximately (25 LTC3550 has a thermal resistance of approximately 40°C/W. • CLOAD). Thus, a 10µF capacitor charging to 3.3V would Failure to make thermal contact between the exposed pad require a 250µs rise time, limiting the charging current on the backside of the package and the copper board will to about 130mA. result in thermal resistances far greater than 40°C/W. As

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APPLICATIO S I FOR ATIOWU Protecting the USB Pin and Wall Adapter Input from 4.7µF ceramic capacitor to locally bypass the 5V input. Overvoltage Transients This trace shows the clean response resulting from the Ω Caution must be exercised when using ceramic capacitors addition of the 1 resistor. to bypass the USBIN pin or the wall adapter inputs. High Even with the additional 1Ω resistor, bad design techniques voltage transients can be generated when the USB or wall and poor board layout can often make the overvoltage adapter is hot-plugged. When power is supplied via the problem even worse. System designers often add extra USB bus or wall adapter, the cable inductance along with inductance in series with input lines in an attempt to mini- the self resonant and high Q characteristics of ceramic mize the noise fed back to those inputs by the application. capacitors can cause substantial ringing which could In reality, adding these extra inductances only makes the exceed the maximum voltage ratings and damage the overvoltage transients worse. Since cable inductance is LTC3550. Refer to Linear Technology Application Note 88, one of the fundamental causes of the excessive ringing, entitled “Ceramic Input Capacitors Can Cause Overvoltage adding a series ferrite bead or inductor increases the ef- Transients” for a detailed discussion of this problem. The fective cable inductance, making the problem even worse. long cable lengths of most wall adapters and USB cables For this reason, do not add additional inductance (ferrite makes them especially susceptible to this problem. To beads or inductors) in series with the USB or wall adapter bypass the USB and the wall adapter inputs, add a 1Ω inputs. For the most robust solution, 6V transorbs or zener resistor in series with a ceramic capacitor to lower the diodes may also be added to further protect the USB and effective Q of the network and greatly reduce the ringing. wall adapter inputs. Two possible protection devices are A tantalum, OS-CON, or can be used the SM2T from STMicroelectronics and the EDZ series in place of the ceramic and resistor, as their higher ESR devices from ROHM. reduces the Q, thus reducing the voltage ringing. Always use an oscilloscope to check the voltage wave- The oscilloscope photograph in Figure 5 shows how seri- forms at the USBIN and DCIN pins during USB and wall ous the overvoltage transient can be for the USB and wall adapter hot-plug events to ensure that overvoltage adapter inputs. For both traces, a 5V supply is hot-plugged transients have been adequately removed. using a three foot long cable. For the top trace, only a 4.7µF ceramic X5R capacitor (without the recommended PC Board Layout Checklist Ω 1 series resistor) is used to locally bypass the input. When laying out the printed circuit board, the following This trace shows excessive ringing when the 5V cable checklist should be used to ensure proper operation of is inserted, with the overvoltage spike reaching 10V. For the LTC3550. These items are also illustrated graphically Ω the bottom trace, a 1 resistor is added in series with the in Figures 6 and 7. Check the following in your layout:

BOLD LINES INDICATE LTC3550 6 HIGH CURRENT PATHS VFB 4.7μF ONLY 7 10 2V/DIV V CC + VCC SW CIN – 8 GND GND 9 L1 – R1 17 COUT VOUT 4.7μF + 1Ω + 2V/DIV R2 3550 F06

3550 F04 20μs/DIV CF Figure 5. Waveforms Resulting from Hot-Plugging a 5V Input Supply When Using Ceramic Bypass Capacitors Figure 6. DC-DC Converter Layout Diagram 3550fa 20

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CF VIA TO VOUT R2

VIA TO VIA TO VCC R1 GND VFB RUN

SW

CIN L1

VCC GND

COUT VOUT

3550 F07 Figure 7. DC-DC Converter Suggested Layout

1. The power traces, consisting of the GND trace, the SW Design Example trace and the V trace should be kept short, direct CC As a design example, assume the LTC3550 is used in and wide. a single lithium-ion battery-powered cellular phone 2. Does the VFB pin connect directly to the feedback resis- application. The battery is charged by either plugging tors? The resistive divider R1/R2 must be connected a wall adapter cable into the phone or putting the phone in between the (+) plate of COUT and ground. a USB cradle. The optimum charge current for this parti- cular lithium-ion battery is determined to be 800mA. The 3. Does the (+) plate of CIN connect to VCC as closely as possible? This capacitor provides the AC current to the buck regulator output voltage needs to be 1.8V. internal power MOSFETs. Starting with the charger, choosing RIDC to be 1.24k programs the charger for 806mA. Choosing R to 4. Keep the switching node, SW, away from the sensitive IUSB be 2.1k programs the charger for 475mA when charging V node. FB from the USB cradle, ensuring that the charger never 5. Keep the (–) plates of CIN and COUT as close as exceeds the 500mA maximum current supplied by the possible. USB port. A good rule of thumb for ITERMINATE is one- 6. Solder the exposed pad on the backside of the package tenth the full charge current, so RITERM is picked to be to PC board ground for optimum thermal performance. 1.24k (ITERMINATE = 80mA). The thermal resistance of the package can be further Moving on to the step-down converter, VCC will be pow- enhanced by increasing the area of the copper used for ered from the battery which can range from a maximum PC board ground. of 4.2V down to about 2.7V. The load current requirement

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LTC3550

U U

APPLICATIO S I FOR ATIOWU is a maximum of 600mA but most of the time it will be in A 2.2µH inductor works well for this application. For best standby mode, requiring only 2mA. Effi ciency at both low effi ciency choose a 720mA or greater inductor with less and high load currents is important. With this information than 0.2Ω series resistance. CIN will require an RMS cur- we can calculate L using Equation (1), rent rating of at least 0.3A = ILOAD(MAX)/2 at temperature Ω ⎛ ⎞ and COUT will require an ESR of less than 0.25 . In most VOUT VOUT ∆=IL •1⎜ − ⎟ cases, a ceramic capacitor will satisfy this requirement. fL• ⎝ V ⎠ O CC For the feedback resistors, choose R1 = 301k. R2 can then Substituting VOUT = 1.8V, VCC = 4.2V, ΔIL = 240mA and be calculated from equation (4) to be: fO = 1.5MHz in Equation (3) gives: ⎛ V ⎞ RR21= OUT –1= 604k 18. V ⎛ 18. V ⎞ ⎝⎜ ⎠⎟ L =−• ⎜1 ⎟ =µ286.HH 06. 1.•() 5MHz 240 mA ⎝ 42. V⎠ Figure 8 shows the complete circuit along with its ef- fi ciency curve.

95 µ VOUT = 1.8V 2.2 H* VOUT SW 1.8V 90 VCC = 2.7V 10µF** 600mA LTC3550 CER 22pF 604k 85 WALL DCIN VFB VCC = 4.2V ADAPTER 80 EN RUN 301k VCC = 3.6V USB 800mA (WALL) USBIN VCC 75 PORT 475mA (USB) 1µF

IUSB BAT EFFICIENCY (%) 2.1k 4.7µF† 70 1% IDC ITERM 4.2V 1µF GND 1.24k + 1.24k SINGLE-CELL 65 1% 1% Li-Ion BATTERY 60 * MURATA LQH32CN2R2M33 3550 F08a 0.11 10 100 1000 ** TAIYO YUDEN JMK316BJ106ML OUTPUT CURRENT (mA) † TAIYO YUDEN LMK212BJ475MG 3550 G24 Figure 8a. Design Example Circuit Figure 8b. Buck Regulator Effi ciency vs Output Current

TYPICAL APPLICATIOU S Full Featured Dual Input Charger Plus Step-Down Converter

800mA (WALL) 475mA (USB) WALL DCIN BAT ADAPTER LTC3550 4.7mF 1k 4.2V USB USBIN PWR + POWER 1k SINGLE-CELL m m 1 F 1 F CHRG Li-Ion BATTERY EN RUN

IUSB VCC VOUT IDC SW 1.8V m 2.2 H m 600mA ITERM V 10 F FB CER 2.1k 1.24k 1k GND 1% 1% 1% 22mF 604k

301k

3550 TA03 3550fa 22 LTC3550

PACKAGE DESCRIPTIO U DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706)

0.65 ±0.05

3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES)

PACKAGE OUTLINE

0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115 5.00 ±0.10 0.40 ± 0.10 TYP (2 SIDES) 9 16 R = 0.20 TYP

3.00 ±0.10 1.65 ± 0.10 (2 SIDES) (2 SIDES) PIN 1 PIN 1 TOP MARK NOTCH (SEE NOTE 6) (DHC16) DFN 1103 8 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 4.40 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3550fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3550

TYPICAL APPLICATIO U Dual Input Charger Plus Step-Down Converter with Wall Adapter PowerPath™

WALL EN DCIN ADAPTER LTC3550 1µF RUN USB V POWER USBIN CC 1µF 4.7µF 1k 800mA (WALL) 475mA (USB) IUSB BAT µ 2.2 H VOUT IDC SW 1.8V + µ 600mA 4.2V ITERM V 10 F FB CER SINGLE-CELL 2.1k 1.24k 1k GND Li-Ion BATTERY 1% 1% 1% 22pF 604k

301k

PowerPath is a trademark of Linear Technology Corporation 3550 TA04

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC3406/LTC3406B 1.5MHz, 600mA Synchronous VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ThinSOT Package Step-Down DC/DC Converter in ThinSOTTM LTC3455 Dual DC/DC Converter with USB Power Effi ciency >96%, Accurate USB Current Limiting (500mA/100mA), 4mm × 4mm Management and Li-Ion Battery Charger QFN-24 Package LTC3456 2-Cell Multi-Output DC/DC Converter Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power with USB Power Manager Sources, QFN Package LTC3550-1 Dual Input USB/AC Adapter Li-Ion Battery Synchronous Buck Converter, Effi ciency = 93%, Output = 1.875V at 600mA, Charge Charger with 600mA Buck Converter Current = 950mA Programmable 5mm × 3mm 16-Lead DFN Package LTC3552-1 Standalone Linear Li-Ion Battery Charger Synchronous Buck Converter, Effi ciency > 90%, Outputs = 1.8V at 800mA, 1.575V at with Dual Synchronous Buck Converter 400mA, Charge Current Programmable up to 950mA, USB Compatible, 5mm × 3mm 16-Lead DFN Package LTC4055 USB Power Controller and Battery Charger Charges Single-Cell Li-Ion Batteries Directly from USB Port, Thermal Regulation, 4mm × 4mm QFN-16 Package LTC4058 Standalone 950mA Lithium-Ion Charger C/10 Charge Termination, Battery Kelvin Sensing, ±7% Charge Accuracy in DFN LTC4063 Standalone Li-Ion Charger Plus LDO 4.2V, ±0.35% Float Voltage, Up to 1A Charge Current, 100mA LDO LTC4068 Standalone Linear Li-Ion Battery Charger Charge Current up to 950mA, Thermal Regulation, 3mm × 3mm DFN-8 Package with Programmable Termination LTC4075 Dual Input Standalone Li-Ion Battery Charges Single-Cell Li-Ion Batteries from Wall Adapter and USB Inputs with Automatic Charger Input Power Detection and Selection, 950mA Charger Current, Thermal Regulation, C/X Charge Termination, 3mm × 3mm DFN Package LTC4076 Dual Input Standalone Li-Ion Battery Charges Single-Cell Li-Ion Batteries from Wall Adapter and USB Inputs with Automatic Charger Input Power Detection and Selection, 950mA Charger Current, Thermal Regulation, USB Low Power Mode Select, C/X Charge Termination, 3mm × 3mm DFN Package LTC4077 Dual Input Standalone Li-Ion Battery Charges Single-Cell Li-Ion Batteries from Wall Adapter and USB Inputs with Charger Automatic Input Power Detection and Selection, 950mA Charger Current, Thermal Regulation, Programmable USB Low Power Mode, C/10 Charge Termination, 3mm × 3mm DFN Package ThinSOT is a trademark of Linear Technology Corporation.

3550fa Linear Technology Corporation LT 0406 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 24 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006