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Appendix A MAX+PLUS II Command-Line Mode
You can operate the MAX+PLUS II Compiler, Timing Analyzer, and Simulator from the command prompt under UNIX, Microsoft Windows NT, and Microsoft Windows 95.
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To run MAX+PLUS II from a command prompt, type:
maxplus2 -h | -v | {
Multiple batch and I/O options can be used for a single project; multiple projects can be processed with the same command line. The
The
Batch Option: Action:
-h or -help displays information about command line options -v or -version displays the MAX+PLUS II version number -c or -compile runs the Compiler -ta_delay runs the Timing Analyzer in Delay Matrix mode -ta_setup runs the Timing Analyzer in Setup/Hold Matrix mode -ta_reg runs the Timing Analyzer in Registered Performance mode -s or -simulate runs the Simulator -i or -ignore_errors ignores errors from the Compiler, Simulator, or Timing Analyzer, and continues processing other projects specified in the same command line, even if the processing on a previous project has failed
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Appendix A: MAX+PLUS II Command-Line Mode
The are shown below. For each option, the
I/O Option: Action:
-tao "
1 You can use > or >> to redirect MAX+PLUS II warning and error messages to an ASCII file. (In UNIX, use >! and >>! instead of > and >> if the noclobber variable is set.)
The following example compiles the upcntr project; compiles the chiptrip project; runs a timing analysis on chiptrip in Registered Performance mode; and simulates chiptrip using test.scf as the source of vectors:
maxplus2 -c upcntr -c -ta_reg -s -scf "test.scf" chiptrip 9
The following example compiles the chiptrip project, overwriting any existing message.out file:
maxplus2 -c chiptrip > message.out 9
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Appendix B Altera Support Services
AlteraÕs support team is dedicated to resolving your technical issues quickly. Altera responds to your questions promptly and efficiently via telephone, fax, or e-mail. Applications Engineers are located at Altera headquarters in San Jose, California, and at locations around the world.
The Altera Applications, Literature, and Marketing Departments offer the following services:
■ Product information ■ Technical support ■ Technical publications ■ Training courses
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Contacting Altera Support Services
Table B-1 describes AlteraÕs support services.
Table B-1. Altera Support Services (Part 1 of 2)
Support Service Contact Information Note (1) Description
Product Tel: (408) 544-7104 Up-to-date information on Altera Information E-mail: [email protected] products is available from the Altera WWW: http://www.altera.com Marketing Department between the BBS: 544-6421 Note (2) hours of 8:00 a.m. and 5:00 p.m. Pacific FTP site: [email protected] Time, Monday through Friday.
or contact your local Altera distributor or sales office Technical Support U.S. & Canada Only: Direct technical support on Altera devices Hotline: (800) 800-EPLD and software is available from the Altera or (408) 544-7000 Applications Department between the hours of 6:00 a.m. and 6:00 p.m. Pacific Worldwide: Time, Monday through Friday. Tel: (408) 544-7000 Fax: (408) 544-6401 Applications Engineers at Altera and Field WWW: http://www.altera.com Applications Engineers located around the BBS: 544-6421 Note (2) world can evaluate customer designs, FTP site: [email protected] recommend efficient design methods and E-mail: [email protected] devices that will best meet your needs, estimate device performance, demonstrate Contact your local Altera MAX+PLUS II software, and provide on- distributor or sales office for site training. design evaluations and on-site support The world-wide web (WWW) site provides access to the Atlas technical support database, and to product information and technical publications.
You can use the FTP site and the BBS to transfer files to and from the Altera Applications Department for technical support and review. The FTP site and the BBS also provide software utilities and technical publications. Notes: (1) AlteraÕs e-mail, world-wide web (WWW) site, bulletin board service (BBS), and File Transfer Protocol (FTP) site are available 24 hours a day. (2) The BBS requires a Bell Standard 212, CCITT standard, or compatible modem at up to 14,400 bps, using 8 data bits, 1 stop bit, and no parity.
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Appendix B: Altera Support Services
Table B-1. Altera Support Services (Part 2 of 2)
Support Service Contact Information Note (1) Description Technical Tel: (888) 3-ALTERA Altera produces a variety of technical Publications E-mail: [email protected] literature to help you select and design with WWW: http://www.altera.com programmable logic, including application BBS: 544-6421 Note (2) notes and data sheets. FTP site: [email protected] Altera also provides News & Views, a quarterly newsletter that includes the latest information on Altera products, technical articles written by Altera Applications Engineers, and a question and answer section that addresses many commonly asked questions. All registered users of Altera products receive News & Views. Training Courses Altera Training Administrator: Altera provides a variety of training Tel: 544-7000 courses to teach you innovative and efficient design techniques. With these or contact your local Altera sales courses, you can discover the time-saving office features of the MAX+PLUS II development system, explore the design features of AlteraÕs device families, or simply learn about Altera products. Notes: (1) AlteraÕs e-mail, world-wide web (WWW) site, bulletin board service (BBS), and File Transfer Protocol (FTP) site are available 24 hours a day. (2) The BBS requires a Bell Standard 212, CCITT standard, or compatible modem at up to 14,400 bps, using 8 data bits, 1 stop bit, and no parity.
f Go to ÒContacting AlteraÓ in MAX+PLUS II Help for up-to-date information on Altera contact information.
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Appendix C Additional Workstation Configuration Information
This section describes how to change additional workstation configuration items that control the appearance of MAX+PLUS II windows, serial port configuration, screen height and width, printer ports, and fonts.
■ Customizing MAX+PLUS II Colors...... 286 ■ Using the mwcolormanager Utility...... 288 ■ Environment Variables...... 288 ■ Fonts...... 292 ■ Printers...... 294
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You can customize the colors of various elements in the MAX+PLUS II window by editing the ASCII-format win.ini file, which is copied into the
The settings in this file determine the colors of basic window elements when Windows Òlook and feelÓ is selected. For more information about changing the Òlook and feelÓ of the user interface, go to ÒEnvironment VariablesÓ on page 288. In contrast, the Color Palette command (Options menu) in MAX+PLUS II determines the colors of specific objects displayed in individual MAX+PLUS II application windows.
The [colors] section of win.ini defines the color of various elements in the MAX+PLUS II window. Three values in the range of 0 to 255 define the amount of red, green, and blue (RGB) that determine the color of each element.
The following table shows the [colors] section of a sample win.ini file and a brief description of each window element.
Component = R G B Value: Description:
Background=192 192 192 Desktop background AppWorkspace=255 255 255 MAX+PLUS II workspace Window=255 255 255 MAX+PLUS II application workspace WindowText=0 0 0 Window text Menu=255 255 255 Window background MenuText=0 0 0 Menu text ActiveTitle=0 0 128 Active window title bar InactiveTitle=255 255 255 Inactive window title bar TitleText=255 255 255 Title bar text in an active window ActiveBorder=192 192 192 Active window border InactiveBorder=192 192 192 Inactive window border WindowFrame=0 0 0 Window frame ScrollBar=192 192 192 Scroll bar background ButtonFace=192 192 192 Button front surface ButtonShadow=128 128 128 Shadow (i.e., darker edges) of an unpressed button
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Component = R G B Value: Description:
ButtonText=0 0 0 Text on the face of a button GrayText=128 128 128 Text color when a menu command is unavailable Hilight=0 0 128 Background behind highlighted text HilightText=255 255 255 Highlighted text InactiveTitleText=0 0 0 Text in the title bar of an inactive window ButtonHilight=255 255 255 Lighter edges of an unpressed button
The following table shows the RGB values of the 16 standard colors normally available on a color monitor. You can edit the colors in the [colors] section of your win.ini file using these values to change the color of the various window components. The availability of other colors depends on the capabilities of your workstationÕs display system.
Color: Red: Green: Blue:
White 255 255 255 Light Gray 192 192 192 Dark Gray 128 128 128 Black 0 0 0 Red 255 0 0 Dark Red 128 0 0 Green 0 255 0 Dark Green 0 128 0 Blue 0 0 255 Dark Blue 0 0 128 Yellow 255 255 0 Dark Yellow 128 128 0 Magenta 255 0 255 Dark Magenta 128 0 128 Cyan 0 255 255 Dark Cyan 0 128 128
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1 If the appearance of colors in MAX+PLUS II is not satisfactory, and editing the win.ini file does not help the problem, you should select the Windows Òlook and feel,Ó either by setting the MWLOOK environment variable described on page 290, or with the Change Look system menu.
Using the mwcolormanager Utility
Altera provides the mwcolormanager utility to correct color flickering problems that might occur when you change to MAX+PLUS II from another application window. If another application changes the system colors after you have started MAX+PLUS II, the colors of MAX+PLUS II window elements may change when you return to MAX+PLUS II.
To correct color flickering problems when changing applications, insert the following line as the first command in your .xinitrc file:
mwcolormanager [-display
The -display
The -extra
Environment Variables
MAX+PLUS II uses environment variables to configure various options and locate its files. MAX+PLUS II initializes them when it is installed, but you may wish to change them to optimize your system performance.
If you are using the C shell, environment variables are located in your .cshrc file, and have the following format:
setenv
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If you are using the Bourne or Korn Shell, environment variables are located in your .profile file, and have the following format:
set
MAX2_HOME
The MAX2_HOME variable specifies the name of the MAX+PLUS II home directory. The default is /usr/maxplus2. You should use this variable only if the system displays an error message indicating that MAX+PLUS II files cannot be found when you start the program.
MAX2_PLATFORM
The MAX2_PLATFORM variable specifies the name of the platform used to run MAX+PLUS II. You should use this variable only if the following error message is displayed when you start the program: Unable to determine the type of system you are using.
The following table lists the supported MAX+PLUS II platform names and corresponding variable values:
Platform Name: Variable Value:
SPARCstation running SunOS 4.1.3+ sunos SPARCstation running Solaris 2.5+ solaris HP 9000 Series 700/800 hp IBM RISC System/6000 rs6000
MWCOM1, MWCOM2, MWCOM3 & MWCOM4
These variables control the mapping of serial ports in MAX+PLUS II, which MAX+PLUS II accesses by the names COM1 through COM4, to the corresponding UNIX serial tty ports. Table C-1 shows the default variable values.
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Table C-1. Serial Ports
Platform Name MWCOM1 MWCOM2 MWCOM3 MWCOM4
IBM RISC System/6000 /dev/tty0 /dev/tty1 /dev/tty1 /dev/tty1 SPARCstation running SunOS 4.1.3 /dev/ttya /dev/ttyb /dev/ttyc /dev/ttyd SPARCstation running Solaris 2.5 dev/term/0 dev/term/1 dev/term/2 dev/term/3 HP 9000 Series 700/800 /dev/ttyd00 /dev/ttyd01 /dev/ttyd02 /dev/ttyd03
You can change the default mapping to reassign a COM port to one of the UNIX serial ports. For example, MWCOM1=/dev/ttyc binds the ttyc serial port to COM1, replacing the default port ttya.
MWFONT_CACHE_DIR
The MWFONT_CACHE_DIR variable specifies the name of the MAX+PLUS II font cache directory. The default directory is /
MWLOOK
The MWLOOK variable controls the initial Òlook and feelÓ of the MAX+PLUS II software on the workstation. MWLOOK may take the following values:
Value: Effect:
motif OSF/Motif look and feel windows Microsoft Windows look and feel
The default value for MWLOOK is windows.
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MWRGB_DB
The MWRGB_DB variable specifies the full pathname to the file rgb.txt, which maps color names to 24-bit RGB color values in the X server. If MWRGB_DB is not used, the program looks for rgb.txt in the following directories, in order:
1. /usr/openwin/lib 2. /lib 3. /usr/X/lib 4. /usr/lib/X11
MWSCREEN_HEIGHT & MWSCREEN_WIDTH
The MWSCREEN_HEIGHT and MWSCREEN_WIDTH variables control the literal size of objects on the screen. They can be set to the actual screen height and width of your display, in millimeters. The default values are those of the X server.
MWSYSTEM_FONT
The MWSYSTEM_FONT variable specifies the default system font used by MAX+PLUS II. If this variable is not used, the default font is Helvetica. To change the system font, set this variable to an existing X font name. For more information, see ÒFontsÓ on page 292.
MWUNIX_SHARED_MEMORY
The MWUNIX_SHARED_MEMORY variable determines whether or not MAX+PLUS II may use UNIX shared memory when it shares data with another program.
If MWUNIX_SHARED_MEMORY is set to true, MAX+PLUS II can use UNIX shared memory, which may improve its speed performance. If it is set to false (the default value), MAX+PLUS II uses shared memory in the X server when it shares data with another program. This shared memory allows data exchanges between programs that run on different machines, but which are displayed on the same X server.
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MWWM
The MWWM variable determines which window manager is used on the system. MWWM may take the following values:
Value: Effect:
MWM uses Motif as the window manager OLWM uses OpenLook as the window manager TWM uses the standard X window manager
MAX+PLUS II automatically detects whether you are using Motif or OpenLook. This variable should be used only if you are using the standard X window manager, TWM.
Fonts
MAX+PLUS II installs the fonts necessary for normal operation. By default, these fonts are located in the /
Adding New Fonts
You can add new X fonts to your system by performing the following steps:
v Copy the fonts into the X11 font directory (/usr/lib/x11/fonts by default) and restart the X server.
or:
1. Copy the new fonts into the /usr/maxplus2/fonts directory.
2. Make a font directory file (font.dir) by running the mkfontdir utility (bldfamily utility on SunOS).
3. Type xset +fp /usr/maxplus2/fonts 9 to prepend the font.dir file to the front of the existing font path.
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4. Type xset fp rehash 9 to reinitialize the font cache in the X server.
5. Depending on your operating system, perform one of the following:
v For Solaris, HP-UX, and AIX with Common Desktop Environment (CDE) 1.0 (autostart enabled), go through the following steps:
a. Add the line DTSOURCEPROFILE=true to the .dtprofile file in your home directory.
b. Edit the .login file in your home directory to read as follows (the following example is for C shell users):
if(!$?DT) then
or:
v For SunOS and Solaris (without Common Desktop Environment), add the following line to the .xinitrc Þle in your home directory to add the directory to your font path each time the X server is started:
xset fp+ /usr/maxplus2/fonts
A system default version of the .xinitrc file, called Xinitrc, is available in the /usr/openwin/lib/ directory.
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Font Aliases
The [FontSubstitutes] section of the win.ini file in the
The following example shows the default font substitution list:
[FontSubstitutes] Helv=helvetica MS Sans Serif=ms sans serif Tms Rmn=times MS Serif=times Times New Roman=times Arial=helvetica
Printers
MAX+PLUS II uses its own Postscript printer driver to support Postscript printers under UNIX.
Installing a New Printer
The following examples show how to edit the various sections of the win.ini file to install a new printer.
[windows] device=Apple LaserWriter II NT,PSCRIPT,LPT1 ...
The device variable in the [windows] section defines the default printer using the following syntax:
device=
MAX+PLUS II uses the PSCRIPT keyword as the
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[ports] lpt1:=lp -c "%s" lpt2:=lp -c -dps1700 "%s" lpt3:= ...
The [ports] section lists the communication and printer ports available to MAX+PLUS II. The Windows LPTn: variables are equated to UNIX commands. In this example, LPT1 and LPT2 are equated to the print command lp. MAX+PLUS II prints its output to an intermediate Postscript file, which is then substituted for the term “%s”. The term -dps1700 in the example refers to a UNIX printer named ps1700 that should be defined in the UNIX printcap file.
[PrinterPorts] Apple LaserWriter II NT=PSCRIPT,LPT1:,15,90 Postscript Printer QMS=PSCRIPT,LPT2:,15,90
The [PrinterPorts] section lists the active and inactive output devices that can be accessed by the printer drivers, specifies the ports to which the output devices are connected, and specifies time-out values. In the example, the Apple LaserWriter II NT printer is connected to the PSCRIPT queue, and is connected to LPT1. MAX+PLUS II ignores the time-out values.
Printer Fonts
You can use the [PSFontSubstitutes] section of the win.ini file to specify aliases for actual printer fonts to match the fonts in MAX+PLUS II. The following example shows the default font substitute list:
[PSFontSubstitutes] Helv=Helvetica helvetica=Helvetica MS Sans Serif=Helvetica Tms Rmn=Times Roman MS Serif=Times Roman Times New Roman=Times Roman Arial=Helvetica courier=Courier
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Glossary
This glossary defines selected terms used in MAX+PLUS II documentation.
1 Choose Glossary (Help menu) to view the full MAX+PLUS II glossary on-line. Glossary Glossary
A AHDL see Altera Hardware Description Language. ACF see Assignment & Configuration File. Altera Design File (.adf) An ASCII-format file (with the extension .adf) for Boolean Glossary active-high node A node that is activated equation entry, used with AlteraÕs when it is assigned a value of one (1 in A+PLUS software. ADFs use a netlist
AHDL and Verilog HDL or '1' in VHDL) format and Boolean equations to describe a Glossary or VCC (e.g., ena, clk). design. The MAX+PLUS II Compiler automatically translates an ADF into a active-low node A node that is activated Compiler Netlist File (.cnf) during project when it is assigned a value of zero (0 in compilation. AHDL and Verilog HDL or '0' in VHDL) or GND (e.g., clrn, prn, oen). In AHDL An ADF is also generated when a State design files, an active-low node should be Machine File (.smf) is compiled. assigned a default value of VCC with the Defaults Statement. Altera Hardware Description Language (AHDL) A high-level, modular language ADF see Altera Design File. that is completely integrated into the MAX+PLUS II system. You can create AHDL Text Design Files (.tdf) with the
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MAX+PLUS II Text Editor or any standard Editable Ancillary Files: text editor, then compile, simulate, and Assignment & Configuration File (.acf) program your projects within Assignment & Configuration Output File MAX+PLUS II. AHDL supports Boolean (.aco) equation, state machine, conditional, and Command File (.cmd) decode logic. AHDL also allows you to EDIF Command File (.edc) create and use parameterized functions, Fit File (.fit) and includes full support for functions in FLEX Chain File (.fcf) the Library of Parameterized Modules Hexadecimal (Intel-format) File (.hex) (LPM). History File (.hst) Include File (.inc) Text Design Export files (.tdx) and Text Jam File (.jam) Design Output Files (.tdo) generated by the JTAG Chain File (.jcf) MAX+PLUS II Compiler are also written in Library Mapping File (.lmf) AHDL syntax. Log File (.log) Memory Initialization File (.mif) Altera Megafunction Partner Program Memory Initialization Output File (.mio) (AMPP) A program that offers support to Message Text File (.mtf) third-party vendors to create and Programmer Log File (.plf) distribute megafunctions for use with Report File (.rpt) MAX+PLUS II. You must enter a password Serial Vector Format File (.svf) in the Megacore/AMPP Licenses dialog Simulator Channel File (.scf) box (accessed through the Authorization Standard Delay Format (SDF) Output File Code command on the Options menu) to (.sdo) enable a particular megafunction for Symbol File (.sym) implementation in a design file. Table File (.tbl) Tabular Text File (.ttf) Additionally, some vendors may provide Text Design Export File (.tdx) the option to view and edit a megafunction Text Design Output File (.tdo) design file. Timing Analyzer Output File (.tao) Vector File (.vec) For information on current AMPP vendors, VHDL Memory Model Output File (.vmo) available megafunctions, and passwords, contact Altera Marketing. Non-Editable Ancillary Files: Compiler Netlist File (.cnf) ancillary file A file that is associated with Hierarchy Interconnect File (.hif) a MAX+PLUS II project, but is not a design JEDEC File (.jed) file in the project hierarchy tree. Most Node Database File (.ndb) ancillary files also do not contain design Programmer Object File (.pof) logic. User-editable ancillary files with the Raw Binary File (.rbf) same filename as the project appear in the Serial Bitstream File (.sbf) Hierarchy Display window. See the Simulator Initialization File (.sif) following list: Simulator Netlist File (.snf) SRAM Object File (.sof)
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Glossary
area marquee In the Graphic or Symbol Mapping File (.lmf), or Vector File (.vec), Editors, the rectangular boundary must conform to this textual data coding surrounding an area selection, which is system. created by dragging Button 1 with the Selection tool. assignment In AHDL and VHDL, assignment refers to the transfer of a value In the Hierarchy Display, the rectangular to a symbolic name or group, usually border that is visible as you drag the mouse through a Boolean equation. The value on to select an area. The marquee is visible the right side of the equation is assigned to only while you are dragging the mouse. the symbolic name or group on the left.
area selection A defined rectangular assignment (resource) see resource region that includes one or more adjacent assignment. objects. In the Graphic and Symbol Editors, this area is contained within a rectangular Assignment & Configuration File (.acf) An border called an area marquee. In the ASCII file (with the extension .acf) that Waveform Editor, Floorplan Editor, and stores information about probe, pin, Hierarchy Display, all objects within an location, chip, clique, logic option, timing, area selection are highlighted. connected pin, local routing, and device assignments, as well as configuration Glossary Area selection is the process of selecting settings for the Compiler, Simulator, and multiple contiguous objects by dragging Timing Analyzer for an entire project. Glossary Button 1 with the Selection tool. In the Waveform Editor, such ÒobjectsÓ can The ACF stores information entered with consist of adjacent nodes and groups, menu commands in all MAX+PLUS II whole waveforms, or intervals on one or applications, as well as pin, location, and more waveforms. In the Floorplan Editor, chip assignments entered in the Floorplan such ÒobjectsÓ can consist of adjacent pins, Editor window. You can also edit an ACF nodes, logic cells, or assignment bins. In the manually in a Text Editor window. Hierarchy Display, file icons can be selected. B
In the Graphic and Symbol Editors, back-annotation The process of copying symbols, arcs, circles, diagonal lines, and device and resource assignments made by text blocks must lie completely within the the Compiler, which are stored in the Fit area marquee to be selected. When an File (.fit), into the Assignment & orthogonal line crosses the marquee, only Configuration File (.acf) for a project. The the portion within the marquee is selected. back-annotation process preserves the current fit in future compilations. array see group. background process An application or ASCII American Standard Code for command that can run unattended as you Information Interchange. Text editing perform another task and which can software used for any MAX+PLUS II text generate its own set of messages in a file, e.g., Text Design File (.tdf), Library Message Processor window. The following
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MAX+PLUS II applications and commands Boolean logic Logic that obeys the are background processes: theorems of Boolean algebra (George Boole, ÒThe Laws of Thought,Ó 1854). The ■ Compiler Boolean portion of a design is the portion ■ Programmer which can be implemented in the AND-OR ■ Simulator matrix of a device. ■ Timing Analyzer ■ ACF Reader branches The extensions of the hierarchy ■ Waveform Editor Import Vector File tree that represent the different levels of the command (File menu) hierarchy. A branch consists of a design ■ MAX+PLUS II Project Archive filename, a file icon, and any ancillary file command (File menu) icons. The intersections of branches are indicated by Ò+Ó and Ò-Ó branch buttons. balloon text Pop-up text in the Floorplan Connection arrows lead from higher-level Editor that provides information on an branches to lower-level branches. item under the mouse pointer, such as a pin, I/O cell, logic cell, embedded cell, or breakpoint A user-defined set of an assignment bin. Information is conditions that will interrupt simulation displayed in the following formats: when fulfilled.
batch mode The simulation mode in In AHDL and Waveform Editor files, a which Simulator commands are executed group is synonymous with a bus. from a Command File (.cmd) rather than from on-screen options or menu In VHDL, a bus is a guarded signal that commands. may have its drivers, i.e., signal sources, turned off. In VHDL, a bus is called an binary The base 2 number system (radix). array, and is not limited to 256 symbolic Binary digits are 0 and 1. names. An example of an array type is STD_LOGIC_VECTOR. See Section 3.2.1:
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Glossary
Array Types in the IEEE Standard VHDL the bus; the last name is the least significant Language Reference Manual for more bit (LSB). information. Only one- and two- dimensional arrays of scalar elements are An arbitrary bus name, consisting of up to supported. 32 name characters, can be entered in a Waveform Design File (.wdf), Simulator In Verilog HDL, a bus is an array of nets, Channel File (.scf), or Vector File (.vec). An and is limited to 256 symbolic names. See arbitrary bus name does not indicate how section 3.3: Vectors in the IEEE Standard many members are included in the bus. Hardware Description Language Based on the Verilog Hardware Description bus pinstub The location on the boundary Language manual for more information. of a mega- or macrofunction symbol, represented by an ÒxÓ in the Symbol File bus (or group) name The name of a bus (or (.sym), that represents multiple inputs or group) of up to 256 nodes. outputs to the function. A bus (thick line) drawn in a Graphic Editor file must A single-range or dual-range name consists connect to a bus pinstub with the same of up to 32 name characters, followed by number of bits to be recognized as a one or two ranges of numbers or arithmetic connection to the function. expressions in brackets. (Dual-range Glossary names are not supported in Waveform ByteBlaster A Parallel download cable Editor files.) The start and end of the that allows PC users to program and Glossary number range are separated by two configure devices in-system. The periods. Each number in the sequence ByteBlaster provides programming represents an individual node (or bit). support for MAX 7000S and MAX 9000 devices, and configuration support for Example: bus a[4..1] consists of the FLEX 6000, FLEX 8000, and FLEX 10K nodes a4, a3, a2, and a1. devices. Multi-device JTAG chain programming and configuration are also Example: bus b[2..1][1..0] consists of available for FLEX 10K, MAX 7000S, and the nodes b2_1, b2_0, b1_1, and b1_0. MAX 9000 devices. Multi-device FLEX chain configuration is available for A sequential name, consisting of a comma- FLEX 6000, FLEX 8000, and FLEX 10K separated list of names, can be entered in devices. AHDL Text Design Files (.tdf) and Graphic Design Files (.gdf). In TDFs only, this list of The ByteBlaster is connected to a parallel names must be enclosed in parentheses. printer port on a PC via a fully populated Sequential bus names can include single- DB25-to-DB25 cable. The ByteBlasterÕs and dual-range bus names. 10-pin female plug connects to a 10-pin male header on the circuit. Example: a[3..0],dout[6..4],z3
The first name in the series of names in a single-range, dual-range, or sequential name is the most significant bit (MSB) of
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C the same row (in FLEX 10K, FLEX 8000, FLEX 6000, and MAX 9000 devices only) or chip A group of logic functions defined as the same device. a single, named unit. A chip is assigned to an actual device by either the user or the Clock A signal that triggers registers. Compiler. In a flipflop or state machine, the Clock is You can make chip assignments on logic an edge-sensitive signal. The output of the functions in design files. Items that are flipflop can change only on the Clock edge. assigned to the same chip are placed in the For example, in a D flipflop, the input same device during compilation. The term value is stored and placed on the output at device always refers to an actual the Clock edge. programmable logic device, whereas the term chip always refers to a group of logic In some cases, MAX+PLUS II lists the Latch functions. Enable input to a latch as a Clock, e.g., in a Delay Matrix timing analysis. When the Compiler processes a project, each chip name is assigned to a Clock Enable The level-sensitive signal on corresponding programming file for a an enabled flipflop, i.e., a flipflop with an particular device. ÒEÓ suffix, including DFFE, TFFE, SRFFE, and JKFFE. When the Clock Enable is low, Classic An Altera device family based on Clock transitions on the Clock input to the AlteraÕs original EPROM-based EPLD flipflop are ignored. architecture. MAX+PLUS II provides support for the following Classic devices: column A vertical line of LABs connected EP600I, EP610, EP610I, EP900I, EP910, by a column FastTrack Interconnect path in EP910I, EP1800I, and EP1810 devices. a FLEX 10K, FLEX 8000, FLEX 6000, or MAX 9000 device. Clear An input signal that resets a register. A synchronous Clear signal resets COM or RS-232 port An RS-232 serial on each rising or falling Clock edge. An communication port on a PC or UNIX asynchronous Clear signal resets workstation. The BitBlaster, which is used regardless of the Clock signal. to configure and program devices in- system, must connect to a COM port. clique A group of logic functions defined as a single, named unit. The Compiler combinatorial feedback Feedback from a attempts to keep clique members together logic cell that goes back into the deviceÕs when it fits the project. A clique logic array. It is the direct function of the assignment allows you to group all logic on inputs to a logic cell, and does not retain a speed-critical path, thus improving values from earlier inputs. performance. combinatorial output Output from a logic If possible, all clique members are assigned cell that is a direct function of the inputs, to the same LAB. If the clique members will without regard to the Clock; i.e., it does not not fit into a single LAB, they are placed in retain values resulting from earlier inputs.
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Glossary
Command File (.cmd) An ASCII text file preceding symbolic name with at least one (with the extension .cmd) that contains space. commands for batch-mode simulation. In Verilog Design Files, comments begin comment In the Graphic and Symbol with two slashes (//) and continue to the Editors, a comment is a free-floating block End-of-Line. Verilog Design Files and of text used to document the design. It is ACFs also support comments consisting of not associated with any object. A comment any string of characters enclosed between stands alone anywhere within Graphic /* and */ characters. Editor files. A comment also stands alone within the symbol border of a Symbol Compiler Netlist File (.cnf) A binary file Editor file. Comments are ignored by the (with the extension .cnf) that contains the Compiler, and can be used to document data from a design file. The CNF is created various sections of a file. by the Compiler Netlist Extractor module of the MAX+PLUS II Compiler. In the Waveform Editor, a comment is a line of text used to annotate the waveforms Configuration EPROM AlteraÕs family of in the waveform drawing area . It is not serial EPROMs, which are designed to associated with any waveform. A comment configure FLEX 6000, FLEX 8000, and is anchored to the time on the time scale FLEX 10K devices. This device family Glossary where the first character is entered. A label includes the EPC1, EPC1213, EPC1064, appears in the Name field to indicate a EPC1064V, and EPC1441 devices. Glossary comment line; when a comment is added between two existing nodes, it appears in a connection dot A dot entered at an blank space, which is inserted between the intersection of two signal lines (nodes or waveforms. Comments are ignored by the buses) in a Graphic Editor file. The Compiler. connection dot indicates that the signals are logically connected. In all MAX+PLUS II text files except VHDL Design Files (.vhd), Verilog Design construct A unit in a text design language Files (.v), and Assignment & such as AHDL, VHDL, Verilog HDL, or Configuration Files (.acf), e.g., in Report EDIF. Files (.rpt), Vector Files (.vec), and Text Design Files (.tdf), a comment is any string continuity checking A test for open circuits of characters enclosed in percent symbols between device pins and programming (%). You can insert comments wherever adapter sockets. This test verifies that a white space is allowed in text files. device is properly seated in the socket of the adapter. In VHDL Design Files and ACFs, comments begin with two dashes (--) and cutoff node A node that is excluded from continue to the End-of-Line. AHDL TDFs timing analysis. The signal associated with also support VHDL-style comments. If you a node can be cut off from a timing analysis use a VHDL-style comment in a TDF, you by tagging it with the Timing Analysis must separate the two dashes from any Cutoff command.
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D delimiter A text string, character, or keyword used to define the beginning or database A flattened representation of all the end of a statement or construct in a text design files in a MAX+PLUS II project file. hierarchy. The database is used internally by Compiler modules during compilation. For example, [ and ] are delimiters of AHDL group ranges and % is a comment decimal The base 10 number system delimiter in many MAX+PLUS II text files. (radix). Decimal digits are 0 through 9. design file A file that contains logic for a In AHDL,VHDL, and Verilog HDL no MAX+PLUS II project and is compiled by special notation is needed to indicate the Compiler. The following files are decimal digits. design files:
default Simulator Channel File (.scf) A ■ Altera Design File (.adf) Simulator Channel File (.scf) that can ■ EDIF Input File (.edf) * contain all nodes and groups that are in the ■ Graphic Design File (.gdf) * Simulator Netlist File (.snf) for a project. It ■ OrCAD Schematic File (.sch) * is created automatically with the Enter ■ State Machine File (.smf) Nodes from SNF command (Node menu) ■ Text Design File (.tdf) * in the Waveform Editor. ■ Verilog Design File (.v) ■ VHDL Design File (.vhd) * default timing tagging The Timing ■ Waveform Design File (.wdf) Analyzer provides the following default ■ Xilinx Netlist Format File (.xnf) node tagging for timing analysis: An asterisk (*) indicates the design files Analysis Mode: Default Tagging: that can exist as top-level files in hierarchical projects. Other design files Delay Matrix All input pins are must be the only design file in a project or sources; all output pins must exist at the bottom level of a are destinations. hierarchical project. Setup/Hold All input pins are Matrix sources; all data and destination node A node that is tagged Clock inputs to (designated) as the destination of a signal registers, Latch Enable for the purpose of timing analysis. A inputs to latches, and destination node is tagged with the Timing data, address, and Write Analysis Destination command (Utilities Enable inputs to menu), and can be any node that is the asynchronous RAM are input to a logic function or a pin. destinations. Registered All Q outputs of device A device refers to an Altera Performance registers are sources; all programmable logic device, including data and Clock Enable Classic, MAX 5000, MAX 7000, MAX 9000, inputs to registers are destinations.
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Glossary
FLEX 6000, FLEX 8000, and FLEX 10K Option: Device Family: device families. Enable LOCK FLEX 10K Altera also offers Configuration EPROM Output devices which are used to configure JTAG User Code FLEX 10K FLEX 6000, FLEX 8000, and FLEX 10K Low-Voltage I/O All devices. Release Clears FLEX 6000, Before Tri-States FLEX 8000, and device assignment A device assignment FLEX 10K assigns a user-specified block of logic Security Bit Classic, MAX 5000, functions, called a chip, to a specific Altera MAX 7000, and device. MAX 9000 device family A group of Altera Turbo Bit Classic, MAX 5000, programmable logic devices with the same MAX 7000, and Logic Cell fundamental architecture. Altera families MAX 9000 ( Turbo Bit include the Classic, MAX 5000, MAX 7000, can be MAX 9000, FLEX 6000, FLEX 8000, applied to all logic and FLEX 10K, device families. cells in a MAX 7000 or MAX 9000 device.) Glossary device option An option that controls a Use Low-Voltage FLEX 6000 and Configuration FLEX 10K
device. Altera devices offer the following Glossary device options: EPROM User Code MAX 7000S and Option: Device Family: MAX 9000 User-Supplied FLEX 6000, Auto-Restart FLEX 6000, Start-Up Clock FLEX 8000, and Configuration on FLEX 8000, and FLEX 10K Frame Error FLEX 10K Disable Start-Up FLEX 8000 dual I/O feedback A combination of pin Time-Out feedback and register or combinatorial Enable Chip-Wide FLEX 6000 and feedback on the same logic cell. Output Enable FLEX 10K Enable Chip-Wide FLEX 6000 and dynamic models Models that represent Reset FLEX 10K actual combinatorial logic in timing Enable DCLK FLEX 8000 Simulator Netlist Files (.snf). Output in User Mode Dynamic models are generated for the Enable INIT_DONE FLEX 6000 and logic in a timing SNF when the CompilerÕs Optimize Timing SNF Output FLEX 10K command (Processing menu) is turned on. Instead of Enable JTAG MAX 7000S, processing the combinatorial logic, the Support FLEX 6000, and Simulator or Timing Analyzer refers to the FLEX 8000 representative dynamic model.
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Dynamic models allow a simulation to run (.edo) created by the CompilerÕs EDIF faster; however, the Compiler requires Netlist Writer module. additional time to generate the SNF. EDIF Input File (.edf) An EDIF version 2 0 0 E or 3 0 0 netlist file generated by any standard EDIF netlist writer. EDIF Input EAB see Embedded Array Block. Files (with the extension .edf) can be compiled by the MAX+PLUS II Compiler. EC see embedded cell. MAX+PLUS II supports EDIF Input Files that contain functions from the Library of EDIF Electronic Design Interchange Parameterized Modules (LPM). Format. An industry-standard format for the transmission of design data. EDIF Output File (.edo) An EDIF version 2 0 0 or 3 0 0 netlist file (with the extension You can generate an EDIF 2 0 0 or 3 0 0 .edo) generated by the EDIF Netlist Writer netlist file from a schematic design or from module of the Compiler. This file can be a VHDL or Verilog HDL design that has exported to an industry-standard UNIX been processed with an appropriate workstation or PC environment for industry-standard synthesis tool and then simulation. import the file into MAX+PLUS II as an EDIF Input File (.edf). MAX+PLUS II EEPROM Electrically Erasable supports EDIF Input Files that contain Programmable Read-Only Memory. A functions from the Library of form of reprogrammable semiconductor Parameterized Modules (LPM). The memory in which the contents (program) MAX+PLUS II Compiler can also generate can be erased by subjecting the device to one or more EDIF Output Files (.edo) in appropriate electrical signals. either EDIF 2 0 0 or 3 0 0 format that contain functional or timing information for Embedded Array Block (EAB) A physically simulation with a standard EDIF grouped set of 8 embedded cells that simulator. implement memory (RAM or ROM) or combinatorial logic in a FLEX 10K device. The MAX+PLUS II CompilerÕs EDIF An EAB consists of an embedded cell array, Netlist Reader and EDIF Netlist Writer with data, address, and control signal modules have been awarded the Electronic inputs and data outputs that are optionally Industries AssociationÕs (EIA) EDIF registered. version 3 0 0 Self-Verification Seal of Approval. This award indicates that A single EAB can implement a memory MAX+PLUS II EDIF 3 0 0 support has block of 256 × 8, 512 × 4, 1,024 × 2, or successfully completed the testing process 2,048 × 1 bits. Each embedded cell within to ensure compliance with the EDIF 3 0 0 the EAB implements up to 256 bits of Netlist View standard. memory. For memory blocks of these sizes, an EAB has 8, 4, 2, or 1 outputs, EDIF Command File (.edc) An ASCII text respectively. Multiple EABs can be file (with the extension .edc) used to combined to create larger memory blocks. customize the format of EDIF Output Files
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The EAB is fed by row interconnect paths functions. The following example shows and a dedicated input bus. the definition of the evaluated function MAX: embedded cell (EC) A memory element that exists in the embedded array of a DEFINE MAX(a,b) = (a > b) ? a : b; FLEX 10K device, and which can implement memory (RAM or ROM) or expander product term A single product combinatorial logic. An Embedded Array term with an inverted output that feeds Block (EAB) consists of a group of 8 back into the Logic Array Block (LAB) of a embedded cells that can implement a MAX 5000, MAX 7000, or MAX 9000 memory block of 256 × 8, 512 × 4, 1,024 × 2, device. or 2,048 × 1 bits. Each embedded cell within an EAB implements up to 256 bits of An uncommitted expander product term memory. Depending on the depth of the that can be shared with other logic cells in memory, up to 8 of the embedded cells in the same LAB is called a shareable an EAB have outputs. For memory blocks expander; a product term that has been of 256 × 8, 512 × 4, 1,024 × 2, or 2,048 × 1 bits, shared in this manner is called a shared an EAB has 8, 4, 2, or 1 outputs, expander. respectively. In MAX 7000 and MAX 9000 devices only, Glossary Embedded cells have ÒnumbersÓ of the an expander product term that is format EC
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MAX+PLUS II Getting Started
fan-in and fan-out Fan-in refers to input filenames, MAX+PLUS II maps longer signals that feed the input equations of a filenames on all Windows operating logic cell. systems to 8-character filenames by default. These filename mappings are Fan-out refers to output signals that are fed stored in the maxplus2.idx file in each by the output equations of a logic cell. directory that contains long filenames. However, you can override this behavior FastTrack Interconnect Dedicated and us the built-in support for long connection paths that span the entire width filenames available in Windows NT and and height of a FLEX 6000, FLEX 8000, Windows 95 by setting the MAX 9000, or FLEX 10K device. These USE_WINNT_LONG_FILENAMES variable connection paths allow signals to travel in the [system] section of your between all Logic Array Blocks (LABs) in a maxplus2.ini file to ON. device. In the Hierarchy Display window, a FCF see FLEX Chain File. filename, along with the file icon and filename extension, represents a file in the file icon An icon that appears in a current hierarchy tree. MAX+PLUS II application window and represents a file in the current hierarchy filename extension The one, two, or three- tree. Double-clicking Button 1 on an icon letter extension of a filename that follows a opens the file that it represents. period (.).
In the Hierarchy Display, the file icon In the Hierarchy Display window, a shows which MAX+PLUS II editor can filename extension, along with the open the file. The filename extension is filename and the file icon, represents a file displayed at the bottom of the file icon to in the current hierarchy or the current show the file type; the filename is project. displayed to the left of the file icon. Fit File (.fit) An ASCII file (with the In the Compiler, the file icons show input extension .fit) generated by the Compiler and output files for the current project. that documents pin, logic cell, I/O cell, embedded cell, chip, and device filename The name of a design file, assignments made during the last ancillary file, or other file, without the compilation. Assignments are recorded in extension. Assignment & Configuration File (.acf) syntax. A single filename can contain up to 32 name characters, plus a 3-character The Fit File can be used for back-annotation filename extension. A full pathname plus and for functional testing in the Simulator filename and extension can contain up to and Programmer. To preserve assignments 128 characters. permanently, Fit File assignments can be back-annotated into a projectÕs ACF with Because Windows 3.1 and Windows for the Back-Annotate Project command Workgroups 3.11 support only 8-character (Assign menu).
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Glossary
You can also display a read-only version of EPF10K50, EPF10K40, EPF10K30, Fit File information from the most recent EPF10K20, and EPF10K10 devices. project compilation in the Floorplan Editor. FLEX 10K devices, which include FLEX Chain File (.fcf) An ASCII file (with EPF10K50V, EPF10K130V, and the extension .fcf) that stores programming EPF10K250A devices, are enhanced file names for use in configuring multiple versions of FLEX 10K devices, and are FLEX 6000, FLEX 8000, or FLEX 10K function-, pin-, and programming-file- devices in a Passive Serial configuration compatible with FLEX 10K devices. scheme. An FCF saves the information FLEX 10KA devices differ from FLEX 10K entered with the ProgrammerÕs Multi- devices in that they are 3.3-V versions of Device FLEX Chain Setup command FLEX 10K devices. (FLEX menu). The EPF10K100GC503-3DX device FLEX 6000 An Altera device family based includes built-in ClockLock and on Flexible Logic Element MatriX ClockBoost phase-locked loop circuitry. architecture. This SRAM-based family offers high-performance, register- flipflop or register An edge-triggered, intensive, high-gate-count devices. The clocked storage unit that stores a single bit FLEX 6000 device family includes the of data. A low-to-high transition on the Glossary EPF6016 device. Clock signal changes the output of the flipflop, based on the value of the data Glossary FLEX 8000 An Altera device family based input(s). This value is maintained until the on Flexible Logic Element MatriX next low-to-high transition of the Clock, or architecture. This SRAM-based family until the flipflop is preset or cleared. offers high-performance, register- intensive, high-gate-count devices. The Depending on the architecture of the FLEX 8000 device family includes the device family, a register can be EPF8282V, EPF8282A, EPF8282AV, programmed as a level-sensitive flow- EPF8452A, EPF8636A, EPF8820A, through latch or as an edge-triggered D,T, EPF81188A, and EPF81500A devices. JK, or SR flipflop.
1 Altera recommends using In Verilog HDL, ÒregisterÓ is also used to FLEX 8000A devices rather than describe the abstraction of a data storage FLEX 8000 devices for all new device that the MAX+PLUS II Compiler designs. uses to infer registers.
FLEX 10K An Altera device family based fMAX (maximum Clock frequency) The on Flexible Logic Element MatriX maximum Clock frequency that can be architecture. This SRAM-based family achieved without violating internal setup offers high-performance, register- and hold time requirements. intensive, high-gate-count devices with embedded arrays. The FLEX 10K device fMAX is also a timing assignment that family includes the EPF10K100, EPF10K70, specifies the minimum acceptable Clock frequency. In MAX+PLUS II, you can
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specify a required fMAX for an entire G project and/or for any input pin (INPUT or INPUTC), bidirectional pin (BIDIR or GDF see Graphic Design File. BIDIRC input function), or a register. glitch or spike A signal value pulse that Function Prototype Specifies the ports occurs when a logic level changes two or (pinstubs) of a primitive, megafunction, or more times over a short period. macrofunction in AHDL. A Function Prototype consists of the name of the When the Simulator is in timing or linked function, and a list of its inputs and simulation mode, you can define the length outputs. For mega- and macrofunctions, of a glitch and monitor the project for the Function Prototype can also contain pulses shorter than the defined value. parameters that are used to specify the Glitch detection is not available in characteristics of the function. Function functional simulation mode. Prototypes are specified in the Function Prototype Statement. They are often stored global signal A pin- or logic-driven signal in Include Files (.inc). Include Files that that passes through the global routing on a contain Function Prototypes for Altera- device before performing its specified provided mega- and macrofunctions are function. Clock, Preset, Clear, and Output located in the \maxplus2\max2lib\ Enable signals can be global signals. mega_lpm and \maxplus2\max2inc directories created during installation, 1 Logic-driven global signals are respectively. (On a UNIX workstation, the available only in FLEX 6000 devices. maxplus2 directory is a subdirectory of the /usr directory.) A global signal can be set in various ways:
To implement an instance of a mega- or ■ During design entry with a GLOBAL macrofunction in AHDL, its logic must be primitive. You can use a dedicated defined in a design file and its Function input pin to drive a global signal Prototype must be declared. (Function directly by feeding its output directly Prototypes are optional for primitives.) to a GLOBAL primitive. You can also You can then create an instance of the use the output of a logic function as a function with an Instance Declaration or an global signal by feeding its output in-line reference. directly to a GLOBAL primitive. A logic- driven global signal consumes a 1 When you use a Module dedicated global input pin. Instantiation in Verilog HDL, the MAX+PLUS II Compiler uses the ■ With the Automatic Global option in the port name and ordering information Global Project Logic Synthesis dialog in AHDL Include Files that contain box (Assign menu). The Compiler Function Prototypes to implement chooses the pin-driven signal that an instance of the logic function. feeds the most flipflops as a global Clock, Preset, or Clear, and the signal that feeds the most TRI buffers is chosen as the global Output Enable.
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■ With the Global Signal logic option in specified with a single-range group name, the Individual Logic Options dialog dual-range group name, or sequential box, which you can open from the group name format. Logic Options dialog box (Assign menu). When this option is turned on In VHDL, a group is called an array, and is for an input pin or for a single-output not limited to 256 symbolic names. logic function, it is equivalent to using Examples of array types are a GLOBAL primitive. Turning this logic STD_LOGIC_VECTOR and BIT_VECTOR. option off prevents an input pin from See Section 3.2.1: Array Types in the IEEE being used as a global signal. Standard VHDL Language Reference Manual for more information. Only one- GND A low-level input voltage. and two- dimensional arrays of scalar elements are supported. GND is the default inactive node value. In an AHDL Text Design File (.tdf), GND is In Verilog HDL, a group is called an array, used as a predefined constant and and is limited to 256 symbolic names. keyword. In a VHDL Design File (.vhd), Examples of array types are memories GND is represented by '0'. In a Verilog (which are arrays of register elements or Design File (.v), GND is represented by 0 . In words) and arrays of gate instances and a Graphic Editor file, GND is a primitive registers. The elements, instances, or Glossary symbol. GND is represented as a low (0) registers in the array are specified with a logic level in the Simulator and Waveform range. See Section 3.3: Vectors, Section 3.8: Glossary Editor. Memories, and Section 7: Gate and Switch Level Modeling in the IEEE Standard Graphic Design File (.gdf) A schematic Hardware Description Language Based on design file (with the extension .gdf) created the Verilog Hardware Description with the MAX+PLUS II Graphic Editor. Language manual for more information.
An OrCAD Schematic File (.sch) is In the Waveform Editor and Simulator, a automatically translated into a GDF and group is a collection of up to 256 nodes that treated as a GDF in the MAX+PLUS II are treated as a unit. In these applications, Graphic Editor and Compiler. a group name can be specified with an arbitrary group name or single-range Gray code A counting scheme in which group name format. only one bit at a time changes value between consecutive count values. In group name see bus name. contrast, a binary count sequence does not preclude more than one bit changing at H consecutive count values. When only one bit changes, noise susceptibility is reduced hard logic function A logic function in a in the circuit. design file that is not removed during standard logic synthesis and therefore can group or array In AHDL, a group is a be assigned to a physical resource such as a collection of up to 256 symbolic names that specific device, pin, logic cell, or I/O cell. are treated as a unit. A group name can be
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In Graphic Design Files (.gdf) and Text Hexadecimal (Intel-Format) File (.hex) An Design Files (.tdf), hard logic primitives/ ASCII text file (with the extension .hex) in ports include INPUT, INPUTC, OUTPUT, the Intel hexadecimal format. OUTPUTC, BIDIR, BIDIRC, LCELL, MCELL, DFF, DFFE, TFF, TFFE,JKFF, The MAX+PLUS II Compiler and JKFFE, SRFF, SRFFE, and LATCH. Simulator can use Hex Files as inputs to However, INPUT and INPUTC primitives specify the initial contents of a memory that do not affect project outputs are not (e.g., a ROM). considered to be hard logic functions. When SOFT, TRI, and OPNDRN primitives The MAX+PLUS II Compiler automatically are not removed during logic synthesis, creates output Hex Files containing they are also hard logic primitives. A configuration data for the Active Parallel megafunction or macrofunction that Up (APU) configuration scheme for contains a hard logic primitive is FLEX 8000 devices, and the Passive Serial considered to be a hard logic function. (PS) configuration scheme for FLEX 6000 and FLEX 10K devices. In Waveform Design Files (.wdf), hard logic functions are input nodes and output After compilation, you can also create Hex and buried nodes with registered and Files that support other configuration combinatorial node types. schemes for FLEX 6000, FLEX 8000, and FLEX 10K devices. hexadecimal The base 16 number system (radix). Hexadecimal digits are 0 through 9 1 If your project uses memory and you and A through F. use a Hex File to specify its initial contents, you should name the file Hexadecimal numbers are indicated with with a name that is not the same as the following notation: the project name or any chip name within the project. Because the Compiler automatically generates Language Notation Hex Files as outputs for FLEX 6000, AHDL X"
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Glossary
Hierarchy Interconnect File (.hif) An ASCII MAX 9000 device. I/O cells permit short file (with the extension .hif) created by the setup time. CompilerÕs Netlist Extractor module. This file specifies the hierarchical 1 In pre-version 5.0 releases of interconnections between design files in a MAX+PLUS II, I/O cells were project. known as peripheral registers.
History File (.hst) An ASCII file (with the I/O feedback Feedback from the output extension .hst) created by the pin on an Altera device. It allows an output MAX+PLUS II Simulator. This time period pin to be also used as an input pin. records all commands, buttons, and on- screen options that are used during a I/O type The direction of signal travel for a simulation session, as well as their output. node, pin, or state machine.
hold time On a flipflop, the hold time is In the Graphic and Symbol Editors, pins the minimum time period for which a and pinstubs can have I/O types of input, signal must be retained on an input pin that output, or bidirectional. feeds the data input or Clock Enable after an active transition at the input pin that In AHDL, the I/O type of a port can be feeds the flipflopÕs Clock input. input, output, buried (i.e., buried output), Glossary machine input, or machine output. On a latch, the hold time is the minimum Glossary time period for which a signal must be In the Waveform Editor, the I/O type of a retained on an input pin that feeds the D node can be input, output, or buried (i.e., input after an active transition at the input buried output). Input and output I/O pin that feeds the Latch Enable input. types can represent actual pin outputs; a buried I/O type always represents logic On an asynchronous RAM block, the hold that does not feed a pin. time is the minimum time period for which a signal must be retained on an input pin ICR see in-circuit reconfigurability. that feeds the data or address inputs after an active transition at the input pin that in-circuit reconfigurability (ICR) The feeds the RAM blockÕs Write Enable input. capability of SRAM-based devices, such as AlteraÕs FLEX 6000, FLEX 8000, and Internal hold times for flipflops, latches, FLEX 10K devices, to load configuration and asynchronous RAM, which are not data at system power-up or during normal user-controllable, similarly constrain system operation after they have been internally generated signals. mounted on a printed circuit board.
I In-circuit reconfiguration can be performed an unlimited number of times I/O cell An I/O cell is a register (also with data from a local PROM such as an known as an I/O element) that exists on the Altera Configuration EPROM, or with data periphery of a FLEX 10K, FLEX 8000, or downloaded by an external controller such as a CPU or the MAX+PLUS II
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Programmer. The Programmer also In a dialog box or in the Text Editor provides the capability to configure one or window, the insertion point appears as a more FLEX 10K devices in a JTAG chain flashing vertical bar. In the Graphic or and one or more FLEX 6000, FLEX 8000, or Symbol Editor, it appears as a flashing FLEX 10K devices in a FLEX chain. square. In the Waveform Editor, an insertion point in the waveform drawing in-system programmability (ISP) The area appears as a short horizontal line that capability of EEPROM-based devices, such extends to the right of the Time cursor. In as AlteraÕs MAX 9000 and MAX 7000S the node/group information area, a name devices, to be programmed after they have or blank space that is selected is interpreted been mounted on a printed circuit board. as an insertion point.
The MAX+PLUS II Programmer supports When you type text, it appears to the left of in-system programming via the BitBlaster the insertion point, which moves to the serial download cable and the ByteBlaster right as you type. When you enter or paste parallel download cable. The Programmer symbols or waveforms, the upper left also provides the capability to program corner of the item(s) appears at the multiple devices in a JTAG chain. insertion point.
Include File (.inc) An ASCII text file (with instance The use of a logic function in a the extension .inc) that can be imported design file. In the Graphic Editor, the into a Text Design File (.tdf) by an AHDL instance is represented by the symbol (net) Include Statement. The Include File ID number in the lower left corner; in the replaces the Include Statement that calls it. Waveform Editor, it is the name of the Include Files can contain Function node. In AHDL, instances are declared in Prototype, Define, Parameters, or Constant one of two forms: an Instance Declaration Statements. Include Files that contain that declares a variable of the type Function Prototypes for Altera-provided
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Glossary
Verilog HDL Module or Gate Instantiation, The MAX+PLUS II Programmer can use a an instance is represented by the module or JEDEC File created with MAX+PLUS II, gate name, followed by the instance name. MAX+PLUS (DOS), A+PLUS, or PLDshell Plus to program the Altera devices listed interactive mode The simulation mode in above. The Programmer can also which you choose on-screen options and optionally save programming data plus buttons, and execute menu commands, functional test vectors in JEDEC File with the keyboard or mouse. format.
ISP see in-system programmability. JTAG boundary-scan testing Testing that isolates a deviceÕs internal circuitry from its J I/O circuitry. This testing is made possible by the Joint Test Action Group (JTAG) Jam File (.jam) An ASCII file (with the Boundary-Scan Test (BST) architecture that extension .jam) in the Jam device is available in all FLEX 10K devices; all programming and test language that stores FLEX 8000 devices except the EPF8452A programming data for programming, and EPF81188A; all FLEX 6000 devices; all verifying, and blank-checking one or more MAX 9000 devices; and all MAX 7000S in-system programmable devices in a devices except the EPM7064S. Serial data is JTAG chain. Jam files are use in embedded shifted into boundary-scan cells in the Glossary processor-type programming device; observed data is shifted out and environments. AlteraÕs MAX 7000S and externally compared to expected results. Glossary MAX 9000 devices can be programmed Boundary-scan testing offers efficient PC with Jam files. The JTAG chain can contain board testing, providing an electronic any other device that complies with the substitute for the traditional Òbed of nailsÓ IEEE 1149.1 JTAG specification, including test fixture. FLEX 10K, FLEX 6000, and some FLEX 8000 devices. The full or partial JTAG BST architecture in all FLEX 10K, MAX 9000, and MAX 7000S You can generate Jam files with the Create devices also supports in-system multi- Jam or SVF File command (File menu) in device JTAG chain device programming the Programmer or the Compiler. and configuration.
JCF see JTAG Chain File. JTAG chain see multi-device JTAG chain.
JEDEC File (.jed) An ASCII file (with the JTAG Chain File (.jcf) An ASCII file (with extension .jed) that contains programming the extension .jcf) that stores device name, information. JEDEC Files provide an device order, and optional programming industry-standard format for transferring file name information for use in information between a data preparation programming or configuring one or more system and a logic device programmer. devices in a JTAG chain. A JCF saves The MAX+PLUS II Compiler automatically information entered with the Compiler or generates JEDEC Files for all Classic ProgrammerÕs Create Jam or SVF File devices and the EPM5032 device during compilation.
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command (File menu) or Multi-Device Library Mapping File (.lmf) An ASCII text JTAG Chain Setup command (JTAG file (with the extension .lmf) used to map menu). cells in EDIF Input Files (.edf) or symbols in OrCAD Schematic Files (.sch) to K corresponding MAX+PLUS II primitives, megafunctions, and macrofunctions. keyword Words that are reserved for implementing syntax in files used as inputs Library of Parameterized Modules (LPM) to MAX+PLUS II, including AHDL Text A technology-independent library of logic Design Files (.tdf), Assignment & functions that are parameterized to achieve Configuration Files (.acf), Command Files scalability and adaptability. Altera has (.cmd), EDIF Command Files (.edc), implemented parameterized modules (also Library Mapping Files (.lmf), VHDL called Òparameterized functionsÓ) from Design Files (.vhd), Verilog Design LPM version 2.1.0 that offer architecture- Files (.v) and Vector Files (.vec). For independent design entry for all example, the keyword OF cannot be used MAX+PLUS II-supported devices. The as an unquoted symbolic name in an MAX+PLUS II Compiler includes built-in AHDL file. compilation support for LPM functions used in schematic, AHDL, VHDL, Verilog L HDL, and EDIF input files.
LAB see Logic Array Block. LMF see Library Mapping File.
latch A level-sensitive clocked storage Load An input signal that loads data into unit that stores a single bit of data. A high- a register. A synchronous Load signal to-low transition on the Latch Enable signal loads data on each rising or falling Clock fixes the contents of the latch at the value of edge. An asynchronous Load signal loads the data input until the next low-to-high data regardless of the Clock signal. transition of the Latch Enable. local routing A resource assignment Latch Enable A level-sensitive signal that available for FLEX 6000 devices that controls a latch. When it is high, the input assigns a fan-out of a node to be placed in flows through the output; when it is low, logic cell in the same LAB as the node or in the output holds its last value. an adjacent LAB to the node. Local routing is also available between a node that is LC see logic cell. placed in a logic cell in an LAB on the periphery of a device and the output pin least significant bit (LSB) The bit of a that it feeds. Local routing assignments binary number that contributes the ensure that the signals are connected with smallest quantity to the value of that shared local interconnect, which is the number, i.e., the last member in a bus or fastest interconnect available. Therefore, group name. For example, the LSB for a bus you can maximize your projectÕs or group named a[31..0] is a[0] (or performance by connecting logic on a a0). speed-critical path with local routing.
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location A generic term that refers to an MAX 5000 and MAX 7000 devices, the LAB assignable physical resource in the interior is fed by a Programmable Interconnect of an Altera device. Array (PIA) and a dedicated input bus. In FLEX 6000, FLEX 8000, MAX 9000, and You can assign a logic function to one of the FLEX 10K devices, the LAB is fed by row following locations: FastTrack Interconnect paths and a dedicated input bus. ■ An individual logic cell ■ An individual I/O cell logic cell (LC) The generic term for a basic ■ An individual embedded cell building block of an Altera device. In ■ A logic array block (LAB), embedded Classic, MAX 5000, MAX 7000, and array block (EAB), row, or column MAX 9000 devices, a logic cell (also called a macrocell) consists of two parts: When you assign a logic function to a combinatorial logic and a configurable general location such as a LAB, EAB, row, register. The combinatorial logic allows a or column, the Compiler can choose the wide variety of logic functions. In best logic cell or embedded cell within the FLEX 6000, FLEX 8000, and FLEX 10K LAB, row, or column to use to implement devices, a logic cell (also called a logic the logic. element) consists of a look-up table (LUT), i.e., a function generator that quickly Glossary Log File (.log) An ASCII text file (with the computes any function of four variables, extension .log) created by the and a programmable register to support Glossary MAX+PLUS II Simulator. The Log File sequential functions. records all commands, buttons, and on- screen options that are used during an The register can be programmed as a flow- interactive simulation session. through latch; as a D, T, JK, or SR flipflop; or bypassed entirely for pure logic function or Design Entity A primitive, combinatorial logic. The register can feed megafunction, macrofunction, or state other logic cells or feed back to the logic cell machine, which may be represented as itself. Some logic cells feed output or either a name or a symbol in a design file. bidirectional I/O pins on the device.
Logic Array Block (LAB) A physically You can assign a logic function to a specific grouped set of logic resources in an Altera logic cell. You can also assign a logic device. An LAB consists of a logic cell array function to a logic array block (LAB), a row, and, in some device families, an expander or a column to ensure that the function is product term array. Any signal that is implemented in a logic cell in a particular available to any one logic cell in the LAB is LAB, row, or column. available to the entire LAB. In FLEX 10K, FLEX 8000, FLEX 6000, and In Classic devices, the logic in the LAB MAX 9000 devices, logic cells have shares a global Clock signal. The LAB is fed ÒnumbersÓ of the format by a global bus and a dedicated input bus. LC
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column number of the LAB. In Classic, A variety of logic options are available. MAX 5000, and MAX 7000 devices, logic Logic option assignments can be applied to cells have numbers of the format individual logic functions; a group of logic LC
logic cell Turbo Bit see Turbo Bit. Logic options can also be assigned as parameters for a megafunction or logic element see logic cell. macrofunction.
logic level The input and output logic 1 1. Some logic options are not levels of nodes and groups are defined available with standard with the following characters: synthesis; all logic options are available with multi-level Character: Logic Level: synthesis. 0 GND Logic low ( ) 2. A logic option is ignored if it 1 Logic high (VCC) does not apply to the current X Undefined/DonÕt Care (not device family. permitted for initialization) logic synthesis style A combination of Z High impedance (no input logic synthesis option settings that are to pin); e.g., used for the saved under a single name. ÒoutputÓ part of a bidirectional pin when the A logic synthesis style can be individually ÒinputÓ part of the pin is tailored for different device families, so driving in. that the logic synthesis option settings vary 0 9 A F to , to Used for groups and according to the architecture of the target interpreted as binary, device family. decimal, hexadecimal, or octal values according to 1 If the global project logic synthesis the current radix. The most style for your project is not fully significant bit is first; the defined, i.e., if the style specified least significant bit is last. with the Global Project Logic Synthesis command (Assign menu) logic option An option that controls the uses a ÒdefaultÓ setting for any logic logic synthesis process on one or more option, the MAX+PLUS II Compiler logic functions. will use the non-ÓdefaultÓ setting for that logic option from the predefined, Altera-provided settings
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for the Normal style. To view the created during installation. AHDL Include settings for a predefined style, open Files (.inc) for these macrofunctions are the Define Synthesis Style dialog located in the \maxplus2\max2inc box, select the style in the Style box, directory; VHDL Component Declarations and choose the Use Default button. for macrofunctions supported by VHDL are provided in the maxplus2 package in logical operator An operator that the altera library, which is located in a performs a logic operation on nodes, subdirectory of the \maxplus2\vhdlnn groups, or numbers. directory, where nn is Ò87Ó or Ò93Ó. On a UNIX workstation, the maxplus2 directory AHDL logical operators are NOT (!), AND is a subdirectory of the /usr directory. (&), NAND (!&), OR (#), NOR (!#), XOR ($), and XNOR (!$). To view the file that contains the logic for a macrofunction, select the macrofunction VHDL logical operators are AND, NAND, OR, symbol in the Graphic Editor or NOR, XOR, and NOT. macrofunction name in the Text Editor and choose Hierarchy Down (File menu). Verilog HDL logical operators are and (&&) and or (||). MAX 5000 An Altera device family based on the first generation of Multiple Array Glossary LPM see Library of Parameterized MatriX architecture. This EPROM-based Modules. device family includes the EPM5032, Glossary EPM5064, EPM5128, EPM5128A, LSB see least significant bit. EPM5130, and EPM5192 devices.
M MAX 7000, MAX 7000E, and MAX 7000S An Altera device family based on the macrocell see logic cell. second generation of Multiple Array MatriX architecture that includes macrofunction A high-level building block MAX 7000, MAX 7000E, and MAX 7000S that can be used together with gate and devices. These EEPROM-based devices flipflop primitives and/or megafunctions include EPM7032, EPM7032V, EPM7064, in MAX+PLUS II design files. EPM7064S, EPM7096, EPM7128E, EPM7128S, EPM7160E, EPM7192E, 1 In general, Altera recommends using EPM7192S, EPM7256E, and EMP7256S megafunctions in preference to devices. equivalent macrofunctions in all new projects. Megafunctions are easier to MAX 7000S and 7000E devices are scale to different sizes and offer more enhanced versions of MAX 7000 devices efficient logic synthesis and device and are function-, pin-, and programming- implementation. file-compatible with MAX 7000 devices. MAX 7000E and MAX 7000S devices differ Altera provides a library of over 300 old- from MAX 7000 devices in that they offer style macrofunctions in the \maxplus2\ up to six pin- or logic-driven Output max2lib directory and its subdirectories Enable signals, fast input setup times to
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logic cells, and multiple global Clocks with devices with JEDEC Files (.jed) and optional inversion. MAX 7000S devices Programmer Object Files (.pof) created by also offer the additional capability of in- MAX+PLUS. system programming via JTAG boundary- scan test circuitry. 1 MAX+PLUS is no longer offered by Altera. All new designs should be 1 Altera strongly recommends using created with MAX+PLUS II. MAX 7000S and MAX 7000E devices rather than equivalent MAX 7000 MAX+PLUS II Message File (.mmf) A devices for new designs. binary file (with the extension .mmf) created by MAX+PLUS II that contains MAX 9000 An Altera device family based messages issued by any MAX+PLUS II on the third generation of Multiple Array application or command that runs as a MatriX architecture. These EEPROM-based background process, e.g., the Compiler devices include the EPM9560, EPM9560A, and Programmer. This file is used to EPM9480, EPM9400, EPM9320, and display messages in the Message Processor EPM9320A devices. and to locate messages in design and ancillary files. MAX 9000A devices are enhanced versions of MAX 9000 devices, and are function-, maxplus2.idx file A text file, created pin-, and programming-file-compatible automatically when you save a file, that with MAX 9000 devices. MAX 9000A maps filenames with more than eight devices differ from MAX 9000 devices in characters to 8-character filenames. that they offer an additional 16 bits for a user code. MAX+PLUS II creates a maxplus2.idx file in each directory where you save a file that MAX 9000 devices with the speed grade contains filenames with more than eight suffix ÒFÓ contain fixed programming characters. The file is automatically algorithms, and therefore can be updated each time you save a file with a programmed with Serial Vector Format long filename. Files. maxplus2.ini file A text file, created MAX+PLUS (DOS) AlteraÕs DOS-based during installation, that contains the Multiple Array MatriX Programmable parameters that affect the way Logic User System. MAX+PLUS is a set of MAX+PLUS II applications operate. This computer programs and hardware support file continuously records the options that products for designing and implementing you set in one session, so that they are custom logic circuits with Altera Classic automatically set for the next session. and MAX 5000 devices. Graphic Design Files (.gdf) created for MAX+PLUS are MegaCore and OpenCore megafunctions automatically converted and processed MegaCore and OpenCore megafunctions with the MAX+PLUS II Compiler; AHDL are pre-verified HDL design files for Text Design Files (.tdf) are compiled complex system-level functions that can be directly. The MAX+PLUS II Programmer purchased from Altera. These pre-tested can program Classic and MAX 5000 megafunctions are optimized for
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FLEX 10K, FLEX 8000, FLEX 6000, old-style macrofunctions in MAX+PLUS II MAX 9000, and MAX 7000 device design files. architectures. Altera MegaCore megafunctions consist of several different Altera provides a library of megafunctions, design files. A post-synthesis AHDL including functions from the Library of design file is used for design Parameterized Modules (LPM) version implementation (i.e., fitting) in the target 2.1.0, in the \maxplus2\max2lib\ Altera device. In addition, VHDL or mega_lpm directory created during Verilog HDL functional simulation models installation. AHDL Include Files (.inc) for are supplied for design and debugging these megafunctions are also located in the with standard EDA simulation tools. \maxplus2\max2lib\mega_lpm directory. VHDL Component Declarations OpenCore megafunctions are MegaCore for LPM functions and other functions that you can use and evaluate megafunctions are provided in the before purchasing full support. If you lpm_components package in the lpm purchase full support, you can generate library, and the megacore package in the programming files and EDIF, VHDL, and altera library, respectively. Both of these Verilog HDL output files for post- libraries are located in subdirectories of the compilation simulation with other EDA \maxplus2\vhdlnn directory, where nn is tools. Ò87Ó or Ò93Ó. (On a UNIX workstation, the Glossary maxplus2 directory is a subdirectory of the Altera provides a library of megafunctions, /usr directory.) Glossary including OpenCore megafunctions, in the \maxplus2\max2lib\mega_lpm To view the file that contains the logic for a directory. (On a UNIX workstation, the megafunction, select the megafunction maxplus2 directory is a subdirectory of the symbol in the Graphic Editor or /usr directory). VHDL Component megafunction name in the Text Editor and Declarations for megafunctions supported choose Hierarchy Down (File menu). by VHDL are provided in the megacore package in the altera library, which is memory bit and memory word A memory located in the\maxplus2\vhdlnn bit is an individual memory address in a directory, where nn is Ò87Ó or Ò93Ó. memory (i.e., RAM or ROM) block.
If your authorization code for a MegaCore A memory word is a group of memory bits megafunction includes permission to view in a RAM or ROM block. the source design file, you can view the file by selecting the megafunction symbol in For example, the content5_[4..0] the Graphic Editor or megafunction name memory word defines a byte of memory in in the Text Editor and choosing Hierarchy which the individual memory bits are Down (File menu). content5_4, content5_3, content5_2, content5_1, and megafunction A complex or high-level content5_0. building block that can be used together with gate and flipflop primitives and/or Memory Initialization File (.mif) An ASCII file (with the extension .mif) that specifies
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the initial content of a memory block (RAM most significant bit (MSB) The bit of a or ROM), i.e., the initial values for each binary number that contributes the greatest address. This file is used during project quantity to the value of that number, and compilation and/or simulation. the first member in a bus or group name. For example, the MSB for a bus named Memory Initialization Output File (.mio) a[31..0] is a[31]. An ASCII file (with the extension .mio) that is generated when the Compiler creates a MSB see most significant bit. Text Design Export File (.tdo) for a project. A TDO File that implements RAM or ROM MTF see Message Text File. always has an MIO File for each memory segment. multi-device FLEX chain A series of devices through which configuration data is An MIO File specifies the memory passed from device to device using the addresses and values used to initialize a sequential Passive Serial configuration RAM or ROM segment, similar to the scheme. information in a Memory Initialization File (.mif). The MAX+PLUS II Programmer can configure multiple FLEX 6000, FLEX 8000, You can rename an MIO File as an MIF and or FLEX 10K devices in a multi-device use it with a TDO File that has been saved FLEX chain. as a Text Design File (.tdf). multi-device JTAG chain A series of memory segment or segment The physical devices through which programming and/ implementation of memory (i.e., RAM or or configuration data are passed from ROM) in a device. A memory segment device to device via the Joint Test Action contains a sequence of memory bits Group (JTAG) Boundary-Scan Test (BST) corresponding to an address range. circuitry.
In FLEX 10K devices, a memory segment The MAX+PLUS II Programmer can consists of that portion of a bit-slice of a program or configure multiple memory which is implemented in a single MAX 7000S, MAX 9000, and FLEX 10K embedded cell. Each embedded cell devices in a multi-device JTAG chain. The implements up to 256 bits of memory. JTAG chain can contain any combination of Multiple memory segments may be needed Altera and non-Altera devices that comply to create a single memory block. with the IEEE 1149.1 JTAG specification, including some FLEX 8000 devices. Message Text File (.mtf) An ASCII file (with the extension .mtf) that contains the MAX+PLUS II can also generate Jam Files text of messages shown in a Message (.jam) and Serial Vector Format Files (.svf) Processor window. that support programming for one or more MAX 7000S and MAX 9000 devices in a MIF see Memory Initialization File. JTAG chain. SVF files can be used in Automated Test Equipment (ATE)-type MMF see MAX+PLUS II Message File. programming environments; Jam Files in
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embedded processor-type programming Item: Name Character environments. Exception:
multi-level synthesis Logic synthesis that single-range No slash (/) is permitted; takes advantage of all available logic group (bus) the bus identifier cannot options, including all options listed in the name end with a digit. The name Define Synthesis Style and Advanced is followed by a range of Options dialog boxes (Assign menu). This numbers or arithmetic type of logic synthesis can handle projects expressions in brackets. with extremely complex logic, without The start and end of the requiring user intervention to achieve a fit. range are separated by two periods. For example, Multi-level synthesis can be selected with group a[3..1] consists of the Global Project Logic Synthesis dialog the nodes a3, a2, and a1. box (Assign menu). This type of synthesis In Graphic Editor files is available only for the MAX 5000, only, sequential bus names MAX 7000, MAX 9000, FLEX 6000, can also include a series of FLEX 8000, and FLEX 10K device families; single-range bus names. it is the only type of synthesis available for For example, FLEX 6000, FLEX 8000, and FLEX 10K a[8..0],d[6..4]. Glossary projects. dual-range Same as single-range group (bus) group names, with two Glossary N name ranges of numbers or arithmetic expressions in name characters The characters A to Z, a to brackets. For example, z, 0 to 9, slash (/), dash (-), and underscore a[6..3][4..0]. (_) are legal for MAX+PLUS II breakpoint, sequential The name consists of a chip, clique, file, group (bus), node, group (bus) series of comma-separated parameter, pin, pinstub, probe, logic name node names enclosed in synthesis style, and quoted and unquoted parentheses. For example, symbolic names, with the exceptions listed group (a, b, c) consists below. Case is significant only in Verilog of the nodes a, b, and c. In HDL files. Graphic Editor files, parentheses are not used. Item: Name Character unquoted No dash (-) is permitted. Exception: symbolic Names cannot consist filename No slash (/) is permitted. name (AHDL) entirely of digits. AHDL Case is significant on UNIX keywords cannot be used. workstations. Verilog HDL No slash (/) or dash (-) is identifiers permitted. Names cannot begin with a digit. Case is significant. Verilog HDL keywords cannot be used.
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Item: Name Character 1 1. If you turn on the CompilerÕs Exception: Preserve All Node Name Synonyms command VHDL names No slash (/) or dash (-) is (Processing menu) before permitted. The name must compilation, this file will not start with a letter, cannot contain all possible forms of the end with an underscore project node names. (_), and cannot contain two underscores (_ _) in a row. 2. If you accidentally delete this VHDL keywords cannot be file, you must recompile the used. project before you can use most ACF names Names that contain slash Assign menu commands and (/), dash (-), vertical bar Floorplan Editor functions. In (|), colon (:), and/or addition, only pins are visible in period (.) characters must the Floorplan Editor if a Node be enclosed in double Database File is created with the quotation marks ("). Project Save & Check command (File menu): a full compilation is net ID number see symbol ID number. required to make buried nodes visible in the Floorplan Editor. network A group of interconnected node and/or bus lines, including nodes or buses node or net name The name given to a that are connected by name only. signal in a design file. A node or net name can contain up to 32 of the following name node A node represents a wire carrying a characters: A to Z, a to z, 0 to 9, slash (/), signal that travels between different logical dash (-), and underscore (_). Hierarchical components of a design file. In Verilog node names can contain 128 characters, HDL, nodes are called Ònets.Ó including vertical bar (|), colon (:), and period (.). Case is not significant. In the Graphic Editor files, nodes are represented as lines; in text files, they are Some restrictions apply to names in VHDL symbolic names; in Waveform Editor files, Design Files (.vhd), Verilog Design they are waveforms. Files (.v), and unquoted port and symbolic names in AHDL Text Design Files (.tdf). Node Database File (.ndb) A file that contains the database of project node node type The type of logic that drives a names, which supports resource and probe node or group in a Waveform Design File assignment edits with Assign menu (.wdf) or Vector File (.vec). Four logic types commands and the Floorplan Editor. The are defined: Compiler Netlist Extractor and Database Builder modules of the Compiler generate Type: Meaning: a Node Database File for a project during project processing. INPUT Node or group is driven by an input pin.
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Type: Meaning: The first object is selected by clicking Button 1 on it. You can add or remove COMB Node or group is fed by objects to the selection by pressing Shift combinatorial logic, e.g., an while clicking on them with Button 1. AND gate. REG Node or group is fed by a In the Graphic Editor, object-by-object register (implemented with a selection can be used to select graphics logic cell on the device). and/or text blocks; in the Waveform MACH Node is fed by a state machine. Editor, to select nodes and groups; in the Floorplan Editor, to select pins, nodes, Normal logic synthesis style The Altera- logic cells, or assignment bins; and in the provided style that directs the Logic Hierarchy Display, to select file icons. Synthesizer to optimize your project for minimum silicon resource usage. In the Graphic Editor, multiple objects in a rectangular area can be selected and added The Normal style attempts to use device to an existing selection by pressing Shift resources as efficiently as possible, without while dragging Button 1. adding excessive timing delays. octal The base 8 number system (radix). To display the settings for this style, select Octal digits are 0 though 7. Glossary the style in the Define Synthesis Style Octal numbers are indicated with the dialog box, which is available through the Glossary Logic Options or Global Project Logic following notation: Synthesis dialog boxes (Assign menu). Language Notation 1 If the global project logic synthesis style for your project is not fully AHDL O"
object-by-object selection The process of selecting multiple non-contiguous objects.
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comprise a Òone-hotÓ code sample because oscillation An unstable logic level on a in each of these four values a single bit is set signal. When the Simulator is in timing or to 1. linked simulation mode, you can specify the time period that constitutes an You can manually implement one-hot oscillation and monitor the project for encoding. In addition, the Global Project signals that do not stabilize within the Logic Synthesis command (Assign menu) defined period. When the Simulator is in includes a One-Hot State Machine Encoding functional simulation mode, you can option to allow the Compiler to monitor the project for nil-period automatically implement one-hot oscillation only. encoding for the entire project. Altera strongly recommends using the One-Hot Output Enable A high logic level on the State Machine Encoding option rather than Output Enable signal enables the output. manual one-hot encoding. In MAX 7000 devices (not including This option is available in both multi-level MAX 7000E devices), the signal from the and standard synthesis. It is ignored if it active-low global Output Enable pin must does not apply to the current device family. be inverted and connected to the active- high Output Enable input of the TRI OrCAD Library File (.lib) A binary file (with primitive. In all other device families, the extension .lib) containing information either active-high or active-low polarity that describes how symbols are displayed can be used. in OrCAD Schematic Files (.sch). In MAX 9000 devices, the Fitter The MAX+PLUS II Graphic Editor uses an automatically inserts additional LCELL OrCAD-generated OrCAD Library File to primitives to provide the correct polarity import an OrCAD Schematic File. The for a non-global Output Enable pin or an OrCAD Library File for each OrCAD Output Enable signal driven by a logic cell. Schematic File should contain all libraries for the OrCAD symbols used in the P schematic. This OrCAD Library File must also be copied to same directory as the parameter or parameterized A parameter is OrCAD Schematic File. an attribute of a megafunction or macrofunction that determines the logic OrCAD Schematic File (.sch) A schematic created or used to implement the function, design file (with the extension .sch) created i.e., a characteristic that determines the with the OrCAD Draft schematic editor. size, behavior, or silicon implementation of You can open and edit an OrCAD a function. The parameter information can Schematic File in MAX+PLUS II and save it be used to determine the actual primitives as both a Graphic Design File (.gdf) and an and other subdesigns needed to implement OrCAD Schematic File (.sch). An OrCAD the logic of the function. Schematic File can also be compiled directly by the MAX+PLUS II Compiler. A parameterized function is a function whose behavior is controlled by one or more parameters. Some logic functions,
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Glossary
such as the functions in the Library of represented as a node with an input, Parameterized Modules (LPM), are output, or bidirectional I/O type and a pin inherently parameterized and require input, registered, or combinatorial node parameter values to be assigned. type.
Parameters can be assigned to any You can assign a logic function to a specific individual instance of a megafunction in pin number. You can also assign a logic MAX+PLUS II to control its size or function to a row or a column to ensure that implementation. Some parameters can also the function is implemented in a pin on a be applied to old-style macrofunctions to particular row or column. determine their style of implementation. MAX+PLUS II also allows you to assign pin number A number used to assign an global, project-wide default values for input or output signal in a design file, parameters. which corresponds to the pin number on an actual device. parameterized module A logic function that uses parameters to achieve scalability, Both letters and digits are used to specify adaptability, and efficient silicon pin numbers for PGA-package devices. implementation. MAX+PLUS II supports a variety of parameterized modules (also pinstub In the Graphic and Symbol Glossary called Òparameterized functionsÓ), Editors, a pinstub is the location on the including functions belonging to the boundary of a symbol represented by an Glossary Library of Parameterized Modules (LPM). ÒxÓ in a Symbol File (.sym) and a name that represents an input or output of the LPM functions provide architecture- primitive or of the megafunction or independent design entry for all macrofunction design file that the symbol MAX+PLUS II-supported devices. The represents. A line (node) drawn in a MAX+PLUS II Compiler includes built-in schematic must connect to this pinstub to compilation support for LPM functions be recognized by the Compiler as a used in schematic, AHDL, VHDL, Verilog connection between the logic in the current HDL, and EDIF input files. file and the logic in the primitive, megafunction, or macrofunction. pin A pin is an actual input or I/O pin on an Altera device. You can specify whether or not to use an optional pinstub when you edit a symbol In Graphic Editor files, a pin is represented instance in a Graphic Editor file. by an INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, or BIDIRC symbol. In a Text Pinstubs in Graphic Editor files are Design File (.tdf), a pin is represented as an synonymous with ports in AHDL Function INPUT, OUTPUT, or BIDIR port. In a VHDL Prototypes and VHDL Component Design File (.vhd), a pin is represented as Declarations. They are also synonymous an IN, OUT, or INOUT port. In a Verilog with ports listed in the Subdesign Sections Design File (.v), a pin is represented as an of lower-level Text Design Files (.tdf); in input, output, or inout port. In a Entity Declarations of lower-level VHDL Waveform Design File (.wdf), a pin is Design Files (.vhd); and in Module
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Declarations, Module Instantiations, and PLS-ES development systems include the Gate Instantiations of Verilog Design following MAX+PLUS II applications and Files (.v). features:
pinstub name A symbolic name that ■ Hierarchy Display identifies an input or output of a logic ■ Graphic, Symbol, and Text Editors function. ■ Compilation support for Classic, MAX 5000, MAX 7000/7000E/7000S, In the Symbol Editor, the ÒvisibleÓ pinstub EPF8282, EPF8452, EPM9320, and name appears both inside and outside of EPF10K10 devices the symbol. This ÒvisibleÓ pinstub name ■ EDIF Interfaces (input and output) can be an abbreviation or an alias for the ■ Verilog HDL and VHDL output ÒfullÓ pinstub name, which represents the ■ Timing Analyzer full name of the original input, output, or ■ Message Processor bidirectional pin in a mega- or ■ Programmer macrofunction design file or primitive Function Prototype. POF see Programmer Object File.
You can specify whether or not to display port A symbolic name that represents an the ÒvisibleÓ pinstub name in a Graphic input or output of a primitive or of a design Editor file when you create a pinstub in the file. Symbol Editor. The use or non-use of a particular pinstub (and hence its visibility) In AHDL, a port name in the Subdesign can be customized when you edit a symbol Section represents an input or output of the instance in the Graphic Editor with Edit current file. This port name also appears in Ports/Parameters (Symbol menu). the Function Prototype for the function. When an instance of a primitive or lower- Pinstubs in Graphic Editor files are level design file is implemented with an synonymous with ports in AHDL Function Instance Declaration or an in-line Prototypes and VHDL Component reference, its ports are used to connect it to Declarations. They are also listed in the other functions in the TDF. After an Subdesign Sections of lower-level Text instance is declared, its inputs and outputs Design Files (.tdf); in Entity Declarations of are expressed as names in the format lower-level VHDL Design Files (.vhd); and
PLS-ES A PC-based MAX+PLUS II In VHDL, a port name in the Entity development system, which is Declaration represents an input or output automatically provided on a site license of the current file. When an instance of a when you purchase any PC-based primitive or lower-level design file is MAX+PLUS II development system. implemented with a Component
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Glossary
Instantiation, its ports are connected to Graphic Editor primitives include buffers, signals with Port Map Aspects. flipflops, a latch, input and output primitives, and logic primitives. Primitive In Verilog HDL, a port in a Module symbols for Graphic Editor files are Declaration represents an input or output provided in the \maxplus2\max2lib\ of the current file. When an instance of a prim directory created during installation. lower-level design file is implemented with a Module Instantiation, its ports are AHDL, VHDL, and Verilog HDL connected by order or by name to the primitives, which include buffers, Module Declaration ports of the module flipflops, and a latch, are a subset of the being instantiated. Similarly, when a primitive symbols used in Graphic Editor primitive is implemented with a Module files. Other functions are represented by Instantiation, its ports are used to connect it logical operators, ports, and other by order of other functions in the file. constructs. Function Prototypes for AHDL Verilog HDL gate primitives also contain primitives are built into the MAX+PLUS II ports (called ÔterminalsÓ); when a gate software; Component Declarations for primitive is implemented with a Gate VHDL primitives are provided in the Instantiation, its terminals are connected maxplus2 package in the \maxplus2\ by order to the terminals of the gate being max2vhdlnn\altera directory, where nn is instantiated. Ò87Ó or Ò93Ó. Glossary
A port name in an AHDL Subdesign 1 On a UNIX workstation, the Glossary Section, VHDL Entity Declaration, or maxplus2 directory is a subdirectory Verilog HDL Module or Gate Declaration of the /usr directory. is synonymous with a pin name in a Graphic Design File (.gdf) or Waveform primitive array A single primitive that is Design File (.wdf). A port name that is connected to two or more buses in order to appended to an instance name is represent multiple primitives. synonymous with the full pinstub name in an instance of a symbol in a Graphic Editor probe A unique name assigned to any file. node, e.g., the input or output of a primitive, megafunction, or macrofunction Preset An input signal that which can be used instead of the full asynchronously sets the output of a hierarchical node name throughout register to a logic high (1), regardless of MAX+PLUS II. A probe name thus other inputs. provides a short name to identify a node.
primitive One of the basic functional product term Two or more factors in a blocks used to design circuits with Boolean expression combined with an AND MAX+PLUS II software. Primitives are operator constitute a product term, where used in Graphic Design Files (.gdf), AHDL ÒproductÓ means Òlogic product.Ó Text Design Files (.tdf), VHDL Design Files (.vhd), and Verilog Design Files (.v).
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Programmer Log File (.plf) An ASCII file can save data read from an examined (with the extension .plf) generated by the device in POF or JEDEC File format. Programmer that records programming session commands and messages. project A project consists of all files that are associated with a particular design, Programmer Object File (.pof) A binary file including all subdesign files and related (with the extension .pof) generated by the ancillary files created by the user or by CompilerÕs Assembler module. This file MAX+PLUS II software. The project name contains the data used by the is the same as the name of the top-level MAX+PLUS II Programmer to program an design file in the project, without the Altera device. The MAX+PLUS II filename extension. Programmer can optionally save functional test vectors in a POF. MAX+PLUS II performs compilation, simulation, timing analysis, and programming file A file containing data programming on only one project at a time. for programming Altera devices. Both the MAX+PLUS II Compiler and Programmer propagation delay The time required for can generate programming files. The any signal transition to travel between pins following programming file formats are and/or nodes in a device. available in MAX+PLUS II: R ■ FLEX Chain File (.fcf) ■ Hexadecimal (Intel-Format) File (.hex) radix A number base. Group logic level ■ Jam File (.jam) and numerical values are entered and ■ JEDEC File (.jed) displayed in binary, decimal, hexadecimal, ■ JTAG Chain File (.jcf) or octal radix in MAX+PLUS II. ■ Programmer Object File (.pof) ■ Raw Binary File (.rbf) RAM Random-access memory. You can ■ Serial Bitstream File (.sbf) implement RAM with Embedded Array ■ Serial Vector Format File (.svf) Blocks (EABs) in the FLEX 10K device ■ SRAM Object File (.sof) family, and with arrays of flipflops or ■ Tabular Text File (.ttf) latches in other device families.
POFs, SOFs, JEDEC Files, JCFs, and FCFs range A sequence of numbers or are used to program or configure devices arithmetic expressions that define the with the MAX+PLUS II Programmer; test width of a group (bus). A range is enclosed vectors for functional testing can be saved in brackets; the most significant bit (MSB) in POFs and JEDEC Files. All other file of the range is shown first; the least formats are used to program or configure significant bit (LSB) is shown last. The start devices in other environments. and end of the range are separated by two periods in the Graphic Editor and in JEDEC Files generated by A+PLUS and AHDL, and by a colon in Verilog HDL. PLDshell Plus software can also be used to program Classic devices. The Programmer
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Glossary
Example: group a[2..0] consists of the registered output The output of a flipflop nodes a2, a1, and a0; the MSB is a2; and or latch, which can feed an output pin on the LSB is a0. the device.
Raw Binary File (.rbf) A binary file (with registered performance The minimum the extension .rbf) containing required Clock period and the maximum configuration data for FLEX 6000, Clock frequency for a circuit, which can be FLEX 8000, and FLEX 10K devices. This file calculated in the MAX+PLUS II Timing is the binary equivalent of a Tabular Text Analyzer. File (.ttf). The Clock period equals the maximum You can create RBFs that support Passive delay from the Q output of a flipflop to the Parallel Synchronous (PPS), Passive D or Clock Enable input of a flipflop, plus Parallel Asynchronous (PPA), and Passive the internal setup time and propagation Serial (PS) configuration schemes in delay through the flipflop. Clock skew MAX+PLUS II. calculations may increase the Clock period. The Clock frequency equals (1/Clock register see flipflop. period).
register packing A feature of logic cells in 1 The Timing Analyzer does not Glossary MAX 9000 and FLEX 10K devices that calculate registered performance for allows two logic functionsÑa a signal path that passes through the Glossary combinatorial logic function and a register primary (data) input to a flipflop. with a single data inputÑto be implemented in the same logic cell. Report File (.rpt) An ASCII text file (with the extension .rpt), generated by the You can manually implement register CompilerÕs Fitter module, that shows how packing by assigning two logic functions to device resources are used by the project. If the same logic cell. In addition, the Global a module preceding the Partitioner Project Logic Synthesis command (Assign generates an error, this file is not menu) includes an Automatic Register generated. If the Partitioner generates an Packing option to allow the Compiler to error, the Report File is generated in most automatically implement register packing cases. for appropriate pairs of logic functions. Altera strongly recommends using the Reset An active-high input signal that Automatic Register Packing option rather asynchronously resets the output of a than manual logic cell assignments to register to a logic low (0) or a state machine implement register packing. to its initial state, regardless of other inputs. This option is available in both multi-level and standard synthesis. It is ignored if it resource A resource is a portion of an does not apply to the current device family. Altera device that performs a specific, user- defined task (e.g., pins, logic cells). registered feedback Feedback that is the output of a flipflop or latch.
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resource assignment An assignment of a segment see memory segment. logic function in a project to a particular pin, logic cell, I/O cell, embedded cell, Serial Bitstream File (.sbf) An ASCII file logic array block (LAB), embedded array (with the extension .sbf) that contains the block (EAB), row, column, or chip. This data for configuring a FLEX 6000, type of resource assignment assigns a logic FLEX 8000, or FLEX 10K device with the function to a physical resource in a device. BitBlaster from a system prompt. This file can be generated with the Combine A resource assignment can also consist of a Programming Files command (File menu) clique, logic option, connected pin, timing in the Compiler or the Simulator. requirement, or local routing assignment to a particular logic function in a project. This Serial Vector Format File (.svf) An ASCII type of resource assignment assigns a file (with the extension .svf) that stores compilation resource to a logic function. programming data for programming one or more fixed algorithm devices in row A horizontal line of LABs connected Automated Test Equipment (ATE)-type by a row FastTrack Interconnect path in a programming environments. AlteraÕs FLEX 6000, FLEX 8000, FLEX 10K, or MAX 7000S and MAX 9000 devices can be MAX 9000 device. programmed with SVF Files. The JTAG chain can contain any other device that RS-232 port see COM port. complies with the IEEE 1149.1 JTAG specification, including FLEX 10K, S FLEX 6000, and some FLEX 8000 devices. You can create SVF Files with the Create SCF see Simulator Channel File. Jam or SVF File command (File menu) in the Programmer or the Compiler. SDF Output File see Standard Delay Format Output File. setup time On a flipflop, the setup time is the minimum time interval between the secondary input The Clock, Preset, application of a signal at the input pin that synchronous and asynchronous Reset feeds the data or Clock Enable input and a (Clear), and synchronous and low-to-high transition at the input pin that asynchronous Load inputs to a register or a feeds the Clock input of the flipflop or the state machine in a design file. Latch Enable input of the latch.
Security Bit A bit that prevents an On a latch, the setup time is the minimum EPROM- or EEPROM-based Altera device time interval between the application of a from being interrogated. This bit also signal at the input pin that feeds the data prevents EPROM-based Altera devices input of a latch and a low-to-high from being inadvertently reprogrammed. transition at the input pin that feeds the Latch Enable input of the latch. (Setup and The Security Bit can be turned on or off for hold time analysis for latches is available each device in a project, or for the entire only for MAX 5000 devices. In other device project. families, latches are implemented using combinatorial logic with feedback.)
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Glossary
On an asynchronous RAM block, the setup group, and memory values, including time is the minimum time interval between initialized values entered with the the application of a signal at the input pin SimulatorÕs Initialize Nodes/Groups and that feeds the data or address inputs and a Initialize Memory commands (Initialize low-to-high or high-to-low transition at the menu) or the Command File (.cmd) GROUP input pin that feeds the Write Enable input INIT and NODE INIT commands. The SIF of the RAM block. allows you to reuse a previously saved set of node and group values. Internal setup times for flipflops, latches, and asynchronous RAM, which are not Simulator Netlist File (.snf) A binary file user-defined, similarly constrain signals (with the extension .snf) that contains the that are generated within the device. data for functional simulation, timing simulation or timing analysis, or linked shared local interconnect Dedicated multi-device simulation. Three optional connection paths on FLEX 6000 devices Compiler modules create the different that allow signals to travel quickly between types of SNFs that contain the information logic cells in the same LAB or adjacent required for different simulation modes LABs, or between logic cells on the and/or timing analysis: periphery of the device and I/O pins. Shared local interconnect is the fastest ■ The Timing SNF Extractor generates a Glossary interconnect available in FLEX 6000 timing SNF that contains all data devices. required for timing simulation and full Glossary timing analysis. SIF see Simulator Initialization File. ■ The Functional SNF Extractor generates a functional SNF that Simulator Channel File (.scf) A graphical contains all data required for waveform file (with the extension .scf) that functional simulation. is both an input and an output to the ■ The Linked SNF Extractor generates a Simulator. This file contains a waveform linked SNF that combines timing and/ representation of the vector values on the or functional data from the timing, input nodes that drive simulation, as well functional, and/or linked SNFs for as the buried and output nodes to be other previously compiled projects. If simulated. Waveforms in the file represent all of the combined SNFs are timing high (1), low (0), high-impedance (Z), and SNFs, a linked SNF can also be used for undefined (X) logic levels. full timing analysis.
An SCF can be created and viewed in the Only one type of SNF can exist at any Waveform Editor; the Simulator also particular time for the same project. automatically creates and updates an SCF during simulation. An SCF can also be single-range group (or bus) name The used to provide the vector inputs for name of a group (or bus) of up to 256 functional testing in the Programmer. nodes, consisting of an identifier with up to 32 name characters, followed by a range of Simulator Initialization File (.sif) A file numbers or arithmetic expressions in (with the extension .sif) that saves all node, brackets. The start and end of the range are
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separated by two periods. Each number in simulators that use simulation libraries the sequence represents an individual node that are compliant with VITAL version 2.2b (or Òbus bitÓ). The identifier cannot end and version 3.0 (VITAL 95); back- with a digit. annotation for simulation in Verilog HDL simulators; and timing analysis and Example: group a[4..1] consists of the resynthesis with EDIF simulation and nodes a4, a3, a2, and a1. synthesis tools.The Standard Delay Format (SDF) is an industry-standard format. In a Graphic Editor files, a sequential bus name can also include one or more single- The MAX+PLUS II CompilerÕs EDIF, range bus names in a series. The first node VHDL, and Verilog Netlist Writer modules of the series or the first node in the first of the MAX+PLUS II Compiler can range is the most significant bit of the bus; generate SDF Output Files in SDF version the last node of the series or the last node in 2.1 or 1.0 format. the last range is the least significant bit. standard synthesis Logic synthesis that Example: a[8..0], b1, dout[6..4] includes the following logic options:
SNF see Simulator Netlist File. ■ Fast I/O ■ Global Signal SOF see SRAM Object File. ■ Hierarchical Synthesis ■ Insert Additional Logic Cell source node A node that is tagged ■ Minimization (Full and Partial) (designated) as the source of a signal for ■ NOT Gate Push-Back the purpose of timing analysis. A source ■ Parallel Expanders node is tagged with the Timing Analysis ■ Slow Slew Rate Source command (Utilities menu), and can ■ SOFT Buffer Insertion be any node that is the output of a ■ Turbo Bit (including logic cell Turbo primitive, megafunction, macrofunction, Bit) or I/O pin. ■ Use LPM for AHDL Operators ■ XOR Synthesis spike see glitch. Standard synthesis includes only these SRAM Object File (.sof) A binary file (with logic options; other options listed in the the extension .sof), generated by the Define Synthesis Style and Advanced CompilerÕs Assembler module, that Options dialog boxes (Assign menu) are contains the data for configuring an Altera available only in multi-level synthesis. This FLEX 6000, FLEX 8000, or FLEX 10K type of logic synthesis is available only for device. the Classic, MAX 5000, MAX 7000, and MAX 9000 device families. Standard Delay Format Output File (.sdo) An optional output file (with the extension state bit An output of a flipflop used by a .sdo) containing timing delay information state machine to store one bit of the value of that allows you to perform back- the state machine. annotation for simulation with VHDL
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Glossary
state machine A sequential circuit that Unquoted subdesign name (AHDL): advances through a number of states. A state machine can be defined in a Maximum 32 characters Waveform Design File (.wdf), State length: Machine File (.smf), Vector File (.vec), Legal a-z, A-Z, 0-9, and VHDL Design File (.vhd), Verilog Design characters: underscore (_) File (.v) or in a State Machine Declaration in An unquoted subdesign an AHDL Text Design File (.tdf). name cannot be a reserved AHDL identifier or keyword. sub-project see super-project. Quoted subdesign name (AHDL): subdesign A lower-level design file in a MAX+PLUS II project, i.e., an Altera- Maximum 32 characters provided or user-created megafunction or length: macrofunction. Legal a-z, A-Z, 0-9, dash (-), and _ Altera provides libraries of mega- and characters: underscore ( ) macrofunctions in the mega_lpm and mf subdirectories of the \maxplus2\max2lib Identifier (VHDL): directory. AHDL Include Files (.inc) for Glossary these functions are located in the Maximum 32 characters \maxplus2\max2lib\mega_lpm and length: Glossary \maxplus2\max2inc directories, Legal a-z, A-Z, 0-9, and underscore respectively. Component Declarations for characters: (_) functions supported by VHDL are An identifier cannot begin provided in the maxplus2 and megacore with a digit or an underscore, packages in the altera library and the cannot end with an lpm_components package in the lpm underscore, and cannot have library. Both of these libraries are located in two underscores (_ _) in the \maxplus2\vhdlnn directory, where succession. It cannot be a nn is Ò87Ó or Ò93.Ó Megacore keyword. megafunctions must be purchased from Altera before you can use them in your Identifier (Verilog HDL): design(s). (On a UNIX workstation, the maxplus2 directory is a subdirectory of the Maximum 32 characters /usr directory.) length: Legal a-z, A-Z, 0-9, and subdesign name or entity name A name characters: underscore (_) that represents the name of a subdesign. In AHDL, the subdesign name is a quoted or An identifier cannot begin unquoted symbolic name that must be the with a digit. Identifiers are same as the Text Design File (.tdf) filename. case-sensitive. Verilog HDL In VHDL, the entity name is an identifier. keywords cannot be used.
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1 In the UNIX workstation ID numbers to nodes when the project is environment, filenames and hence compiled. In the Hierarchy Display subdesign names are case-sensitive. window, the name of each lower-level design file is appended with a colon (:) sum-of-products A Boolean expression is plus the ID number or an AHDL,VHDL, or said to be in sum-of-products form if it Verilog HDL mega- or macrofunction consists of product terms combined with instance name. the OR operator. T super-project and sub-project A super- project consists of a top-level design file Table File (.tbl) An ASCII file (with the that contains symbols or instances extension .tbl) that contains a tabular- representing multiple, individual projects. format list of all input vectors and output logic levels in the current Vector File (.vec) A sub-project is any individual project that or Simulator Channel File (.scf). The Table serves as part of a super-project. You can File can be generated in the Simulator or use any super-project as a sub-project in a Waveform Editor. higher-level super-project. Tabular Text File (.ttf) An ASCII text file in SVF File see Serial Vector Format File. tabular format (with the extension .ttf) containing configuration data for Symbol File (.sym) A graphic file (with the FLEX 6000, FLEX 8000, and FLEX 10K extension .sym) created by the Symbol devices. A TTF contains the decimal Editor or the Compiler Netlist Extractor equivalent of a Raw Binary File (.rbf). module of the Compiler. This file represents a design file (i.e., megafunction The MAX+PLUS II Compiler automatically or macrofunction) or MAX+PLUS II creates TTFs containing configuration data primitive with the same name and can be for the sequential Passive Parallel used in Graphic Design Files (.gdf). Synchronous (PPS), Passive Parallel Asynchronous (PPA), and Passive Serial When the CompilerÕs Linked SNF (PS) configuration schemes for FLEX 8000 Extractor module is turned on, a symbol in devices, the PS configuration scheme for a Graphic Editor file represents a Simulator FLEX 10K devices, and the PS and Passive Netlist File (.snf), rather than a design file, Serial Asynchronous (PSA) configuration during compilation. schemes for FLEX 6000.
symbol ID number or net ID number A After compilation, you can also create TTFs number that uniquely identifies every that support other configuration schemes node and symbol in a design file. for FLEX 6000, FLEX 8000, and FLEX 10K devices. In the Graphic Editor, this number appears inside the bottom left corner of a symbol tCO (Clock to output delay) The time and reflects the order in which symbols are required to obtain a valid output at an entered in a Graphic Editor file. In other output pin that is fed by a register after a types of design files, the Compiler assigns Clock signal transition on an input pin that
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clocks the register. This time always Text Design Output File (.tdo) An ASCII represents an external pin-to-pin delay. text file (with the extension .tdo), generated by the MAX+PLUS II Compiler, that tCO is also a timing assignment that contains the AHDL equivalent of the fully specifies the maximum acceptable Clock to optimized logic for a device in the project. output delay. In MAX+PLUS II, you can specify a required tCO for an entire project The Compiler generates a TDO File, as well and/or for any input pin (INPUT or as an Assignment & Configuration Output INPUTC), output pin (OUTPUT or File (.aco) when you compile a project if OUTPUTC), or TRI buffer (i.e., BIDIR or you turn on the Generate AHDL TDO File BIDIRC pin output function) pin. command (Processing menu).
TDF see Text Design File. You can save a TDO File as a Text Design File (.tdf) and recompile it. (You must also ternary operator An operator that selects save the Assignment & Configuration between two expressions within an AHDL Output File (.aco) as an Assignment & arithmetic expression. The ternary Configuration File (.acf) if you wish to operator is used in the following format: preserve the assignments for the device.) TDO Files facilitate back-annotation and
Text Design Export File (.tdx) An ASCII ns nanosecond text file (with the extension .tdx) in AHDL ms millisecond that is optionally generated when you us microsecond compile a Xilinx Netlist Format File (.xnf). s second It contains the same logic as the XNF File. mhz megahertz A Text Design Export File can be saved as a A time value is always followed Text Design File (.tdf) and used to replace immediately (i.e., with no space in the corresponding XNF File in the between) by a time unit. If you do not enter hierarchy of a project. a time unit, either ns or mhz is assumed as the default, depending on the appropriate Text Design File (.tdf) An ASCII text file context. (with the extension .tdf) written in AHDL. Text Design Export Files (.tdx) and Text Timing Analyzer Output File (.tao) An Design Output Files (.tdo) can be saved as ASCII text file (with the extension .tao) that TDFs and compiled with MAX+PLUS II. is used to save the results of the current
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timing analysis displayed in the Output Enable input is low, the output MAX+PLUS II Timing Analyzer. signal is in a state of high impedance. The tri-state buffer is implemented with the timing assignment An assignment that TRI primitive. specifies desired speed performance on one or more logic functions. Tri-state buses can be implemented by tying multiple nodes together in a Graphic The tPD, tSU, tCO, and fMAX timing Editor file and with the TRI_STATE_NODE assignments, as well as Òtiming cuts,Ó are variable in an AHDL file. available. You can assign timing to individual logic functions and specify tSU (Clock setup time) The length of time default timing for the project as a whole. for which data that feeds a register via its Timing assignments influence project data or Enable input(s) must be present at compilation only for the FLEX 6000, an input pin before the Clock signal that FLEX 8000, and FLEX 10K device families. clocks the register is asserted at the Clock pin. timing cut A type of timing assignment that cuts the connections between the tSU is also a timing assignment that timing path for an individual node and specifies the maximum acceptable Clock other nodes in the project, to indicate that setup time. In MAX+PLUS II, you can the Compiler should not consider the delay specify a required tSU for an entire project along this path when it attempts to meet and/or for any input pin (INPUT or the userÕs desired speed performance INPUTC) or bidirectional pin (BIDIR or while processing the project. BIDIRC input function).
tPD (input to non-registered output delay) TTF see Tabular Text File. The time required for a signal from an input pin to propagate through Turbo Bit and logic cell Turbo Bit A control combinatorial logic and appear at an bit for choosing speed and power external output pin. characteristics of an Altera device. The Turbo Bit logic option is most effective tPD is also a timing assignment that when applied to megafunctions, specifies the maximum acceptable input to macrofunctions, and pins. If the Turbo Bit non-registered output delay. In is on, the speed increases; if it is off, the MAX+PLUS II, you can specify a required power consumption decreases. The Turbo tPD for an entire project and/or for any Bit can be turned on or off in a design file or input pin (INPUT or INPUTC), output pin the Compiler. (OUTPUT or OUTPUTC), or TRI buffer (i.e., BIDIR or BIDIRC pin output function) Turbo Bit availability differs for each pin. device family
tri-state buffer A buffer with an input, output, and controlling Output Enable signal. If the Output Enable input is high, the output signal equals the input. If the
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. Altera Device Turbo Bit Availability: macrofunctions, Symbol Files (.sym), Family: AHDL Include Files (.inc), or precompiled, user-defined VHDL packages. Classic Applies to the entire device (specified as a The Compiler automatically searches for device option) these user-specified libraries when it MAX 5000 Not available compiles a project. The CompilerÕs VHDL MAX 7000 Applies to individual logic Netlist Settings command (Interfaces cells within a device menu) specifies VHDL design libraries for (specified as a logic option) the current project. You can specify which directories contain your other user libraries MAX 9000 Applies to individual logic with the User Libraries command cells within a device (Options menu) in any MAX+PLUS II (specified as a logic option) application. FLEX 6000 Not available FLEX 8000 Not available V FLEX 10K Not available variable A name that represents a node. In In MAX 7000E devices, the Turbo Bit option AHDL, a variable can also represent a state and the Slow Slew Rate option on output machine or an instance of a primitive, pins are controlled by a single bit. megafunction, or macrofunction and is Therefore, only one of these options can be declared in the Variable Section. In VHDL, turned on on an output pin at any one time. variables have a single current value, and If both options are turned on or if both are declared and used only in processes options are turned off, the Compiler uses and subprograms. A VHDL variable is the Slow Slew Rate setting and ignores the declared with a Variable Declaration; the Turbo Bit setting. On input pins and buried value of a variable can be modified with a logic cells, the Compiler uses the Turbo Bit Variable Assignment Statement. setting and ignores the Slow Slew Rate setting. VCC A high-level input voltage represented as a high (1) logic level in two’s complement A system of binary group values. representing binary numbers in which the negative of a number is equal to its inverse In an AHDL Text Design File (.tdf), VCC is plus 1. Arithmetic operators in AHDL a predefined constant and keyword, and assume that groups they operate on are a the default active node value. In a VHDL twoÕs complement binary number. In Design File (.vhd), VCC is represented VHDL, you must declare a twoÕs by'1'. In a Verilog Design File (.v), VCC is complement binary number with a signed represented by 1. In a Graphic Editor file, data type. VCC is a primitive symbol. VCC is represented as a high (1) logic level in the U Simulator and Waveform Editor.
user libraries One or more directories that vector A vector specifies the logic levels contain your own megafunctions, for an individual node within a project. The
339 Altera Corporation 81_GSBOOK.fm5 Page 340 Tuesday, October 14, 1997 4:04 PM
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Simulator uses vectors to simulate the MAX+PLUS II as an EDIF Input File (.edf). behavior of the project; the Programmer In addition, you can directly process a and Simulator use vectors for functional Verilog Design File (.v) in MAX+PLUS II testing. with Synopsys tools if you turn on the Synopsys Compiler command (Interfaces Vectors for simulation and functional can menu). The MAX+PLUS II Compiler can be defined in Vector Files (.vec) or also generate a Verilog Output File (.vo) Simulator Channel Files (.scf). Functional that contains functional and timing testing vectors can also be stored in information for simulation with a standard programming files. Verilog HDL simulator.
Vectors for design entry can be defined in a Verilog Output File (.vo) A Verilog Waveform Design File (.wdf). Hardware Description Language (HDL) standard netlist file (with the extension .vo) Vector File (.vec) An ASCII file (with the that is generated by the Verilog Netlist extension .vec) that contains vectors that Writer module of the Compiler. This file specify the logic levels of input nodes in a can be exported to an industry-standard project. The Simulator uses this file to test Verilog HDL simulator for simulation. A the logical operation of the project; the Verilog Output File cannot be compiled Programmer and Simulator can also use a with the MAX+PLUS II Compiler. Vector File for functional testing. VHDL Very High Speed Integrated Circuit In addition, a Vector File can also be (VHSIC) Hardware Description Language. converted into a Waveform Design File (.wdf) for design entry. You can create a VHDL Design File (.vhd) with the MAX+PLUS II Text Editor or any Verilog Design File (.v) A Verilog HDL standard text editor and compile it directly File (with the extension .v) created with the with MAX+PLUS II. You can also generate MAX+PLUS II Text Editor or any other an EDIF 2 0 0 or 3 0 0 netlist file from a standard text editor. Verilog Design Files VHDL design that has been processed with can be compiled with the MAX+PLUS II a VHDL synthesis tool, then import the file Compiler. into MAX+PLUS II as an EDIF Input File (.edf). The MAX+PLUS II Compiler can Verilog HDL A Hardware Description also generate a VHDL Output File (.vho) Language (HDL). that contains functional and timing information for simulation with a standard You can create a Verilog Design File (.v) VHDL simulator, and a VHDL Memory with the MAX+PLUS II Text Editor or any Model Output File (.vmo) that contains standard text editor and compile it directly simulation models for a RAM or ROM with MAX+PLUS II. block.
You can also generate an EDIF 2 0 0 or 3 0 0 VHDL Design File (.vhd) An ASCII text file netlist file from a Verilog HDL design that (with the extension .vhd) written in VHDL. has been processed with a Verilog HDL VHDL Design Files can be compiled by the synthesis tool, then import the file into MAX+PLUS II Compiler.
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VHDL Memory Model Output File (.vmo) A include state machines with waveforms Compiler-generated VHDL standard that represent different state names. netlist file (with the extension .vmo) that contains VHDL simulation models. The waveform interval In the Waveform Compiler automatically generates a VHDL Editor, an interval is a segment of a node or Memory Model Output File for the project group waveform that represents its logic when it generates an EDIF Output File level or state name over a specific period of (.edo) that contains one or more RAM or time. ROM blocks. WDF see Waveform Design File. VHDL Output File (.vho) A VHDL standard netlist file (with the extension .vho) that is X generated by the VHDL Netlist Writer module of the Compiler. This file can be Xilinx Netlist Format (XNF) File (.xnf) A exported to an industry-standard VHDL netlist file (with the extension .xnf) simulator for simulation. A VHDL Output generated by Xilinx software. XNF Files File cannot be compiled with the that are generated by running the Xilinx MAX+PLUS II Compiler. LCA2XNF utility can be compiled directly by the MAX+PLUS II Compiler. An XNF VITAL (VHDL Initiative Toward ASIC File can define all logic in a project, or be Libraries) An industry-standard format incorporated at the bottom level in a for VHDL simulation libraries. hierarchical project.
MAX+PLUS II provides VHDL cell simulation models that are compliant with VITAL version 2.2b and version 3.0 (VITAL 95). In addition, the EDIF, VHDL, and Verilog Netlist Writer modules of the MAX+PLUS II Compiler can generate an optional Standard Delay Format (SDF) Output File (.sdo) for use with VITAL- compliant simulation libraries.
VMO File see VHDL Memory Model Output File.
W
Waveform Design File (.wdf) A graphical waveform design file (with the extension .wdf) created with the MAX+PLUS II Waveform Editor. This file represents logic with high (1), low (0), undefined (X), and high-impedance (Z) waveforms. It can also
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342 Altera Corporation
Index
Nonalphabetic AHDL command 90 AHDL Template command 187, 189 .cshrc file 26, 28, 30, 32, 68, 288 Altera Design File (.adf) 95, 96, 129 .profile file 68, 288 altera library 123 .xinitrc file 288 Altera Megafunction Partner Program /usr/lib/x11/fonts directory 292 (AMPP) authorization codes 49 /usr/max2work directory Altera Programmer driver 11 see max2work directory alterad daemon 4, 34, 35, 37, 39 /usr/maxplus2 directory AMPP authorization codes 49 see maxplus2 directory Analyze Timing command 268 /windows directory 294 ancillary file definition 86 \lit directory xvii, xviii, 51 anti-virus software 8 Applications Department 282 Numerics Arc tool 171 Assembler module 137 8count macrofunction 173 Assignment & Configuration File (.acf) 97, 109, 115, 130, 135, 234 A assignments back-annotating 99 A+PLUS 95 bins 115 About MAX+PLUS II command 92 device 98 ACF 97, 109, 115, 130, 135, 234 logic option 99 adapters parameters 100 installing 58 resource 98, 114 releasing 59 viewing 104 adders 118 Authorization Code command 48, 80 ADF 95, 96, 129 auto_max.tdf file 157, 193 Adobe Acrobat Reader 51 autoexec.bat file 68 AHDL Auto-Indent command 188 auto_max.tdf file 193 Boolean equations 190 B general description 117 If Then Statement 192 Back button 92 Logic Section 190 Back-Annotate Project command 234 megafunction support 124 back-annotation 99 primitives 123 Backus-Naur Form xxii Register Declaration 189 backward compatibility, A+PLUS & state machines 193 SAM+PLUS 95 Subdesign Section 187 balloon text 116 templates 109, 117 Basic Tools command 90 time_cnt.tdf file 186 BBS 282, 283 used with Text Editor 108 Variable Section 189
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BitBlaster colors, customizing 286 baud rate dipswitch settings 63 COM port 289 capabilities 150 Command File (.cmd) 109, 145, 257 installation 61 command shortcuts 94, 161 bldfamily utility 292 command-line operation 79, 277 BNF see Backus-Naur Form Commands command 90 Boolean equations (AHDL) 190 Compiler branch buttons 126 general description 128 breakpoints 145 input files 129 bulletin board service (BBS) 282, 283 modules and output files 132 bus lines 181 tutorial sessions 216, 231 buses Compiler command 217, 236 connecting 104, 182 Compiler Netlist Extractor module 132 creating 112 Compiler Netlist File (.cnf) 132 naming 182 conditional logic (AHDL) 118 Button 2 menus 102, 161 Configuration EPROM devices 153 ByteBlaster Configure button 153 capabilities 150 connected pin assignments 98 installation 65 connection dots 213 Windows NT driver installation 11 constants 118 Contents button 92 C context-sensitive help 94, 109, 162 context-sensitive menus 102 CD-ROM counters 112, 118 mounting 16 Create Default Include File command 101 running help from the CD-ROM 19 Create Default Symbol command 101, 106, unmounting 25 184, 214 chip assignments 98 Create Table File command 260 chiptrip project .cshrc file 26, 28, 30, 32, 68, 288 see tutorial Current Assignments Floorplan chiptrip.gdf file 210 command 234 chiptrip.scf file 245 Cut Off Clear & Preset Paths command chiptrip.tbl file 260 268 chkdsk command 7 Cut Off I/O Pin Feedback command 268 Circle tool 171 Classic devices 74, 153 D Clear signal 100, 138, 149, 268 clique assignments 98 Database Builder module 133 cliques, finding 101 decoders 118 Clock signal 100, 112, 138, 149, 206 Decrease Indent command 188 Close command 184 default SCF 143, 147, 246 Close Editor command 230 Delay Matrix 149, 266 CMD file 109, 145, 257 Delay Matrix command 267 CNF 132 delimiters, finding 109 Color Palette command 286 Design Doctor command 219
344 Altera Corporation
Index
Design Doctor Settings command 219 equations, viewing in Floorplan Editor 116 Design Doctor utility 138, 219 error messages 34, 140 design entry, general description 95 ES site licenses 49 design evaluations 282 Esc key 205 design file definition 86 evaluated functions 118 Device command 217 Exit MAX+PLUS II command 167 Device Model File (.dmf) 144, 269 exports file 26 Device View 114, 232 devices F assignments 98 configuring 150 F1 key 162 options 100, 220 fan-in & fan out, viewing 115 partitioning 134 FCF 153 programming 150, 273 feedback 268 selecting 217 file icons 125 supported families 74 file server configuration verifying, examining, blank-checking, see installation, UNIX workstation and testing 154 files Devices & Adapters command 91 checking for basic errors 183 Diagonal Line tool 171 closing 184, 230 directory structure 69 creating 168, 257, 260 Disk Protect 8 opening 226, 228 Ditto drive (Iomega) 46 organization 69 DMF 144, 269 printing 126 drivers, Windows NT 11 saving 169, 183 Find Clique in Floorplan command 101 E Find Next Transition command 208 Find Node in Design File command 101 e-mail 282, 283 Find Node in Floorplan command 101 EDIF Command File (.edc) 109, 129 Find Text command 234 EDIF Input File (.edf) 96, 129, 133 finish.scf file 265 EDIF Netlist Reader module 133 Fit File (.fit) 115, 135, 234 EDIF Netlist Writer module 136, 137 Fit in Window command 175, 201 EDIF Output File (.edo) 136, 137 Fitter module 135 Edit Node/Bus Name command 214 FLEX Chain File (.fcf) 153 Edit Pin Assignments & LCELLs dialog FLEX Download Cable 60, 150 box 236 FLEX 10K devices 74, 138, 153 Edit Pin Name command 212 FLEX 6000 devices 74, 138, 153 electronic mail 282, 283 FLEX 8000 devices 74, 138, 153 Embedded Array Block (EAB) 98, 100 floating-point emulation, disabling 13 embedded cells, assignments 98 Floorplan Editor End Time command 246 general description 114 Enter Nodes from SNF command 246 tutorial sessions 231, 266 Enter Symbol dialog box 172 Floorplan Editor command 232, 237 environment variables 13, 67, 288 fMAX 99, 100
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Font commands 182, 188, 215 Help (continued) font.dir file 292 running from the CD-ROM 19 fonts, UNIX workstation 291, 292, 295 searching for a topic 94, 163 FTP site 282, 283 where to start 93 Function Prototypes 118 Help on Message button 140, 162, 227 functional simulation 143 Help Topics dialog box 92, 163 Functional SNF Extractor module 136 Hexadecimal (Intel-format) File (.hex) 129, functional testing 111, 145, 154 137, 143, 153 Hierarchy Display G general description 125 tutorial session 229 GDF 96, 129, 168, 210 Hierarchy Display command 229 glitch monitoring 145 Hierarchy Interconnect File (.hif) 132 Global Project Device Options command hierarchy traversal 102 220 HIF 132 Global Project Logic Synthesis command History button 92 220 History File (.hst) 145, 257, 263 global signals 100 hold times 145, 149, 258 Glossary button 92 How to Use Help command 92 Glossary command 91 How to Use MAX+PLUS II Help GND pins 115 command 92 Golden Rules command 90 HP 9000 Series 700/800 workstations Graphic Design File (.gdf) 96, 129, 168, 210 see installation, UNIX workstation Graphic Editor HST file 145, 257, 263 general description 103 tutorial sessions 168, 210 I Graphic Editor command 103 Gray code 112 I/O cells 98, 100 Grid Size command 201, 246 I/O pin feedback 149, 268 groups I/O types 112 creating 112 IBM RISC System/6000 workstations initializing 145 see installation, UNIX workstation moving 251 icons GUARD_PORT variable 47 file 125 Guideline Spacing command 175 MAX+PLUS II applications 83 MAX+PLUS II help 89 H If Then Statement (AHDL) 192 Include File (.inc) 101, 118, 130 Hardware Setup command 58, 63, 66 Increase Indent command 188 Help indenting text 188 commands 89 inittab file 34 context-sensitive 94, 109, 162 Inputs/Outputs command 257, 274 Help window buttons 92 Insert Node command 199, 250 icons 89 install program 7 on command shortcuts 94 install.cd program 15
346 Altera Corporation Index installation, PC Interlink program 46 see also network licensing Introduction command 90 Adobe Acrobat Reader 51 Iomega Zip and Ditto drives 46 BitBlaster installation 61 iterative logic generation (AHDL) 118 ByteBlaster installation 65 determining free disk space 7 J file organization 69 FLEX Download Cable installation 60 Jam Files (.jam) 153 Master Programming Unit JEDEC File (.jed) 137, 153 installation 53 JTAG Chain File (.jcf) 153 MegaCore/AMPP authorization jumps 88 codes 49 NEC 9801 steps 13 K read.me file 3 site license 49 keyboard shortcuts 161 Software Guard installation 46 software installation 7 L software registration 4 system requirements 6 LAB View 114, 232 uninstalling 10 LAB View command 232, 271 Windows NT drivers 11 Last Compilation Floorplan command installation, UNIX workstation 232, 237, 271 see also network licensing Latch Enable signal 149 additional configuration information Library Mapping File (.lmf) 109, 133 285 Library of Parameterized Modules (LPM) Adobe Acrobat Reader 51 103, 118, 124 BitBlaster installation 61 license file configuring file server and user installing 21 environment 25 sample file 21 file organization 69 license server configuration mounting the CD-ROM 16 FLEXlm utilities 40 network licensing file 21 setup 33 printer installation 294 troubleshooting 34 read.me file 3 license.dat file software installation 15 FLEXlm 40, 42, 43, 44 specific steps for HP 9000 Series MAX+PLUS II 24, 37, 43 700/800 29 Line Style commands 179, 181, 212 specific steps for IBM RISC lines System/6000 31, 64 deleting 180 specific steps for SPARCstation drawing 179 running Solaris 2.5+ 27 linked multi-project simulation 144 specific steps for SPARCstation Linked SNF Extractor module 136 running SunOS 4.1.3+ 26 List Only Longest Path command 270 system requirements 14 List Paths button 140, 270 unmounting the CD-ROM 25 \lit directory xvii, xviii, 51
Altera Corporation 347 MAX+PLUS II Getting Started
Literature Department 283 MAX+PLUS II lmdown utility 42 application icons 83 LMF 109, 133 command-line mode 277 lmgrd daemon 4, 34, 36, 37, 39, 40 design entry 95 lmhostid utility 45 device programming 150 lmremove utility 43 error detection & location 139 lmreread utility 44 exiting 167 lmstat utility 41 general description 74 lmver utility 45 global features 97 local routing assignments 98 help description 88 local.options file 39 project processing 127 Locate All button 271 project verification 141 Locate button 226, 272 starting 79, 165 location assignments 98 MAX+PLUS II Manager, general Log File (.log) 145, 257, 263 description 81 Logic Array Block (LAB) 98, 114 MAX+PLUS II manuals logic cell registers 98 documentation conventions xix logic cells 114 help updates xxiii editing assignments 115 list of documents xvi logic levels 112 MAX+PLUS II Table of Contents logic option assignments 99 command 89 Logic Programmer Card 54, 56, 150 max2protd script 34, 37 Logic Programmer card 150 max2work directory 87, 160 Logic Section (AHDL) 190 Maximize button 167 logic synthesis 220 maxplus2 directory logic synthesis styles 100 .\fonts directory 69, 292 Logic Synthesizer module 134, 220 .\max2inc directory 69 lp command 295 .\max2lib directory 69, 123 LP6 Logic Programmer Card .\vhdl87 directory 70, 123 I/O addresses & dipswitch settings 56 .\vhdl93 directory 70, 123 installing 54 overall structure 69 maxplus2.ini file 13, 19, 47, 67 M MAXPLUS2_INI environment variable 13, 67 macrofunctions, general description 124 MegaCore authorization codes 49 Marketing Department 282 MegaCore/AMPP Licenses dialog box 49 Master Programming Unit (MPU) 53, 57, megafunctions, general description 123 59, 150 Megafunctions/LPM command 91 matrix, delay 149 memory 145, 291 MAX 9000 devices 74, 153 Memory Initialization Files (.mif) 129, 143 MAX 5000 devices 74, 153 Message button 226, 271, 272 MAX 7000 devices 74, 153 Message Processor MAX+PLUS (DOS) 95 general description 139 tutorial session 216 Message Processor command 226, 270
348 Altera Corporation Index
Message Text File (.mtf) 140 New Features in This Release command messages 92 getting help 162, 227 noclobber variable 279 listing propagation delays 270 Node Database File (.ndb) 132 locating sources 140, 226 nodes 112 Messages command 91 connecting 104, 182 MIF 129, 143 creating 198, 246 mkfontdir utility 292 editing 252 Motif 292 finding 101, 102 MPU gray 235 see Master Programming Unit handles 115, 234, 251 MTF 140 initializing 145 multi-level synthesis 100 moving 251 multiplexers 118 naming 182 multi-project simulation 144 red 115 mwcolormanager utility 288 secondary inputs (in WDFs) 198 MWCOM1 through MWCOM4 variables 289 showing fan-in & fan-out 115, 237, 240 MWFONT_CACHE_DIR variable 290 tagging for timing analysis 102, 149 MWLOOK variable 290 viewing equations 116 MWRGB_DB variable 291 Novell networks 9 MWSCREEN_HEIGHT variable 291 NTFS 13 MWSCREEN_WIDTH variable 291 MWSYSTEM_FONT variable 291 O MWUNIX_SHARED_MEMORY variable 291 MWWM variable 292 old-style macrofunctions see macrofunctions N Old-Style Macrofunctions command 91 one-hot state machine encoding 100 names Open command 263 buses 182 OpenCore megafunctions 91 nodes 182 open-drain pins 100 pins 177 OpenLook 292 pinstubs 107 OrCAD Schematic File (.sch) 96, 104, 129 NDB file 132 Orthogonal Line tool 171, 179 NEC 9801 computers 13 oscillation monitoring 145 network licensing Output Enable signal 100 configuring the license server 33 Override User Assignments dialog box FLEXlm utilities 40 236 license file installation 21 Overwrite Clock command 206, 253 PLS-ES site licenses 49 Overwrite High (1) command 252 sample license file 21 Overwrite State Name command 202, 203 specifying the license file in Overwrite Undefined (X) command 206 MAX+PLUS II 48 troubleshooting license installation 34 New command 103, 168
Altera Corporation 349 MAX+PLUS II Getting Started
P Programmer general description 152 palette tools input & output files 154 Graphic Editor 104, 171, 179 tutorial session 273 Waveform Editor 202 Programmer command 273 parallel port 150 Programmer Log File (.plf) 154, 274 parameter assignments 100 Programmer Object File (.pof) 137, 153, 273 parameters project compilation, general description default values 107 127 in AHDL 118 project definition 87 in macrofunctions 124 Project Name command 170 in megafunctions 124 project name, specifying 170, 171 Partitioner module 134
350 Altera Corporation Index reserved pins 115 Simulator rgb.txt file 291 general description 142 ripple clocks 138 tutorial session 255 ROM initialization 145 Simulator Channel File (.scf) 111, 143, 146, routing information 115, 237, 240 154, 245, 265 Routing Statistics command 239 Simulator command 256 RPT file 115, 130, 135, 222, 228 Simulator Initialization File (.sif) 145 RS-232 port 289 Simulator Netlist File (.snf) 112, 136, 142, rubberbanding 104 147, 148 Rubberbanding command 174 site license 49 smart recompile 133 S Smart Recompile command 218 SmartDrive 9 SAM (HP) 29 SMF 95, 96, 129 SAM+PLUS 95 Snap to Grid command 201 sample files xxiv SNF 112, 136, 142, 147, 148 Save As command 169 SOF 137, 153 SBF 138, 153 Software Guard installation 46 SCF 111, 143, 146, 154, 245, 265 software installation SCH file 96, 104, 129 see installation SDF Output File (.sdo) 120, 122, 137 Software Interface Guides xvii, 51 Search button 92 software registration 4 Search dialog box 92, 163 Solaris 2.5+ operating system Search for Help on command 89, 163 see installation, UNIX workstation Security Bit 100, 154, 220 speed_ch.wdf file 158, 196 segmented hypergraphics 88 SRAM Object File (.sof) 137, 153 Selection tool 104, 171, 179, 202 Standard Delay Format (SDF) Output File Sentinel driver 11 (.sdo) 120, 122, 137 Serial Bitstream File (.sbf) 138, 153 Start button 223 serial port 150, 289 State Machine File (.smf) 95, 96, 129 Serial Vector Format File (.svf) 153 state machines setup & hold times 145, 149, 258 creating 111, 118 Setup/Hold Matrix 149, 266 in AHDL 193 Shift+F1 keys 94, 162 in WDFs 198, 201 shortcuts 161 one-hot encoding 100 Shortcuts command 90 simulating 144 Show Grid command 201 state names 202 Show Guidelines command 175 status bar 166 Show Moved Nodes in Gray command Subdesign Section 187 235, 238 SunOS 4.1.3+ operating system Show Node Fan-In command 237, 241 see installation, UNIX workstation Show Node Fan-Out command 237, 241 support services 281 Show Path command 238, 271 SVF file 153 SIF 145 Symbol Editor command 106 Symbol Editor, general description 106
Altera Corporation 351 MAX+PLUS II Getting Started
Symbol File (.sym) 101, 106, 130, 184 text, finding & replacing 102 symbol ID number 177 third-party interfaces, software installation symbols 15 connecting 179 third-party simulation 137 creating 184 tick_cnt.gdf file 157, 168 entering 172 time_cnt.tdf file 157, 186 flipping & rotating 105 Timing Analysis Destination command moving 176 268 updating 104 Timing Analysis Source command 268 syntax coloring 109, 117, 119, 122 Timing Analyzer Syntax Coloring command 186 delay matrix display 149 System Administration Manager (SAM) general description 148 (HP) 29 tutorial session 266 system requirements Timing Analyzer command 267 PC 6 Timing Analyzer Output File (.tao) 149 UNIX workstation 14 timing assignments 99, 100 system.ini file 13 timing simulation 143 Timing SNF Extractor command 222 T Timing SNF Extractor module 136, 222 Toggle Connection Dot command 213 Tab Stops command 188, 193 tool palette 161 Table File (.tbl) 112, 143, 260, 263 toolbar 161, 166 Tabular Text File (.ttf) 137, 153 Topics Found dialog box 164 TAO file 149 total recompile feature 133 tCO 99, 100 tPD 99, 100 TDF 96, 108, 117, 129, 135, 185 training courses 283 TDO file 118, 135 troubleshooting 285 TDX file 118, 133 truth tables 118 technical publications 283 tSU 99, 100 technical support 282 tty ports 289 templates 109, 117, 119, 122, 187 tutorial text command shortcuts 161 changing font & size 188 Compiler sessions 216, 231 indenting 188 directory 160 templates 109, 117, 119, 122, 187 file locations 160 Text Design Export File (.tdx) 118, 133 Floorplan Editor sessions 231, 266 Text Design File (.tdf) 96, 108, 117, 129, 135, Graphic Editor sessions 168, 210 185 Hierarchy Display session 229 Text Design Output File (.tdo) 118, 135 Message Processor session 216 Text Editor Overview 160 general description 108 Programmer session 273 tutorial sessions 185, 261 simulation driving map 243 Text Editor command 108 simulation overview 242 Text Size commands 182, 188, 215 Simulator session 255 Text tool 171 Text Editor/AHDL sessions 185, 261
352 Altera Corporation Index tutorial (continued) virus-detection software 8 Timing Analyzer session 266 visible pinstub names 107 Waveform Editor sessions 196, 245, 261 VO file 136, 137 vsafe.com 8 U W UNIX workstation installation see installation, UNIX workstation 14 Waveform Design File (.wdf) 96, 111, 129, /usr/lib/x11/fonts directory 292 146, 196 /usr/max2work directory Waveform Editing tool 202, 205 see max2work directory Waveform Editor /usr/maxplus2 directory general description 111, 146 see maxplus2 directory tutorial sessions 196, 245, 261 Waveform Editor command 111 V waveforms comparing 113 V file 108, 121, 129 creating 111, 198, 246 Variable Section 189 editing 112, 201, 204, 252 VCC pins 115 WDF 96, 111, 129, 146, 196 Vector File (.vec) 109, 143, 146, 154 win.ini file 286, 294, 295 Verilog Design File (.v) 108, 121, 129 /windows directory 294 Verilog HDL Windows NT, installing MAX+PLUS II general description 121 drivers 11 megafunction support 124 workstation installation primitives 123 see installation, UNIX workstation templates 109, 122 world-wide web (www) site xvi, xvii, xxiii, used with Text Editor 108 4, 282, 283 Verilog HDL command 91 Write Enable signal 149 Verilog Netlist Reader 133 Verilog Netlist Writer module 136, 137 X Verilog Output File (.vo) 136, 137 VHD file 96, 108, 119, 129, 133 Xilinx Netlist Format File (.xnf) 96, 129, 133 VHDL .xinitrc file 288 general description 119 XNF Netlist Reader 133 megafunction support 124 primitives 123 Z templates 109, 119 used with Text Editor 108 Zip drive (Iomega) 46 VHDL command 90 Zoom In & Zoom Out commands 175, 201 VHDL Design File (.vhd) 96, 108, 119, 129, 133 VHDL Netlist Reader 133 VHDL Netlist Writer module 136, 137 VHDL Output File (.vho) 120, 122, 136, 137 VHO file 120, 122, 136, 137
Altera Corporation 353