International Journal Of Computer Science And Applications Vol. 6, No.2, Apr 2013 ISSN: 0974-1011 (Open Access)

Available at: www.researchpublications.org

Intel’s 45nm CMOS TECHONOLOGY PERFORMANCE PARAMETERS IN VLSI DESIGN

Mr. Dharmik Narendra Mehta Mr. Pankaj Navin Sanghavi Dr. Ms. U. A. Belorkar M.E. (First Year) M.E. (First Year) Associate Professor and Head, Electronics & Communication Dept. Electronics & Communication Dept. Electronics & Telecommunication, SIPNA College of Engg. & G.H. Raisoni College of Engg. HVPM College of Engg. & Technology, & Management Technology, Amravati, Maharastra, India Amravati, Maharastra, India Amravati, Maharastra, India Email: [email protected] Email: [email protected] Email: [email protected]

In January 2007, introduced one of the ABSTRACT — biggest advancements in fundamental transistor In this paper we describe Intel’s 45nm design in 40 years — the use of dramatically different technology performance parameters and relate it with a transistor materials (a new material combination of other technology . hafnium-based high-k (Hi-k) gate dielectrics and new Firstly, we give an overview of the evolution of metal materials for the gate) to build the hundreds of important parameters such as the integrated circuit (IC) millions of microscopic 45nm transistors inside the complexity, gate length, switching delay and supply voltage next generation of the company’s 2 with a prospective vision down to the 22 nm CMOS technology. processor family. By using the element Hafnium, a metal that significantly reduces electrical leakage and KEY WORDS — provides the high capacitance necessary for good Hafnium-based high-k (Hi-k) gate, 45nm transistor performance. Transistor, Penryn. In the second half of 2007, Intel will begin production of the next generation Intel® Core™2 INTRODUCTION: process family code named "Penryn" which is based The trend of CMOS technology on our industry-leading 45-nanometer (nm) Hi-k improvement continues to be driven by the need to metal gate process technology and latest micro integrate more functions within a given silicon architecture enhancements. This next evolution in area. Table (a) gives an overview of the key Intel Core™ micro architecture builds on the parameters for technological nodes from 180 nm, tremendous success of our revolutionary micro introduced in 1999, down to 22 nm, which is architecture (currently used in both the Intel® ® supposed to be according to Moore’s Law & in and Intel® Core™2 processor families) and marks production around 2011. Demonstration chips using the next step in Intel's rapid cadence for delivering a 45-nm technology have been reported starting in new process technology with an enhanced micro 2004. Mass market manufacturing with this architecture or an entirely new micro architecture technology is scheduled for late 2007. every year.

With more than 400 million transistors for Technology 130 90 65 45 32 22 dual-core processors and more than 800 million for Node (nm) nm nm nm nm nm nm quad-core, the 45nm Penryn family introduces new First 200 200 200 200 201 2003 micro-architecture features for greater performance at production 1 5 7 9 1 a given frequency, plus expanded power management Effective 70 50 35 25 17 12 capabilities for new levels of energy efficiency. The gate length nm nm nm nm nm nm 45nm Hi-k next generation and Intel Gate Pol Pol Me Me Me Poly Xeon processors have more transistors but are about material y y tal tal tal 25 percent smaller in silicon area than Intel® s Gate SiO SiO Hi- Hi- Hi- SiO 2 current 65nm products and operate at the same or Dielectric 2 N K K K lower power than the current Intel Core 2 processors. 150 280 450 Kgates/mm 2 240 480 900 0 0 0 The Penryn family adds to the Intel Core 2 Memory 0.1 0.0 processor Family: 2.4 1.3 0.6 0.3 point (µ 2) 5 8 • A second-generation quad-core desktop Table (a) processor with up to 12MB L2 cache. • A new dual-core desktop processors with up to 6MB shared L2 cache.

NCAICN-2013, PRMITR,Badnera 98 International Journal Of Computer Science And Applications Vol. 6, No.2, Apr 2013 ISSN: 0974-1011 (Open Access)

Available at: www.researchpublications.org

• A new low-power dual-core mobile processor and maximize its utilization. Cache is a with up to 6MB shared L2 cache and a new memory reservoir where frequently accessed low-power state that substantially lowers data can be stored for more rapid access. processor idle power. Larger and faster cache sizes speed a computer's performance and response time. The Penryn family also adds several new processors to the Intel Xeon processor family: 6. Unique Super Shuffle Engine: • A second-generation quad-core dual- Implementing a full-width, single-pass processing (DP) server/workstation processor shuffle unit that is 128-bits wide, Penryn with up to 12 MB L2 cache. processors can perform full-width shuffles in a • A dual-core DP processor with 6MB shared single cycle. This significantly improves L2 cache. performance for SSE2, SSE3 and SSE4 • A multi-processing (MP) quad-core processor instructions that have shuffle-like operations like pack, unpack, and wider packed shifts. currently under development. 7. Streaming SIMD Extensions 4 (SSE4) REMARKABLE PERFORMANCE Instructions: IMPROVEMENTS: The Penryn family includes Streaming

SIMD Extensions 4 (SSE4) instructions, the The Penryn family includes a number of most significant SIMD instruction set addition improvements to help speed up software and improve since the original SSE Instruction Set response times. Architecture (ISA). This extends the Intel® 64 1. Micro architecture optimizations: instruction set architecture to expand the New optimizations increase the overall performance and capabilities of the Intel® performance and energy efficiency of the architecture.

already leading Intel® Core™ micro 8. Intel® Dynamic Acceleration Technology: architecture to deliver more instruction For the mobile Penryn processor, Intel has executions per clock cycle. This means more enhanced the Intel® Dynamic Acceleration performance and quicker computer Technology available in current Intel Core 2 responsiveness. processors. This feature uses the power headroom freed up when a core is made 2. Enhanced Intel® Virtualization inactive to boost the performance of another Technology: still active core. Penryn micro architecture improvements speed up virtual machine transition (entry/exit) 9. Deep Power Down for energy savings and times by an average of 25 to 75 percent. improved battery Life: (Requires no virtual machine software The mobile Penryn processor has a new changes.) advanced power management state called Deep Power Down Technology that 3. Higher Frequencies: significantly reduces the power of the Penryn processors deliver higher core and processor during idle periods such that internal bus clock frequencies within existing power transistor power leakage is no longer a factor. and thermal envelopes to further increase This helps extend battery life in laptops and is performance. Desktop and server products will a major advancement over previous introduce core speeds greater than 3GHz. generationindustry-leading Intel mobile 4. Fast Division of Numbers: Penryn processors provide faster divider performance, roughly doubling the divider speed over previous generations for computations used in nearly all applications through the inclusion of a new, faster divide technique called Radix 16.

5. Larger Caches: Penryn family processors include up to a 50 percent larger L2 cache with a higher degree of associativity to further improve the hit rate

NCAICN-2013, PRMITR,Badnera 99 International Journal Of Computer Science And Applications Vol. 6, No.2, Apr 2013 ISSN: 0974-1011 (Open Access)

Available at: www.researchpublications.org

processors. transistors, Figure (a): Technology scale down to nano- scale 2.4 GHz device 45nm TRANSISTORS: • Intel 2 90 nm A 45nm technology is used in 1.7 billion transistors manufacturing VLSI transistor which has used in 1 GHz both the Intel® Xeon® and Intel® Core™2 processor families. Figure shows the constructional view of NEW TECHNOLOGIES...... NEW 45nm transistor with 50nm gate. (made up of SiO 2) CHALLENGES.....!!

This type of technology increases the switching speed • Power Consumption of the transistor as compared to the previous VLSI Optimization of power, but still want high technology . performance circuit with more features . Glitches were never look with perspective of power but now you cannot ignore them.

• Packing Placing every transistor of circuit on smallest area possible is Herculean task, and then everyone has to be routed.

• Verification Today’s designs require advance testability circuit just to ensure correct manufacturing. More no. of verification teams than design team.

Figure (b): 45nm Transistor • Dealing with leakage problems: This generation problem, as if Ioff = 1 nA, Some of the key features of the 45 nm so even if a 500 million transistor are OFF, technologies from various providers are given in still will leak 0.5 Amperes. Table (b). • Routing Problems While transistor scaling ensures we can pack more in the same area, however an efficient metal stack is required to wire all these transistors.

• Cross talk, Yield Metal width and pitches are reducing, and additional layers of metal are being added. The reduction of metal width causes increased resistance. This leads to increased coupling capacitance which results in more crosstalk between signal lines. Table (b) Yield is a metric of manufacturability, but is RECENT ICs: not limited to process defects. Today, yield can be impacted by crosstalk which could • Intel Dual-Core Processor cause glitches on data or clock resulting in 45nm, intermittent failures which can be impossible More than 400 million to debug if not caught early in the design. transistors, 2.8 GHz. REFERENCES: • Intel Quad-Core (I) White Paper of Introducing the 45nm Next- Processor Generation Intel® Core™ . 45nm, (II) Intel Technology Journal Q2’08 (Volume 12, More than 800 million Issue 2)

NCAICN-2013, PRMITR,Badnera 100 International Journal Of Computer Science And Applications Vol. 6, No.2, Apr 2013 ISSN: 0974-1011 (Open Access)

Available at: www.researchpublications.org

(III) 45nm High-k+Metal Gate Strain-Enhanced Transistors[pp. 10-16] (IV) K. Mistry, et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging.” IEDM Technical Digest , 2007, pp. 247–250.

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