JOURNAL OF COMMUNICATIONS AND INFORMATION SYSTEMS, VOL. 1, NO. 26, APRIL 2011 13 Fast Hardware Design of 1/f Fractional Brownian Noise Generator G. Loss and R. Coelho
Abstract—This paper proposes the design of a fast and accurate signal processing and other scientific areas concerned with 1/f fractional Brownian motion (fBm) noise generator. The noise issues. Hardware architectures for white Gaussian noise solution is based on the successive random addition algorithm generators [11] [12] [13] have been reported in the literature. using the midpoint displacement (SRMD) technique. The imple- mentation was performed on a high-speed field-programmable However, from the authors knowledge, the proposition of a gate array (FPGA) Development Kit. It enabled the generation fast hardware design of 1/f fBm noise generator is addressed of 150 million of 16-bit noise samples per second. The 1/f noise for the first time in this work. This 1/f noise solution de- generator achieved 7.4% of the logic elements, 52% of the RAM scribes a hardware design for the successive random addition memory and 1.6% of the ROM memory. The accuracy of the method using the midpoint displacement (SRMD) technique 1/f noise samples was evaluated for different sequence size and confidence intervals. The noise samples pattern was examined introduced by Mandelbrot [9]. In a preliminary study [14] the by the probability density (PDF) and the heavy-tail distribution SRMD design was proposed and evaluated for the generation (HTD) functions. The results also include the auto-correlation of optical signal samples. The results showed to be very function (ACF) to show the low-frequency statistics of the 1/f promising. noise samples. For the investigation it was used the real 1/f The fractional noise generator was implemented on Altera speech-babble acoustic noise parameters. The results showed that the proposed 1/f noise generator design can be promising to the Stratix EP1S25 FPGA Development Kit using the Quartus performance evaluation of communications channels with low II v5.0 suite for Linux. The design proposed in this work bit error rate (BER) values. It can also be interesting for signal also considered the trade-off between the device resources processing applications and other areas concerned with noisy usage (e.g., memory, logic elements and embedded multipli- conditions. ers) to produce fast and accurate 1/f 16-bit noise samples. The design also includes a Gaussian random variables (RVs) Index Terms—1/f noise, fractional Brownian noise, low- frequency statistics, field-programmable gate array. block generator. The Box-Muller [15] method is the most important approach used for the generation of Gaussian RVs. The generation is based on transformation functions performed I.INTRODUCTION on Uniform variables. In [11] the authors proposed a hard- HE provision of fast and accurate noise generators has ware architecture based on the Box-Muller algorithm and the T become an important issue for digital communications Central Limit Theorem (CLT) [16]. This solution was also systems which attained reliable and high-speed channels. performed by Xilinx [17] and evaluated under different FPGA Moreover, 1/f noise [1] has been observed in several physical devices by the authors in [12] [13]. The results demonstrated systems such as, communication channels [2], electronic com- that the implementation based on both Box-Muller algorithm ponents and semiconductors devices [1] [3], natural phenom- and the CLT achieves accurate and fast Gaussian RVs. Hence, ena (e.g., rivers, ocean flows, average seasonal temperature, this method was used for the Gaussian samples generation. rainfall) [4], financial markets [5], image [6], acoustics and Nevertheless, the solution presented in this work introduces a music [7]. The 1/f noise is a random process characterized memory optimization for the Box-Muller functions evaluation. by its low-frequency or scaling invariance over a wide range The Tckacik algorithm [18] was applied for the Uniform of timescales [8]. White noise represented by the Gaussian RVs generation. This technique achieved fast generation, good distribution, is widely employed since it enables tractable randomness and few device resources requirements. analysis. But, since the presence of 1/f noise is a reality, The proposed design performance was examined in terms its investigation became a key issue. The fractional Brownian of its device resources requirements and the representation of motion (fBm) [8] [9] [10] leads to an efficient representation the pattern and low-frequency statistics (i.e., evaluations of the of the 1/f or fractional noise samples with low-frequency probability density (PDF), heavy-tail distribution (HTD) and statistics or scaling invariance degree represented by the Hurst auto-correlation coefficient (ACF) functions) of the 1/f noise (0
Daubechies filters with 12 coefficients.
II. 1/FFRACTIONAL BROWNIAN MOTION NOISE Generally, noises can be represented by the power spectral density fluctuations per a frequency interval. Or, similarly, by its variations over a time scale of order 1/f β (0 β 2). In the literature, white, red/brow and pink noises are≤ also≤ referred as 1/f 0, 1/f 2 and 1/f noises, respectively. The 1/f noise is a random process with power spectral density (S(f)) defined as S(f) = 1 where 0 β 2. f β ≤ ≤ Mandelbrot showed that 1/f fractional noises have S(f) defined by S(f)= f 1−2H with H parameter values frequently close to 1. Thus, H parameter is the exponent of the power spectral density of the 1/f fractional noises. The H parameter expresses the low-frequency statistics, i.e., the scaling or time- (a) invariance degree, of a random process. It can also be defined by the decaying rate of the auto-correlation coefficient function ρ(k) ( 1 <ρ(k) < 1) as k . A random process can be classified− by its H (0
TABLE I and X[i] RAM memory. All functions performed by the fBm BOX-MULLER GRNG BLOCK block were coded as very-high-speed integrated circuit hard- ware description language (VHDL) entries. In this work, the Compilation Without Memory With Memory usage usage Uniform random numbers generator (URNG) implementation Logic elements 193 158 is based on a combination of multiple-bit linear feedback ROM Memory (bits) 0 382 shift registers (LFSR) and cellular automata shift registers Embedded Multipliers 2 2 (CASR) method proposed in [18]. This method generates a Max Clock Freq. 56 MHz 168 MHz random sample by using XORs with the LFSRs and CASRs registers. This combination leads to a good randomness and the two registered values of the x and x functions. It takes its implementation requires few device resources. The linear 1 2 3 clock cycles: one cycle to store each x and x value and a function was implemented by a XOR of 43-bit position values. 1 2 second cycle for the sum of these values. It can be seen from The cellular automata consists of a circular register with K Eq. 2 and Eq. 3 that both g and g functions are indexed by cells, each having a value a equal to 0 or 1. These values 1 2 i u . Thus, their implementation were pipelined to improve the are synchronously updated in discrete time steps according 2 block performance. to a` = a XOR (a OR a ) or, equivalently, i i−1 i i+1 In this work, two different approaches were evaluated for a` = (a + a + a + a a ) mod 2. The a(t) i i−1 i i+1 i i+1 the implementation of the GRNG block. Firstly, the GRNG values attained by a particular cell through time serve as the block was coded in VHDL using only the available standard random sequence. The URNG block was coded to produce 32- logic elements. In a second approach, a set of Altera Stratix bit uniformly distributed samples with periodicity 1010. The Device Family’s memory blocks was defined to deal with the LSFRs are started with a random seed. LUT size issue. Table I shows the devices resources needed for The Gaussian random number generator (GRNG) block both GRNG implementations. The second strategy achieved (Fig. 1(b)) performs the Gauss( ) function (Fig. 1(a)) of the an improvement of 18% in the logic elements usage. It can SRMD algorithm. The Box-Muller method shows that, given also be noted that its overall performance was increased, e.g., u and u obtained from Uniform RVs distributed over the 1 2 a maximum clock frequency of 168 MHz (improvement of interval [0,1], a set of intermediate functions f, g , g such 1 2 300%) when compared to the first implementation approach. that This solution also uses around 0.03 % of the ROM memory. f(u )= ln(u ) (1) 1 − 1 Hence, this approach was chosen as the default implementation p of the GRNG block. g1(u2)= √2sin(2πu2) (2) The data ROM block performs the computation of the g2(u2)= √2cos(2πu2), (3) delta[i] vector of the SRMD algorithm. The data ROM is indexed by i and H and it is defined by and the following x1 and x2 RVs delta[i] 1 iH 1 x = f(u ) g (u ) (4) data ROM[i, H] := = ( ) 1 22H−2. 1 1 1 2 sigma 2 r2 − p (6) x = f(u ) g (u ). (5) 2 1 2 2 It can be seen from Eq. 6, that data ROM[i, H] uses
Then, x1 and x2 are independent Gaussian distributed RVs some complex calculations to compute the delta[i] vector. with zero mean and unit variance. Linear segmentation approx- The power and square-root functions evaluated by LUTs, imation is then applied to determine the f, g1 and g2 functions usually take several clock cycles to be solved. In the proposed of the Box-Muller algorithm. The CLT is used to reduce approach all delta[i] values are stored and addressed by the the nonlinearities of these functions for values close to the i and H indexes. This would be prohibitive due to the large interval limits, i.e., 0 and 1. Thus, improving the representation amount of memory resources needs for storing a wide range of accuracy of the Gaussian RVs. The output of the URNG block delta[i] values. However, H values can be represented with provides both u1 and u2 to obtain the x1 and x2 (Eqs 2 and only 2-digits after the decimal point. Thus, 1,000 H values 3) in only one clock cycle. Look-up tables (LUT) are largely are necessary for each iteration of the SRMD algorithm. Since used to store the linear segmentation outputs of the Box-Muller 0 maxlevel 16, delta[i] vector can have a maximum of ≤ ≤ functions (f, g1 and g2) in a few clock cycles. But, in these so- 16,000 elements. Hence, 1.6% of the ROM memory ressource lutions, large LUTs sizes are required to store all the resulting was needed to store the delta[i] vector. In fact, 1/f noises linear approximation segments of the Box-Muller functions. In have 1/2 TABLE II TABLE IV DEVICE RESOURCES USAGE OF THE 1/f FBM BLOCK DESIGN STATISTICS ESTIMATION:PURE 1/f NOISE PARAMETERS. maxlevel 14 15 16 parameters m σ H Logic elements 1595 (6.1%) 1723 (6.9%) 1848 (7.4%) pure 1/f noise 0.000010 1.00 0.50 RAM memory (bits) 261,144 (13%) 542,288 (27%) 1,048,576 (52%) fBm block (CI 95%) 0.000011 1.00±0.00001 0.51±0.00099 Embedded multipliers 10 10 12 fBm block (CI 99%) 0.000011 1.00±0.00001 0.51±0.00112 Initializing time (cycles) 344064 688128 1376256 Max. Clock Freq. (MHz) 176 173 152 TABLE III i.e., largest 1/f generated noise sequence, the implementation STATISTICS ESTIMATION: factory2 NOISE PARAMETERS. used 7.4% of logic elements, 52% of RAM memory and 1.6% of ROM memory of the FPGA main resources. parameters (frame=16ms) m (bits/frame) σ (bits/frame) H The delta[i] of fBm block solves two power and two factory2 639.50 369.65 0.990 square-root functions (using the LUT method), hence it is fBm block (CI 95%) 642.03±3.432 370.75±5.683 0.989±0.00357 maxlevel fBm block (CI 99%) 638.18±4.747 368.83±6.911 0.987±0.00732 necessary a total of 152 2 clock cycles. Since the SRMD algorithm performs∗ one while and two for loops, the X[i] vector spends an initial output delay tinit. This initial 3) Evaluate delta by multiplying previous data ROM data delay depends on the maxlevel variable and is equal to by sigma; maxlevel maxlevel+2 tinit = (2 1)+(2 + 4) Fill the initial values of the X[i] vector with the com- − puted sigma Gauss values; + maxlevel 2) tgauss ∗ maxlevel− ∗ 5) Perform the loops iterations (one while and two for’s); (1+4 tgauss) 2 [cycles], (7) ≈ ∗ ∗ 6) Update the d, D and level counters; where t is the total clock cycles to generate a Gaussian 7) Read fBm output samples from X[i] vector. gauss sample. However, after this initial time, only one clock cycle The EP1S25 FPGA kit used for the 1/f noise block imple- is needed to read a sample value from the X[i] vector. mentation has approximately 25,000 logic elements, 4 RAM Tables III and IV show the statistics results obtained with blocks of 500 Kbits each, ROM of 1 Mbits, 10 digital signal the 1/f fBm noise samples using the factory2 and the pure- processor (dsp) blocks and 6 phase locked loop (PLL) used for Brownian noises parameters. The m, σ and H results accuracy clock generation. The multstyle attribute was set for using the was obtained considering the t-student method [20] for the dsp blocks. Altera’s Stratix devices have a fixed number of dsp 95% and 99% confidence intervals. Considering n independent blocks which include a fixed number of embedded multipliers. 2 σx experiments it follows that Xˆn = X¯n tn−1,1−α , where The multstyle attribute specifies the implementation style for ± q n multiplication operations (*) in the VHDL source code. It tn is a t-student RV with n 1 degrees of freedom and an exact 100(1 α) percent confidence− interval. These results show also defines if the compiler shall implement a multiplication − operation in general logic or in dedicated hardware. The D/2 that the samples generated by the 1/f fBm blocks achieved and d/2 division operations of the SRMD algorithm were close statistics to real factory2 and the pure-Brownian noises. implemented using shift registers. The scaling degrees accuracy was achieved for both noise generation experiments. Particularly, the H results obtained from the 1/f fBm samples, were very interesting since they in- IV. RESULTS dicate the good representation of the low-frequency (H > 1/2) This section presents the main results obtained from the characteristics of the 1/f noise. evaluation of the proposed 1/f fBm noise generator. For Fig. 2 presents the PDF, HTD and ACF curves obtained 2 the tests it was used the m, σ and H statistics estimated from the fBm noise samples. These plots were evaluated from the real 1/f factory2 acoustic noise. This acoustic noise considering the real factory2 parameters since it is a 1/f noise was sampled at 16kHz and 16 ms frame length considering (H = 0.75). The results obtained from the noise samples Hamming window. Additionally, a pure-Brownian generation generated from the hardware fBm block were compared to the 2 was performed with statistics m = 0, σ = 1 and H = 1/2. referred ideal curve in which the fBm samples were obtained 6 Five independent fBm noise sequences were generated of 10 , from a C++ language implementation of the SRMD algorithm 9 10 11 12 10 , 10 , 10 , 10 bit samples sizes. For the H parameter considering 106 (maxlevel= 16) samples. The PDF plots (Fig. estimation it was used the wavelet-based method [10] with 12 2(a) were evaluated by the approximation of the noise samples Daubechies filters with the 3-12 scale ranges. histograms. Note that the noise samples pattern distribution The main results presented in this section include: obtained from the hardware implementation is quite similar to • Device resources usage; the one obtained from software-based generation. • Estimation of the statistical parameters: m, σ, H; The log-log HTD (P [X > x]) curves were very important • 1/f fBm noise samples representation: PDF, (log-log) to show the tail distribution of the noise samples. For example, HTD and ACF plots. pure-white-Gaussian distributed samples have Exponential de- The device resources usage was evaluated for different caying tails. Differently, 1/f samples with scaling invariance maxlevel values, i.e., the number of increments of the 1/f degrees (H > 1/2) have slow or heavy decaying tail behavior. fBm noise sequence. This report is presented in Tab. II. It can As expected, the generated fBm samples (H 0.75) presented be noted that for the maximum number of SRMD iterations, heavy tails (Fig. 2(b)). ± JOURNAL OF COMMUNICATIONS AND INFORMATION SYSTEMS, VOL. 1, NO. 26, APRIL 2011 17 0.035 0.05 "pdf_1f_fBm_H099_ideal" "htd_1f_fBm_H099_ideal" "pdf_1f_fBm_H099_FPGA" "htd_1f_fBm_H099_FPGA" 0.03 0 0.025 -0.05 0.02 P[X=x] P[X > x] 0.015 -0.1 0.01 -0.15 0.005 0 -0.2 -1500 -1000 -500 0 500 1000 1500 2000 2500 -1 -0.5 0 0.5 1 1.5 2 2.5 3 x x (a) (b) 0.7 "acf_1f_fBm_H099_ideal" "acf_1f_fBm_H099_FPGA" 0.6 0.5 0.4 0.3 ACF 0.2 0.1 0 -0.1 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 lag (c) Fig. 2. 1/f fBm Noise Design Validation Results: (a) PDF, (b) log-log HTD, (c) ACF. From the ACF graphics (Fig.2(c)) it can be inferred that memory and 1.6% of ROM memory. The estimation results they follow a slowly-vanishing function with slow variations showed that 1/f fBm noise generator accurately achieved to infinity (i.e., lag k ). This also demonstrates that the the mean, variance and the low-frequency statistics and the noise samples have S(f→) concentrated ∞ in low-frequency range. noise samples pattern. Moreover, the auto-correlation function of the generated noise samples confirmed the expected V. CONCLUSION slow variations of the real 1/f factory2 acoustic noise. The This paper proposed a fast and accurate hardware design proposed design showed to be very promising to evaluate of 1/f noise generator based on the fractional Brownian the performance of communications channels with very low motion. The noise generator is described for the successive BER values. It can also be interesting for signal processing random addition midpoint displacement method. The solution applications (e.g., noise extraction) that deals with noisy enabled the generation of 150 million of 16-bit noise samples conditions such as automatic speaker recognition [22]. Other per second. The 1/f noise generator achieved for the largest algorithms for the generation of 1/f fBm samples [9] [6] sample size generation 7.4% of logic elements, 52% of RAM and true random number [23] can be considered as future JOURNAL OF COMMUNICATIONS AND INFORMATION SYSTEMS, VOL. 1, NO. 26, APRIL 2011 18 work. The proposed design will also be applied to generate Gustavo Lima Loss received the B.S. and M.Sc. impulsive or alpha-stable noises [24]. degrees in Electrical Engineering from the Insti- tuto Militar de Engenharia (Military Institute of Engineering-IME) of Rio de Janeiro in 2006 and Acknowledgments: This work was partially supported by 2000, respectively. the APQ1/FAPERJ (E26/170.518/2007) and Universal/CNPq In 2006, he joined the Military Material Industry of the Brazilian Army. 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