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Front-End Electronics for Unattended Measurement (FEUM): Prototype Test Plan Revision 1

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Front-End Electronics for Unattended Measurement (FEUM): Prototype Test Plan Revision 1 PNNL-24553 Prepared for the U.S. Department of Energy under Contract DE-AC05-76RL01830 Front-end Electronics for Unattended Measurement (FEUM): Prototype Test Plan Revision 1 RC Conrad SJ Morris LE Smith D Keller August 2015 DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor Battelle Memorial Institute, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government or any agency thereof, or Battelle Memorial Institute. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. PACIFIC NORTHWEST NATIONAL LABORATORY operated by BATTELLE for the UNITED STATES DEPARTMENT OF ENERGY under Contract DE-AC05-76RL01830 Printed in the United States of America Available to DOE and DOE contractors from the Office of Scientific and Technical Information, P.O. Box 62, Oak Ridge, TN 37831-0062; ph: (865) 576-8401 fax: (865) 576-5728 email: [email protected] Available to the public from the National Technical Information Service, U.S. Department of Commerce, 5285 Port Royal Rd., Springfield, VA 22161 ph: (800) 553-6847 fax: (703) 605-6900 email: [email protected] online ordering: http://www.ntis.gov/ordering.htm This document was printed on recycled paper. (9/2003) PNNL-24553 Front-end Electronics for Unattended Measurement (FEUM): Prototype Test Plan RC Conrad SJ Morris LE Smith D Keller August 2015 Prepared for the U.S. Department of Energy under Contract DE-AC05-76RL01830 Pacific Northwest National Laboratory Richland, Washington 99352 Revision Log and Approvals Front-end Electronics for Unattended Measurement (FEUM): Prototype Test Plan Rev. No. Date Describe Changes Pages Changed 0 11/25/14 Original Issue 1 5/20/15 Removed references to use of charge injector – Arbitrary Various Waverform Generator (AWG) to be use instead Removed quantitative aspects of Test 3 (Pulse Shape). Added reference AWG waveforms to Section 3. Removed ground loop noise susceptibility test (Test 22) Various edits for clarity Removed Test 9 (impedance measurements) Performance targets recalculated and updated in section 1.2 Deleted references to performing NGAM verification Added Appendix B (original IAEA specifications for FEUM) in place of original appendix B (Charge Injector Technical Specifications) Updated the digital summing test procedure Removed Test 21, Conducted EMI Susceptibility Name and Title Approvals Date PNNL Page iv of xiv Acronyms and Abbreviations ADAM Advanced Data Acquisition Module from Bot Eng. AWG arbitrary waveform generator CANDU CANada Deuterium Uranium COTS commercial off the shelf CZT cadmium zinc telluride DAQ data acquisition DUT device under test ECP Engineering Change Proposal ESD electrostatic discharge EMI electromagnetic interference FEUM Front-end Electronics for Unattended Measurements GRAND Gamma Ray and Neutron Detector from Canberra Ind. IAEA International Atomic Energy Agency LED light-emitting diode MCA multichannel analyzer NGAM Next Generation ADAM Module NGSI Next Generation Safeguards Initiative RFI radio frequency interference SCA Single channel analyzer TTL transistor-transistor logic UMS Unattended monitoring system(s) UNAP Universal NDA Data Acquisition Platform UNDA Unattended Non-Destructive Assay Page v of xiv Contents Revision Log and Approvals ....................................................................................................................... iv Acronyms and Abbreviations ....................................................................................................................... v Contents ....................................................................................................................................................... vi Figures and Tables ...................................................................................................................................... xii 1.0 Introduction ....................................................................................................................................... 1 1.1 Background ................................................................................................................................... 1 1.2 Test Objectives .............................................................................................................................. 3 2.0 Testing Overview .............................................................................................................................. 5 2.1 Conformance Verifications ........................................................................................................... 5 [TEST 1] Feature Conformance Verification ...................................................................................................... 5 2.2 Functional Tests ............................................................................................................................ 5 2.2.1 Preamplifier ............................................................................................................................................. 6 [TEST 2] Pulse Rise Time ................................................................................................................................... 6 2.2.2 Shaping Amplifier ................................................................................................................................... 6 [TEST 3] Shaping Amplifier – Gain and Charge Calibration .............................................................................. 6 [TEST 4] Analog Shaping Constant ..................................................................................................................... 6 2.2.3 Discriminator ........................................................................................................................................... 6 [TEST 5] Discriminator - Threshold .................................................................................................................... 6 [TEST 6] TTL Pulse Width .................................................................................................................................. 7 2.2.4 High-Voltage Bias Supply ....................................................................................................................... 7 [TEST 7] Bias Supply – Voltage .......................................................................................................................... 7 [TEST 8] Bias Supply - Stability ......................................................................................................................... 7 2.2.5 Interfaces.................................................................................................................................................. 7 [TEST 9] Input/Output Port Resistance ............................................................................................................... 7 [TEST 10] Count-Rate Indicator - LED Pulse ..................................................................................................... 7 [TEST 11] Isolated Input Power .......................................................................................................................... 8 [TEST 12] Digital Input - Logic Voltage Levels ................................................................................................. 8 [TEST 13] Digital Input – Digital Summing ........................................................................................................ 8 [TEST 14] Vcc Grounded Input Power ................................................................................................................ 8 [TEST 15] Analog Output 1 & 2 .......................................................................................................................... 8 [TEST 16] Digital Output- Logic Voltage Levels ................................................................................................ 8 [TEST 17] Ground Isolation ................................................................................................................................ 8 Page vi of xiv 2.2.6 Deadtime and Intrinsic Noise Characteristics .......................................................................................... 9 [TEST 23] Deadtime ............................................................................................................................................ 9 [TEST 24] Equivalent Noise Charge.................................................................................................................... 9 2.2.7 UMS DAQ Standards Compatibility ....................................................................................................... 9 [TEST 18] NGAM Compatibility ........................................................................................................................ 9 Test Removed. This test was a lower priority
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