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Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy

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Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy Trans. Mat. Res. Soc. Japan 38[2] 265-268 (2013) Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy Leonid Bolotov, Tetsuya Tada*, Yukinori Morita*, Vladimir Poborchii* and Toshihiko Kanayama* University of Tsukuba, Tennodai 1-1-1, Tsukuba, Ibaraki 305-8573 Fax: 81-298-53-5341, e-mail: [email protected] *National Inst. of Advanced Industrial Science and Technology, Higashi 1-1-1, Tsukuba, Ibaraki 305-8562 Fax: 81-298-62-7326 Structural and electronic properties of silicon-on-insulator (SOI) nanowires with a cross section area of 2020 nm2 were investigated with high spatial resolution by multimode scanning probe microscopy (MSPM) in the constant force mode. The position-dependent tunneling current was measured in the interior of the Si nanowires whose surfaces were terminated with hydrogen and with ultrathin thermal oxide. The current value and fluctuations were reduced for Si nanowires terminated with an ultrathin oxide layer (~0.3 nm), indicating the homogeneous surface passivation. The tunneling current decreased within a distance of ~300 nm from the Si pad electrode for both types of surface termination. Calculations of the tunneling current were performed based on the macroscopic conduction model including the conductance contributions of the nanowire volume and the surface states. In the model, the bulk carrier concentration and the surface state density were tuned to fit the experimental data for the small Si nanowires. The results support the length-dependent conductance of thin Si nanowires, demonstrating the ability of the technique for characterization of modern silicon-on-insulator devices. Key words: silicon, scanning probe microscopy, nanowire, tunneling current, conductance (about 5 words) 1. INTRODUCTION scanning probe microscopy (M-SPM) system has been Fabrication of modern devices on silicon-on-insulator constructed and evaluated for structural and electronic (SOI) platform presents the challenge to perform characterization silicon-on-insulator (SOI) nanowires high-resolution characterization of semiconductor with high spatial resolution. Improved resolution and structures on non-conductive substrates. Of particular easy navigation to nanowire devices were achieved due attention is the role of surface and interface properties in to integration of STM and AFM operation by the use of carrier transport in advanced Si nanowire (NW) devices. a force sensor consisting of a sharp tungsten probe [1-4] attached to a quartz length extension resonator (qLER) Scanning probe techniques such as scanning cantilever. [11,12] We have already reported on spreading resistance microscopy (SSRM), scanning photocarrent distriution in Si stripes separated by SiO2 Kelvin probe microscopy (SKPM) have been employed films, [13] and the built-in potential mapping of a p-n for two-dimensional (2D) characterization of modern junction under the optimized probe-sample gap. [14] devices. However, high load from the SSRM probe and Here, we demonstrate high-resolution characterization of the series resistance have become the limitation for small SOI nanowires by using M-SPM. quantitative characterization of nanowire devices smaller than 50 nm. [5] In the conventional SKPM 2. EXPERIMENTAL TECHNIQUES technique long-range electrostatic force acting on the 2.1 Sample preparation probe results in the measured potential averaged over Silicon nanowires (NWs) with a cross-sectional extended area beneath the probe, thus, the spatial area of 2020 nm2 were defined in an undoped SOI resolution is insufficient for measurements of nanoscale wafer using e-beam lithography. For the measurements patterns. [6,7] Alternatively, high-resolution carrier NW surfaces were either hydrogen-terminated by profiling of metal-oxide-semiconductor field effect etching in 1%-HF solution or passivated by ultra-thin transistor (MOSFET) has been demonstrated by thermal oxide. [10] The hydrogen-terminated silicon employing scanning tunneling microscopy and surfaces with atomically smooth morphology were spectroscopy (STM/STS). [8-10] While atomic obtained by a two-step treatment consisting of a dip in resolution is attainable, the STM technique requires diluted (~1%) fluoric acid for 30 s following boiling in a conductive samples. Therefore, the characterization of mixture of sulphuric acid and peroxide (3:1) for 10 min. nanoscale structures has remained the important The passivation with ultrathin oxide was obtained by challenge. thermal oxidation of the H-terminated Si surface at o -3 To overcome the difficulty, an integrated multimode 600 C and an O2 pressure of 10 Pa for 30 min. [10] 265 266 Nanoscale Characterization of Silicon-On-Insulator Nanowires by Multimode Scanning Probe Microscopy Fig. 2. AFM topograph (a) and current map (b) of a H-terminated NW taken at VS = -1.5 V. Broken line in (a) indicates the SOI edge. White triangle marks a surface contamination. The gray scale is 3 nm in (a) and 80 pA in (b). beneath the probe tip. Amount of supplied carrier at the probe position is obtained from the conductance of the NW including the bulk and surface contributions as 1 a 2 G NW surface qG ef N 0 s SS ANq S , )1( Fig. 1. (a) Experimental setup for tunneling NW xR )( x current measurements along a SOI NW (top). The 2 electric circuit diagram, RNW and Rtun are where a is the NW cross section, AS is the surface resistances of the NW and the tunneling gap, collection area, q is the elementary charge, are ef , s respectively. (b) SEM image of measured the effective mobility of carriers in Si bulk and the structure. surface, respectively. N0 and NSS are densities of the NW bulk carriers and the surface states, respectively. The Additionally, annealing in a mixture of H2 (5%) and N2 quantity in brackets in Eq. 1 is an effective carrier o gases was performed at 450 C for 30 min to reduce the concentration. residual density of surface states on Si/SiO2 surface. The tunneling resistance (Rtun) is related to the quantum mechanical tunneling probability, i.e. the 2.2 Tunneling current maps tunneling factor. For a rectangular potential barrier, it is Measurements were performed in a non-contact approximated by an exponential function atomic force mode with a metallic probe tip attached to a Vgap d qLER cantilever. In the mode, the tip-surface distance tun eT ; with b BH , )2( was kept constant by maintaining the force acting on the 2 metal probe tip in the repulsive regime. To control the where d is a width of the tunneling gap, Vgap is the tip-surface interaction force, we used the shift in the potential across the gap, BH is the effective potential resonance frequency (f) of the qLER which vibrated at barrier in the gap, and b is the constant. ~1 MHz (Q factor ~45 000) with an amplitude of 0.1 nm. In metal-insulator-semiconductor structures,[17] the [11,12,15] In our setup, the tip-surface distance (the potential across the gap is defined by the strength of electric field in Si at the probe position ( ). Using the tunneling barrier) was ~0.5 nm on H-terminated Si surfaces.[16] When a bias voltage (VS) was applied continuity of electric displacement across the between the probe and the Si pad, mean tunneling silicon/vacuum interface, the gap potential is expressed current was recorded at each position of the probe tip. as [Fig.1] All measurements were performed in dark at d VV dV Si Q , )3( room temperature in an ultra-high vacuum chamber (a gap S NW Si SS residual pressure of ~1.410-7 Pa). 0 0 where VS is the applied voltage, VNW is the potential across the NW, and are the permittivity of 2.3 Tunneling current calculation model 0 , Si Calculations of the tunneling current were performed vacuum and the dielectric constant of silicon, considering resistances of the tunneling barrier and the respectively. According to the Gauss’s law the charge NW volume connected in series as shown in Fig.1. In per unit area in Si (QSS) at the probe position determines our calculations, we assumed that (1) the position the electric field in the gap. Therefore, decrease of the dependence of the tunneling current is given mainly by effective carrier concentration in the collection volume the NW conductance; (2) the measured current is results in decrease in the potential across the gap. Under defined as a product of the tunneling factor and total the steady-state conditions, the potential distribution in amount of carriers supplied within the tip-induced band the NW can be obtained from the solution of the Poisson bending (TIBB) region in Si (the collection volume) equation at each probe position.[17] Here, we assume L. Bolotov et al. Trans. Mat. Res. Soc. Japan 38[2] 265-268 (2013) 267 Table 1. Parameters used in the calculations of tunneling current profiles of 2020nm2 SOI NWs. parameter H-terminated Ultrathin Oxide d (nm) 0.6 0.9 3 14 14 N0 (1/cm ) 1.310 1.510 N SS 7.5107 6106 (1/cm2) The measured current value was about 40 pA in the Si pad, and gradually decreases to 3 pA in the NW interior. The position-dependence of the current indicates the decrease in the NW conductivity with its length. When the conductivity decreases, the amount of supplied carriers reduces, resulting in the small tunneling current. One characteristic feature in the measurements of tall structures such as nanowires is large current seen at the NW edges in Fig.2 (b). When the side of the elevated Si NW is in contact with the side of the metallic probe, the tunneling current steeply rises. Such scanning artifacts can easily be identified by its position beyond the structure edges and discarded. [13] The observations Fig. 3. Line profiles of measured (solid lines) demonstrate superior sensitivity of the technique to and calculated (symbols) tunneling currents along structural and chemical inhomogeneity.
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