<<

1

Defects and Disorders in

Jermell Powell, Electrical and Computer Engineering

position, and interstitials, in which an is located in Abstract— Various defects and disorders in between lattice sites. Also, when dealing with doping or semiconductors will be described, along with their causes fabrication, one can encounter impurities. These which and consequences. Determination and classification of are different than the original material may be substitutional defects will follow. Many defects are general; however, defects, when they replace an intended atom at a lattice specific materials will be examined. position, or interstitial impurities [4]. Figure 1 provides examples for four of the previously stated defects. Index Terms — Defect Density, Point defects, Vacancy, Silicon

I. INTRODUCTION HERE is an abundance of previous research that has Tdetermined and categorized defects. The simplified case is to assume that defects occur randomly over a silicon slice. Further in-depth analysis has shown that this simplification is not realistic, however [1]. Most faults have been shown to lie at the material’s edge, due to thermal and mechanical stress. And while classically, fault densities were considered with respect to radial variation, further attention has been given to angular deviation. Both variations have been studied for analysis of defect phenomena, including defect clusters and slip lines. Fig 1. Common point defects in semiconductors. Substitutional and interstitial defects involve a separate II. DEFECT TYPES ion, whereas self interstitials are due to an original atom. The categories of defective circuits are as follows: A) Local faults initially in the material; Area defects are thought of as extended point defects, B) Local faults created during fabrication; particularly epitaxial mounds. As such, they are modeled with C) Broad faults initially in the material; both a radial and angular property about the slice. The D) Broad faults created during fabrication. angular property comes about usually during the high The effect of faults are denoted either as catastrophic, when temperature activity phases. This may include gas flow the circuit is completely inoperable; or degraded, where the variation, slice insertion, or placement techniques [1]. circuit is marginally inoperable. However, all defects do not There are also impurities that may be formed from what is cause operational faults [1]. In fact, some defects are intended known as an octahedral void defect. During oxidation, these or expected, during the doping process. For example, carbon impurities may affect the gate-oxide, forming a conductive had previously been found in many defects observed in silicon path within it. As such, a reduction in the gate oxide integrity semiconductors [2], and a common modern semiconductor can occur, including a dielectric breakdown [5]. These material is silicon carbide (SiC). Therefore, the chip area is impurities are called grown-in defects. Vacancies are a multiplied by a constant, always less than unity, which defines common grown-in defect, usually appearing when oxidation the active chip area. This area is susceptible to inoperability temperatures reach 1070-1100ºC [6]. due to defects [1]. However, defects originally created near Epitaxial mounds become an issue when the imperfection is the surface may be repositioned or fixed, due to wafer observed on the photomask, and propagates throughout many processes like polishing, oxidation, and chemical etching [3]. of the silicon slices. Although one solution may involve non- The local faults can be categorized into: point defects, area contact processes, more careful photoetching management has defects, lines, and clusters. Examples of point defects include also led to the reduction of this area defect [7]. pinholes, imbedded grains, and [1]. Especially Line faults are mainly denoted in the following categories: common are vacancies of an atom from a particular lattice A) Slip lines due to chipped edges of the slice, in a high temperature phase;

2

B) Slip lines from thermal gradients at the slice edge via IV. DIVACANCY direct contact; Up until this point, we described a basic vacancy defect, C) Stacking fault defects in the epitaxial layer; where a thermal reaction or ion implantation removed a host D) Line defects from thermal oxidation; atom from its lattice position. However, there is another E) Slip lines from uneven heating and pressure; rather common reaction to irradiation which is known as a F) Scratching. divacancy. In this case, two adjacent atoms have been Finally, a defect cluster can be attributed to a dust particle, removed from their lattice positions. or a scratch on the mask, perpetuating to multiple slices [1]. There are five general reactions in the event of a divacancy. Above a threshold temperature, [8] shows the formation of The first two are consequences of a divacancy and one defect clusters in addition to point defects on silicon. interstitial. If the interstitial combines with the divacancy, then the semiconductor ultimately has a single vacancy. If the interstitial instead escapes, then the divacancy is considered III. DEFECT DENSITY non-reorientable, and the interstitial is free. Defect density has been modeled and represented by an When considering the case of a divacancy and two empirical equation. The following equation is dependent on interstitials, those interstitials may escape a bond. In this case, the radial variation: no change will occur. If one of the interstitials combines with the divacancy, then the net effect is one vacancy and a free- d(r) = d{l + 2.5 exp [0.34 X 19(1 - r/R)]} (1) roaming interstitial. However, if both interstitials combine with the divacancy, then the semiconductor will appear to be

correct [10]. Here, d(r) is the density at point r, d is a constant, and R is the radius of the slice. The equation infers that the defect V. MATERIAL density will increase at points near the edge of the wafer. This effect can be seen in Fig. 2 [1]. The graph models a relative Although certainly not exclusive, silicon is currently the ratio, but research has shown defect densities(d) to take values most popular material used in semiconductor devices. The of 104-107 cm-3 [3] [9]. research in [11] shows that the electrical deactivation of arsenic in silicon can create silicon self-interstitials. Other defects can arise due to one of the major growth processes, accredited to Jan Czochralski (see Figure 3). During the formation of Czochralski silicon, it may dissolve the supporting cubicle made of quartz, and the result can lead to trace amounts of oxygen. This oxygen is then dispersed throughout the silicon.

Fig. 3. Czochralski process for silicon wafers. A pure The angular defect density resembles a sine wave, peaking silicon seed is placed into a SiO2 melt, and slowly pulled out at an angle of 180 degrees. This corresponds to the line at while rotated. The result is a pure silicon cylinder, or an which the slice occurs. Research in [1] classified defect ingot. density analysis into three cases: normal radial and angular defects; line defects compounded with the basic faults; and a Oxygen in silicon has situational benefits. There are some cluster of defects at a random point, graphically denoted by a semiconductor devices which require high carrier lifetimes, spike. Defects that demonstrate a large electron-lattice diffusion lengths, and mobilities. Some solar cells and coupling may affect the host’s , depending integrated circuits are therefore produced with oxygen on the lattice relaxations near the defect [2]. concentrations below 30 PPMA. However, other devices require pure silicon, so oxygen would prove to be as detrimental a defect as any other foreign element. These specific types of photodiodes and “high- 3 efficiency” solar cells use silicon created by the Float Zone [Online] 53(2). Available: http://ieeexplore.ieee.org/iel5/23/33963/ process. This process heats polycrystalline ingots, and then 01621369.pdf?tp=&arnumber=1621369&isnumber=33963 [9] T. Mera, J. Jablonski, M. Danbata, K. Nagai, M. Watanabe, “Structure of re-freezes them into single silicon [12]. the Defects Responsible for B-mode Breakdown of Gate Oxide Grown In observing the stoichiometric, or chemically balanced on the Surface of Silicon Wafers,” in Defects in Electronic Materials II, formation of, ZnTe and CdTe semiconductors, chlorine was Boston, 1997, pp. 107-112. added as a dopant. In both cases, the Cl doping forms an [10] R. D. Harris and G. D. Watkins, “Interstitial Related Defects in n-type Silicon,” in 13th Int. Conf. on Defects in Semiconductors, Coronado, CA, excess of Te, leading to low p-type resistivity. The study also 1984, pp. 799-805. showed that copper dopant can increase the p-type resistivity [11] O. Dokumaci, H. J. Gossman, K.S. Jones, M. E. Law, “An Investigation in a CdTe sample [13]. of Vacancy Population During Arsenic Activiation in Silicon,” in Another popular material used for semiconductors is Defects in Electronic Materials II, Boston, 1997, pp. 151-156. [12] Oxygen Precipitation in Silicon. Virginia Semiconductor, Inc. [online] Gallium-Arsenide (GaAs). Depending on the function and/or Available: http://www.virginiasemi.com/pdf/Oxygen%20Precipitation process, the material can be Ga-heavy, or As-rich. However, %20in%20Silicon_finished.pdf a common defect known as an antisite occurs when an [13] V. Valdna, “Complex defects in Cl doped ZnTe and CdTe,” in Defects Arsenide atom appears at a Gallium location, or vice versa. in Electronic Materials II, Boston, 1997, pp. 585-591. [14] J. Lagowski, H. Gates, “Nonstoichiometric defect in GaAs and the EL2 Incorrect distribution of chemical compounds can lead to bandwagon,” in 13th Int. Conf. on Defects in Semiconductors, Coronado, nonstoichiometric defects. However it has been shown that a CA, 1984, pp. 73-85. GaAs melt that favors Arsenic can demonstrate a beneficial affect: a compensation mechanism, attributed to a prevalent semi-insulating property [14].

VI. CONCLUSION Various defects in a semiconductor device have been presented, determined, and categorized. Equations and graphs are shown that were empirically created by past research to show defect distribution. It has been shown that defects are based on both radial and angular variation. Additionally, Carbon may be directly incorporated in most silicon defects, Classical and contemporary defect issues have been described, ignoring their current effect or proposed remedies. Interestingly though, the added focus in angular variation, per [1], can result in a better production yield by a factor of five in large chip sizes.

REFERENCES [1] A Gupta, W. A. Porter, and J. W. Lathrop. (1974, June) “Defect Analysis and Yield Degradation of Integrated Circuits.” IEEE Journal of Solid-State Circuits. [Online] 9(3). Available: http://ieeexplore.ieee. org/iel5/4/22536/01050475.pdf?tp=&arnumber=1050475&isnumber=22 536 [2] G. D. Watkins, “Defect structures and reactions,” in 13th Int. Conf. on Defects in Semiconductors, Coronado, CA, 1984, pp. 11-15. [3] M. Kato, H. Takeno, Y. Kitogawara, “TEM Observation of Grown-in Defects in Cz-Si and their Secco Etching Properties,” in Defects in Electronic Materials II, Boston, 1997, pp. 119-130. [4] D. A. Neamen, Semiconductor Physics and Devices. Boston: McGraw- Hill, 2003, pp. 14-15. [5] M. Itsumi, “Octahedral Void Defects Causing Gate Oxide Defects in MOSLSIs,” in Defects in Electronic Materials II, Boston, 1997, pp. 95- 106. [6] K. Nakal, M. Hasebe, T. Iwasaki, and Y. Tsumari, “Characterization of Grown-in Defects In CZ-Si crystals by Bright Field IR Laser Interferometer,” in Defects in Electronic Materials II, Boston, 1997, pp. 119-130. [7] T. Yanagawa. (1969, September). Influence of Epitaxial Mounds on the Yield of Integrated Circuits. Proceedings of the IEEE. [Online] 57(9). Available: http://ieeexplore.ieee.org/iel5/5/31124/01449276.pdf? tp=&arnumber=1449276&isnumber=31124 [8] M. Scaringella, D. Menichelli, A. Candelori, R. Rando, and M. Bruzzi. (2006, April) Defect Characterization in Silicon Particle Detectors Irradiated With Li Ions. IEEE Transactions on Nuclear Science.