Ultra Thin Ultrafine-Pitch Chip-Package Interconnections For
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ULTRA THIN ULTRAFINE-PITCH CHIP-PACKAGE INTERCONNECTIONS FOR EMBEDDED CHIP LAST APPROACH A Thesis Presented to The Academic faculty By GAURAV MEHROTRA In Partial Fulfillment Of the Requirements for the Degree Master of Science in Materials Science and Engineering Georgia Institute of Technology March 2008 ULTRA THIN ULTRAFINE-PITCH CHIP-PACKAGE INTERCONNECTIONS FOR EMBEDDED CHIP LAST APPROACH Approved by: Prof. Rao R. Tummala, Advisor School of Materials Science and Engineering Georgia Institute of Technology Dr. P. M. Raj School of Mechanical Engineering Georgia Institute of Technology Dr. Jack Moon School of Materials Science and Engineering Georgia Institute of Technology Date Approved: March 6, 2008 ACKNOWLEDGMENT Many a wise men (and women) have said that there is no end to what one can accomplish if one doesn’t care who gets the credit. This thesis is to my credit but it wouldn’t have been possible without people around me who believed in this ideology. This thesis was accomplished with the support of many people who surrounded me and I would like to acknowledge their support, comments, discussions, time and energy. My special thanks are due: • To my advisor, Prof. Rao R Tummala, who always set high goals for me and continuously inspired and encouraged me to achieve them. His insight and long- term vision have helped make my work a part of a much bigger effort. Working for him has been a truly wonderful experience. • To Drs. P M Raj and Jack Moon for their commitment to serve on my masters thesis committee; Dr. P M Raj also for his guidance and support throughout this work. • To all the wonderful students and research engineers I had the opportunity to work with and who have made countless contributions to this work, especially Dr. M J Yim for numerous discussions on nano-adhesive materials and help with the assembly process, Dr. Jack Moon for valuable discussions on adhesive materials, reliability and failure analysis towards the later part of this work, Nitesh for helping with the measurements and for countless discussions on assembly and iii reliability, Pradeep for discussions on electroplating, Venky Sundaram and Tapobrata Bandyopadyay for helping with the mask designs, and Dr. Mahadevan Iyer for discussions early on in this work. • To all my friends in the PRC; Aditya, Dhanya, Ganesh, Gopal, Jin Liu, Nithya,and Tapobrata. • To the administrative staff in the PRC and MSE for saving me huge hassles and immeasurable time; especially Susan Bowman, Traci Walden, Christine Baker, Lauren Hall, and Tina Turner. My heartfelt thanks go to a few friends who would probably want to remain unnamed; who have stood by me and helped keep my spirits high in my worst days; who I have shared memorable moments with; and who have made immeasurable indirect contributions to this work and more. Most importantly, my endless thanks are due to my family; to my younger brother, Gautam, for his great understanding, love and support; and to my parents for being the reason I am what I am today; for making me want to study and excel; for their sacrifices, love, and support for which I will be eternally indebted to them. iv TABLE OF CONTENTS ACKNOWLEDGMENT....................................................................................................iii LIST OF TABLES............................................................................................................ vii LIST OF FIGURES .........................................................................................................viii SUMMARY....................................................................................................................... xi 1. INTRODUCTION .................................................................................................... 13 1.1 Major enablers for SoP ..................................................................................... 16 1.1.1 High density substrate wiring ................................................................... 16 1.1.2 Embedded Actives .................................................................................... 17 1.1.3 Ultrafine pitch chip-package interconnection........................................... 19 1.2 Current Approaches for Device-Package Interconnections.............................. 23 1.2.1 Ultra-fine pitch wire bonding.................................................................... 24 1.2.2 Flip-chip Solder Bumping......................................................................... 25 1.2.3 Compliant Interconnects........................................................................... 25 1.2.4 Stud Bumping ........................................................................................... 25 1.2.5 Underfills .................................................................................................. 26 1.3 Copper interconnect proposal for chip-last and 3D packaging technologies ... 27 1.4 Objective and organization of thesis................................................................. 29 2. LITERATURE REVIEW ......................................................................................... 33 2.1 Long Term R&D challenges from Roadmaps .................................................. 33 2.2 Fine Pitch Interconnection Trends and Challenges .......................................... 36 2.3 Traditional interconnection approaches, limitations and the need for copper- based interconnections.................................................................................................. 39 2.3.1 Eutectic Sn/Pb Fine-Pitch Solder bumping at 50 micron Pitch................ 39 2.3.2 Stress-relief with solders........................................................................... 42 2.3.3 Micro C-4 Interconnections...................................................................... 43 2.3.4 Ultra-thin Soldered Flip Chip Interconnections on Flexible Substrates... 44 2.3.5 3D Embedded Components in Organic Packages .................................... 45 2.4 Limitations of Solders and the Need for Novel Interconnection Materials...... 46 2.5 State of the art Copper pillar/post/bump technology ........................................ 52 2.5.1 Spin-on Photoresist Process...................................................................... 57 2.5.2 Dry film Process ....................................................................................... 60 2.6 Emerging direct metal-metal bonding trends.................................................... 62 2.6.1 Transient Liquid Phase bonding ............................................................... 62 2.6.2 Cu-Cu Thermocompression bonding........................................................ 64 2.6.3 Surface-Activated Bonding....................................................................... 65 2.7 Conductive adhesives for fine pitch interconnections ...................................... 67 3. 30µm Pitch Chip and Substrate Layout.................................................................... 72 3.1 Chip Layout ...................................................................................................... 72 v 3.2 Substrate Layout ............................................................................................... 76 4. EXPERIMENTAL PROCEDURES - ADVANCED FABRICATION AND PROCESSING TECHNIQUES........................................................................................ 78 4.1 Fabrication of electroplated Copper bumps at 30 micron pitch........................ 78 4.1.1 Wafer Oxidation........................................................................................ 81 4.1.2 Die Pad Deposition................................................................................... 81 4.1.3 Electroplating Seed Layer Deposition...................................................... 83 4.1.4 Photoresist processing............................................................................... 84 4.1.5 Electrolytic plating of fine-grained copper............................................... 87 4.1.6 Gold protection evaporation and lift-off................................................... 88 4.1.7 Photoresist release and seed layer etch..................................................... 88 4.2 Electrolytic plating of fine-grained copper....................................................... 89 4.3 Glass substrate fabrication................................................................................ 94 5. RESULTS AND DISCUSSION............................................................................... 98 5.1 Fabrication of copper interconnections at 30 micron pitch .............................. 98 5.2 Fabrication of glass substrate at 30 micron pitch............................................ 104 5.3 Assembly processes using advanced adhesives.............................................. 106 5.4 Assembly process optimization at 30 micron pitch ........................................ 110 5.5 Insulation resistance comparison of n-ACF and NCF at 30 micron pitch...... 118 5.6 Reliability evaluation of 30 micron pitch copper bump with advanced adhesives 119 5.6.1 Reliability of 30 micron pitch Copper bump in HTS ............................. 121 5.6.2 Reliability of 30 micron pitch Copper bump in HAST........................... 122 6. CONCLUSIONS AND OPPORTUNITIES FOR FUTURE WORK .................... 127 6.1 Conclusions..................................................................................................... 127 6.2 Future