Graphene Nanoribbon Fets: Technology Exploration for Performance and Reliability Mihir R

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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 727 Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability Mihir R. Choudhury, Student Member, IEEE, Youngki Yoon, Member, IEEE,JingGuo, Member, IEEE, and Kartik Mohanram, Member, IEEE

Abstract—Graphene nanoribbon FETs (GNRFETs) are promis- Although 2-D graphene is a zero band-gap semi-metal, ing devices for beyond-CMOS nanoelectronics due to their a band-gap opens when a FET channel is fabricated on a excellent carrier-transport properties and potential for large- nanometer-wide graphene nanoribbon (GNR) [6]–[9]. In gen- scale processing and fabrication. This paper combines atomistic quantum-transport modeling with circuit simulation to perform eral, the band-gap of a GNR is inversely proportional to its width, technology exploration for GNRFET circuits. Results indicate that and width confinement down to the sub-10-nm scale is essen- GNRFETs offer significant gains over scaled CMOS at the 22-, 32-, tial to open a band-gap that is sufficient for room temperature and 45-nm nodes, with over 26–144× improvement in the energy- transistor operation. Unlike CNTs, which are mixtures of metal- delay product at comparable operating points. A quantitative study lic and semiconducting materials, recent samples of chemically of the effects of variations and defects on the performance and reliability of GNRFET circuits is also presented. Simulation results derived sub-10-nm GNRs have exhibited all semiconducting indicate that whereas GNRFET circuits promise higher perfor- behavior [9], generating considerable excitement for transistor mance, lower energy consumption, and comparable reliability at applications. The two main types of GNRs, with the edges of the similar operating points to scaled CMOS circuits, they are more ribbons assumed passivated by hydrogen atoms, are armchair- susceptible to variations and defects. These results motivate signif- edge and zigzag-edge GNRs (AGNRs and ZGNRs). ZGNRs icant engineering, modeling, and simulation challenges facing the device and computer-aided design (CAD) communities involved in are predicted to be metallic by a simple tight-binding model, graphene electronics research. but a band-gap exists in more advanced, spin-unrestricted simulations [10]. For digital circuits applications, the focus has been Index Terms—Circuit design, defects, energy, energy-delay product, field-effect transistor, graphene, inverter, latch, nanorib- on using AGNRs as the channel material. AGNRs have an elec- bons, performance, quantum transport, reliability, ring oscillator, tronic structure that is closely related to that of zigzag CNTs. variability. The band-gap in AGNRs originates from quantum confinement, and edge effects play a critical role [10]. I. INTRODUCTION This paper first provides an overview of Schottky barrier (SB) RAPHENE, which is a monolayer of carbon atoms GNRFETs with intrinsic AGNR channels (GNRFETs hence- G packed into a 2-D honeycomb lattice, has emerged as a forth, unless specified otherwise). Unlike traditional MOSFETs, promising candidate material for beyond-CMOS nanoelectron- SBFETs use metal or metal silicide contacts at the source and ics. Graphene-based devices offer high mobility for ballistic drain ends, leading to the formation of SBs at these contacts. transport, high carrier velocity for fast switching, monolayer In SBFETs, the gate modulates the quantum tunneling current thin body for optimum electrostatic scaling, and excellent ther- through the SB [11]. Recently fabricated GNRFETs with chan- mal conductivity [1]–[6]. The potential to produce wafer-scale nel lengths of the order of 200 nm delivered about 21% of the graphene films with full planar processing for devices promises ballistic current at VD = 1 V, and about 4.5% of the ballistic high integration potential with conventional CMOS fabrication current at low VD < 0.1 V [12]. Clearly, these are prelimi- processes, which is a significant advantage over carbon nan- nary devices, and it would be natural to expect further advances otubes (CNTs) [6]. such as the integration of ultrathin high-κ dielectrics [13] and aggressive channel length scaling to move the performance of these devices closer to the ballistic limit, with switching speeds, Manuscript received October 18, 2009; revised June 2, 2010; accepted July ION/IOFF, and sub-threshold slope that is competitive with 19, 2010. Date of publication September 9, 2010; date of current version July scaled CMOS. 8, 2011. This work was supported in part by the National Science Foundation under Grant CCF-0916636 and Grant CCF-0916683, and in part by the Office Although most discussions in this paper focus on SB-type of Naval Research. The review of this paper was arranged by Associate Editor GNRFETs [14], [15], simulation studies of MOSFET-type R. Lake. GNRFETs with doped reservoirs have also been reported in M. R. Choudhury and K. Mohanram are with the Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA (e-mail: [16]–[18]. In [19] and [20], SB-type GNRFETs were also com- [email protected]; [email protected]). pared to MOSFET-type GNRFETs. There is consensus that Y. Yoon was with the Department of Electrical and Computer Engineering, in ideal devices, MOSFET-type GNRFETs show better de- University of Florida, Gainesville, FL 32611 USA. He is now with the University of California, Berkeley, CA 94720 USA (e-mail: ykyoon@ufl.edu). vice characteristics over SB-type GNRFETs: larger maximum J. Guo is with the Department of Electrical and Computer Engineering, achievable ION/IOFF, larger ION, larger transconductance, and University of Florida, Gainesville, FL 32611 USA (e-mail: guoj@ufl.edu). better saturation behavior. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Further, this paper presents extensive results on technology Digital Object Identifier 10.1109/TNANO.2010.2073718 exploration for GNRFET circuits. It couples atomistic quantum-

1536-125X/$26.00 © 2010 IEEE 728 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 transport modeling in intrinsic GNRFETs with a circuit simulator that includes parasitics and nonidealities that are necessary to capture extrinsic effects in fabricated GNRFETs. At the device level, GNRFETs are simulated by self-consistently solving an atomistic quantum transport equation based on the nonequilibrium Green’s function (NEGF) formalism with the 3-D Poisson’s equation. These rigorous simulations provide I– V and Q–V data for intrinsic GNRFETs, which are integrated Fig. 1. NEGF formalism for a generic transistor. into a circuit-level simulation framework based on lookup tables for technology exploration of GNRFET circuits. The simulator This paper is an extended version of [21] and is organized is used to study the delay, power, energy, and noise margins of as follows. Section II provides a background in quantum simu- representative GNRFET circuits including inverters, ring oscil- lation of intrinsic GNRFETs. Section III describes technology lators, and latches. Results indicate that GNRFETs offer signif- exploration for GNRFET circuits based on a large-signal circuit icant gains over scaled CMOS at the 22-, 32-, and 45-nm nodes, model for extrinsic GNRFETs. Sections IV and V discuss how with over 26–144× improvement in the energy-delay product variations and defects impact the performance and reliability of (EDP) at comparable operating points. GNRFET circuits. Section VI is a conclusion. Significant technical challenges, however, remain to be met. Due to the atomically thin and nanometer-wide geometries of II. SIMULATION OF INTRINSIC GNRFETS GNRs, variability and defects are projected to have a larger impact on circuit performance and reliability in comparison As devices scale with technology, a powerful quantum trans- to conventional silicon devices. The framework is extended to port simulation framework based on the NEGF formalism pro- perform a quantitative study of the effects of variations and vides an ideal approach for bottom-up device modeling and defects in intrinsic GNRFETs on the performance and reliabil- simulation [22] for the following reasons: 1) atomistic descrip- ity of GNRFET circuits. Independent variations in GNR width, tions of devices can be readily implemented; 2) open boundaries which is the most common source of variation, and independent can be rigorously treated; and 3) multiphenomena (e.g., inelastic charge impurities in the gate oxide, which is the most com- scattering and light emission) can be modeled. mon source of defects, are considered in this paper. Variation Fig. 1 summarizes the procedure to apply the NEGF approach in GNR width affects GNRFET ION/IOFF nonlinearly, which to a generic transistor. The transistor channel, which can be a in turn impacts circuit performance, power, and noise margins. piece of silicon, a GNR, a nanowire, or a single molecule, is Simulation results indicate that variation in GNR width can in- connected to the source and drain contacts. The gate modulates crease the delay, static power, and dynamic power of inverters the conductance of the channel. One first identifies a suitable by 6%–77%, 313%–643%, and 37%–215%, respectively, while basis set and derives the Hamiltonian matrix H for the isolated reducing the noise margin by 27%–80%. Charge impurities af- channel. Then, the self-energy matrices Σ1 , Σ2 , and ΣS , which fect intrinsic GNRFET characteristics nonlinearly and in an describe how the channel couples to the source contact, the asymmetric manner, depending upon the polarity of the charge. drain contact, and the dissipative processes, respectively, are Simulation results indicate that charge impurities can increase computed. Then, the retarded Green’s function, including self- the delay, static power, and dynamic power of inverters by 8%– consistent electrostatic potential U, is computed as 92%, 11%–37%, and 5%–19%, respectively, while reducing the − Gr(E)=[(E + i0+ )I−H−U−Σ − Σ − Σ ] 1 . (1) noise margin by 14%–40%. When simultaneous variations in 1 2 S width and charge impurities are considered, variations in width Finally, the physical quantities of interest, such as the charge dominate, though the effects are exacerbated by the presence of density and current, are computed from the Green’s function. charge impurities. In this paper, the DC characteristics of ballistic GNRFETs are Latch noise margins and static power also exhibit significant simulated by solving the open-boundary Schrodinger¨ equation sensitivity to variations and defects, with near-zero noise mar- using the NEGF formalism in the atomistic pz orbital basis set gins and over 5× increase in static power in the worst case. self-consistently with Poisson’s equation. Ballistic transport (no Low noise margins may result in higher error rates than scaled scattering) is assumed, which sets ΣS =0in (1). The superior CMOS, though the redundancy required for error detection and carrier transport properties of graphene [23] promises ballistic correction as well as the high static power may be offset by the transport for a nanoscale channel. The simulation results es- advantages of high density and low power that GNRFETs offer tablish the device performance at the ballistic limit. Whereas over scaled CMOS. further work is needed to compare theory with experiment as In summary, results show that graphene-based electronics has more data for GNRFETs becomes available, it has been demon- the potential for smaller, faster, and lower energy switches than strated previously that a CNTFET with a 50-nm-long channel scaled CMOS. The results also motivate significant engineer- delivers a near ballistic DC current [24]. ing, modeling, and simulation challenges facing the device and An ab initio treatment of the metal contacts is not practical computer-aided design (CAD) communities to make the perfor efficient device simulation; therefore, a phenomenological formance and reliability of GNRFETs suitable for large-scale treatment of the metal-semiconductor contacts has been used in integration. this study. The model, which has been used to simulate the metal- CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 729

Fig. 2. (a) I–V characteristics and (b) VT extraction at low VD for ideal N =12GNRFETs.

CNT [25] and the metal-GNR contacts [26] earlier, describes operates as a SBFET. The threshold voltage VT of the GNRFET the metal-semiconductor contacts by two input parameters. The is obtained using traditional VT extraction methods for MOS first parameter is the SB height, which determines the band devices from the I–V data [31]. When a low drain voltage VDS discontinuity at the metal-semiconductor interface. The second is applied to an n-type GNRFET, the slope of the I–V curve at a parameter is the density of the metal-induced gap states, which high gate voltage is said to intersect the VG axis at the threshold determines the surface Green’s function of the metal contact. voltage VT . This is illustrated for the I–V curve in Fig. 2(b), The model treats the contact at the level of the Tersoff theory for where the VT is approximately 0.3 V. The leakage current at metal-semiconductor contacts [27], [28], and has been validated VG =0is large, but the threshold voltage of the FET can be by experiments for metal-CNT contacts [24]. For a detailed tuned by engineering the gate metal material to shift the I–V derivation, see [29]. curves along the x-axis, thereby moving the point with minimum Since the electric field varies in all dimensions for the sim- leakage current to VG =0[32]. Note that when the offset is ulated device structure, the 3-D Poisson’s equation is used and applied to achieve minimum leakage, VT changes by an amount numerically solved using the finite-element method (FEM). The equal to the offset, illustrated by the I–V curve for an offset FEM is efficient to treat a device with multiple gates because of 0.2 V and a VT of approximately 0.1 V in the same figure. it can easily handle an arbitrary grid for complex geometry. Finally, both n-type and p-type FETs can be achieved on the A pz orbital coupling parameter of 2.7 eV is used and the same GNRFET due to the ambipolar I–V characteristics. This tight-binding model [10] is used for band-gap calculations. The has already been experimentally demonstrated in the context of simulations in this paper consider a 15-nm-long AGNR as the CNTFETs [32], which exhibit ambipolar I–V characteristics channel material, and the GNR width is varied from N =9to qualitatively similar to GNRFETs. N =18, where N denotes GNR index [30]. Double gate geometry is implemented through a 1.5-nm-thick SiO2 gate insulator III. SIMULATION OF GNRFET CIRCUITS (r = 3.9). The source and drain contacts are metals, and the SB height is equal to half the band-gap of the channel GNR (ΦBn = A simulator based on table lookup techniques was imple- ΦBp = Eg /2). The gate modulates the quantum tunneling cur- mented to simulate circuits built with GNRFETs. The simu- rent through the SB at the source end of the channel, and the lator uses the drain current ID (VG ,VD ) and channel charge device operates as a SBFET [11]. Q(VG ,VD ) computed for the intrinsic GNRFET using the The I–V device characteristics for the ideal N = 12 quantum-transport simulations described in Section II. These GNRFET for different drain voltages is shown in Fig. 2(a). values were used to populate a lookup table at discrete volt- Ambipolar characteristics due to both electron and hole con- age steps of VGS and VDS ranging from 0 to 0.75 V. The duction are clearly seen, and the drain voltage exponentially intrinsic gate and drain capacitances CGD,i and CGS,i vary increases the minimum leakage current. If ION is divided by with the gate and drain voltages. These values can be com- the channel width, it is 6300 μA/μmfortheN =12GNRFET puted and stored in the lookup table by differentiating the chan- when VD is 0.5 V. As drain voltage increases, SBFETs show nel charge w.r.t. VGS and VDS, respectively. Thus, CGD,i = linear behavior in the overall range of gate bias. For example, |∂Q/∂VDS| and CG,i = CGS,i + CGD,i = |∂Q/∂VGS|, which the drain current and the channel charge for VD = 0.75 V are yields CGS,i = |∂Q/∂VGS|−|∂Q/∂VDS|. linearly proportional to VG , whereas those for VD = 0.25 V The extrinsic n-type and p-type GNRFETs were modeled by show exponential behavior in the sub-threshold region. adding the parasitic capacitances and contact resistances around As shown in Fig. 2(a), the I–V characteristics exhibit electron the intrinsic GNR, as shown in Fig. 3(a). Two strategies— conduction at high gate voltages and hole conduction at low gate fabricating very narrow contacts to an individual GNR or fab- voltages, with minimum leakage current at VG ≈ VD /2.The ricating multiple GNRs in an array for a wide contact—are ambipolar conduction is explained by observing that the device currently under investigation in the device community. The 730 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011

Fig. 3. (a) Circuit model for GNRFET simulation. (b) EDP, frequency, and SNM contours for a 15-stage ring oscillator.

GNRFET considered in this paper is comprised of four equidis- A. Technology Exploration tant GNRs that form the channel. The pitch refers to the spacing The tradeoff between delay, energy, and noise robustness can between the neighboring GNRs in the GNRFET channel, and be explored for different values of V and V for GNRFET cir- 1 μ DD T usually ranges from the GNR width to m as annotated in cuits. We choose a 15-stage ring oscillator, where each inverter the figure. In this paper, we assume that an individual GNR drives a fanout-of-4 load as the representative circuit for this channel has a contact width of 10 nm, and that this equals the study. The EDP has been widely used to explore the tradeoffs pitch in the GNR array. Thus, a GNRFET with four GNRs has between delay and power in CMOS circuits. The EDP captures a total contact width of 40 nm. The current in the GNRFET how delay can be reduced by increasing V and reducing V , is four times the current in the individual GNR channel, and DD T dynamic power can be reduced by lowering VDD, and static the parasitics are also four times that for an individual GNR. power can be reduced by increasing V . The EDP attains a Thus, the parasitic junction capacitances C and C are T GD,e GS,e minimum at an intermediate value of V and V , and can be 0.01 0.1 T DD given by – aF/nm times the total GNRFET contact width used for technology exploration of GNRFET circuits. Fig. 3(b) of 40 nm. It is assumed that the substrate is thick enough and presents the EDP contours (solid curves) for the ring oscillator. that the extrinsic parasitic capacitances CDB,e and CSB,e are The optimum value of the EDP is achieved at VDD = 0.15 V negligible. The contact capacitance at the device terminals and and V = 0.08 V, and is conventionally the preferred operating interconnect capacitance are assumed negligible and are not T point for the circuit. considered in this paper. However, this optimum corresponds to a low frequency of 1 The contact resistances were assumed to range from to operation. By plotting the frequency of operation that can be 100 kΩ, with a nominal value of 10 kΩ. The SB contact be- achieved for a 15-stage ring oscillator for each VDD–VT com- tween the metal source/drain electrodes and the GNR chan- bination, it is possible to explore performance-energy tradeoffs nel, which is modulated by the gate voltage, is modeled in the further using the following observation. For a given desired fre- NEGF quantum-transport calculation. The approach to model- quency of operation, the optimum EDP curve is tangential to the ing the SB contact in this study is standard, as used by many frequency curve. For example, for a desired frequency of 3 GHz groups, e.g., [19], [33]. The parasitic resistance component in for the 15-stage ring oscillator, point A in Fig. 3(b) suggests that Fig. 3(a) accounts for additional parasitic resistance, such as the the minimum EDP is attained at VDD = 0.3 V and VT = 0.06 V. diffusion resistance of the thin metal films. The parasitic capac- Reliability can be introduced as an additional figure-of-merit itances were also determined using a 2-D capacitance model. to determine optimum EDP for a desired frequency of operation The values used in this paper for the resistive and capacitive by drawing the static noise margin (SNM) contours for an in- parasitics are in the ballpark as characterized by earlier ex- verter. These contours represent points of equal SNM for each periments. The simulation model has been calibrated to ex- V –V combination. Point A in the figure lies on the 0.1-V perimental data with very good agreement in the context of DD T SNM contour, which is unacceptable for most applications. CNTFETs [24]. CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 731

TABLE I TABLE II DELAY,EDP,AND SNMSFORGNRFETS AND CMOS FREQUENCY AND EDP VERSUS PITCH AND NUMBER OF GNRS

does not consider tunneling currents, no leakage power is dissi- When a desired SNM is identified, the intersection of the desired pated when the gate-source voltage is zero. frequency and SNM contours identifies a region for reliable op- A striking difference between the scaled CMOS nodes and eration that achieves desired performance. The intersection of GNRFETs is that the optimum EDP for scaled CMOS is 26– the two curves determines the point of minimum EDP. For ex- 144× higher than the EDP for GNRFETs at operating point B. ample, for a SNM of 0.15 V at 3 GHz, the optimum V –V DD T GNRFETs have lower noise margins in comparison to scaled combination is given by point B with V =0.4 V and V = DD T CMOS and are also more susceptible to variability and defects as 0.13 V in Fig. 3(b). This operating point offers a good tradeoff discussed in the remainder of this paper. However, the significant between EDP, performance, and noise. difference in EDPs leaves enough headroom for robust design Note that unlike CMOS, increasing V does not necessar- T with GNRFETs to overcome these challenges. ily help tradeoff performance for higher noise robustness in Design Parameters (Pitch and Number of GNRs): Table II GNRFET circuits. For example, the operating point C with shows the performance and EDP of a 15-stage ring oscillator V = 0.4 V and V = 0.23 V has the same EDP and noise DD T for different values of pitch and for different number of GNRs margins as point B in the figure. However, the frequency of the in the array of a GNRFET device. Table II shows that increas- ring oscillator for operating point B is 40% greater than that ing the pitch decreases the frequency of the ring oscillator and for operating point C, as seen in the figure. Higher V at C is T increases the EDP. This trend is observed because increasing achieved by decreasing the offset as shown in Fig. 2, which cor- the pitch increases the extrinsic parasitic capacitance within the responds to operating the ring oscillator at a point other than that GNRFET. However, an interesting observation is that for the of minimum leakage, as explained in Section II. As a result, the same pitch, the frequency of the ring oscillator decreases and resulting potential divider effect within the GNRFET inverter the EDP increases, as we increase the number of GNRs in the limits noise margins and decreases performance as observed in array. This is because the extrinsic capacitance is proportional to the figure. the contact width, which is given by the product of the number Comparison to Scaled CMOS: Table I compares the per- of GNRs and the pitch. Hence, as the number of GNRs in the formance, EDP, and SNM of the 15-stage ring oscillator for array increases, the extrinsic capacitance increases. The drive GNRFETs and scaled CMOS nodes (simulated using the pre- current of the channel also increases as we increase the number dictive technology model (PTM) [34]). For all scaled CMOS of GNRs in the array. However, the effect of increase in extrin- nodes, V = 0.8 V provides the best performance, V = 0.4 DD DD sic capacitance is more dominant, and thus the frequency of the V consumes the least power, and V = 0.6 V provides the best DD ring oscillator decreases. The screening effect of the GNRs has tradeoff between performance and power. been neglected in this paper. This is a reasonable assumption for For CMOS technology based on the PTM, the intrinsic ca- values of pitch used in this paper. However, it has been shown pacitance of a fanout-of-4 inverter is about one-third of the in [35] that screening effect in CNTFETs cannot be neglected total capacitance. Hence, the intrinsic capacitance contributes for smaller values of pitch. A similar study of screening effect in to about 33% of the dynamic power component of EDP. In con- GNRFETs is necessary and is a potential area of future research. trast, for GNRFETs, the values of the intrinsic gate-source and gate-drain capacitances depend on the operating point and range from 6%–8% of the fanout load capacitance for a fanout-of-4 IV. INTRINSIC GNRFETS:VARIATIONS AND DEFECTS inverter. The contribution of the intrinsic and fanout load capacitances to the EDP also depends on technology-dependent Variability and defects are expected to play an important role factors, such as source and drain contact resistances. When the in graphene electronics in practice. Variability, for example, contact resistance is small (1 kΩ), the circuit switches faster and can come from the difficulty in control of the GNR width or the intrinsic capacitances account for 8%–10% of the dynamic oxide thickness in fabrication. The charge impurity in the gate power component of EDP. Similarly, for contact resistance of insulator, lattice vacancy, or edge roughness [36] of GNR may 10 kΩ and 100 kΩ, the intrinsic capacitances account for roughly be a defect that results in a large performance variation. Our 15%–18% and 22%–25% of EDP. For CMOS technology based atomistic NEGF simulation of a wide variety of variability and on the PTM, at VDD = 0.6 V, the leakage power dissipated when defect mechanisms have identified the important role of the GNR gate-source voltage is zero is a negligible fraction of the total width variation and the effect of Coulomb charge impurities in power dissipation, and hence, a negligible fraction of the EDP graphene, which are the subject of this study. Other defect and (about 0.004%). For GNRFET technology, since our framework variability mechanisms exist and should be explored in future 732 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011

B. Charge Impurities For SBFETs, the charge impurity may affect device characteristics most severely when it is located close to the source, since the SB between source and GNR is affected. In our simulations, the charge impurity is considered as a fixed external charge in the gate-oxide region, and it plays an important role for self-consistent electrostatic potential. To exaggerate the effects of an impurity, the impurity is placed near the source and at a distance of 0.4 nm from the GNR surface. Both polarities of charges are considered, and the charge magnitude is also Fig. 4. I–V characteristics for different GNR widths, where the GNR width varied. is about 1.23 A˚ times its index, as labeled in the figure. Fig. 5(a) shows the severely affected SB due to the charge impurity. The inset in the figure shows the position of the charge impurity in the cross section of the simulated device. A nega- studies, but we expect the effects are qualitatively similar and tive charge impurity increases the barrier height and thickness, can be explored by readily extending the bottom-up simulation whereas a positive charge impurity decreases the barrier height framework presented here. and thickness at the source contact. This affects the source–drain The occurrence of variation and defect events in the GNR current and the charge in the channel. With the negative charge array channel of a GNRFET is modeled and analyzed in two impurity of −2q, the electron flow is significantly reduced by ways. In the first case, it is assumed that only one GNR in the ar- the large barrier, and the ON current is a factor of 6 smaller than ray is subject to a variation, defect, or combination thereof. The that in the ideal device. For the device with the +2q positive total current is given by the sum of the currents in the GNRs, charge impurity, both OFF and ON currents show a relatively nominal or otherwise. Since the pitch is larger than the gate smaller variation from the ideal device compared to that with oxide thickness, an impurity near one GNR has a negligible ef- the −2q negative charge impurity in the n-type operation branch fect on other GNRs because the impurity charge electric field is (VG > 0.25 V), as illustrated in Fig. 5(b). screened by the gate. In practice, multiple defects and variability of all GNRs in the array may exist, and this is handled in the second case by assuming that each GNR in the channel expe- V. GNRFET CIRCUITS:VARIATIONS AND DEFECTS riences the same variation, defect, or combination thereof. The results in this study, therefore, establish lower and upper limits In this section, we study the sensitivity of inverter delay, for the effects of variations and defects on GNRFET circuits. power, and noise robustness to variations in GNR width and Future studies are necessary to address multiple variability and charge impurities. The combined effect of variations in GNR defect effects, but we expect the broader conclusions to remain width and charge impurities is also studied to identify the worst the same. case combination of width variation and charge impurity on delay, power, and noise margins. As explained in the earlier section, two scenarios are considered: one where the anomaly A. GNR Width Variations affects one out of four GNRs in the array, and the second where The band-gap in AGNRs originates from quantum confine- all four GNRs in the array are similarly affected. The simulations ment, and edge effects play a critical role [10]. The band-gap of were performed for an inverter with a fanout-of-4 load. The the semiconducting GNR is, in general, inversely proportional operating point (VDD = 0.4 V and VT = 0.13 V) derived in to the GNR width. Since device characteristics are very sen- Section III-A as a good tradeoff point among delay, energy, and sitive to the band-gap of channel material, the width effect is noise robustness for the nominal device is used to simulate all critical to GNRFET performance. GNR width is proportional the GNRFET circuits in this section. In Tables III and IV, the to the GNR index. GNRs with index values of 9, 12, 15, and nominal value of delay is reported in picoseconds, nominal static 18 are used to study the effect of variations in width. Starting and dynamic power in microWatt, and nominal noise margin in with the minimum GNR index of N = 9, which has a width of Volt. All other entries in the table are reported as percentage 1.1 nm, the index is increased in steps of 3, or equivalently, by deviation with respect to the nominal case. an incremental width of 3.7 A.˚ Fig. 4 illustrates how variability in GNR width affects device A. Width Variations ID –VG characteristics. The band-gap of the N = 18 GNR is too small to achieve a small leakage current, whereas that of the Table III shows the delay, power, and noise margin due to N = 9 GNR is sufficiently large so that ION/IOFF is as high independent variations in GNR width in both the n-type and as 1000×. However, the capacitance of a wider GNRFET is p-type GNRFETs of an inverter. The nominal inverter has both large due to the larger surface of the GNR channel. The N = 18 n-type and p-type GNRFETs composed of four N = 12 GNRs GNRFET has 50% larger intrinsic channel capacitance than the in the array. The delay of an inverter driving a fanout-of-4 load, N = 9 GNRFET in the ON state, which can affect performance with nominal n-type and p-type GNRFETs composed of four as discussed in the following section. N = 12 GNRs in the array, is 7.54 ps. The delay increases as CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 733

Fig. 5. (a) Conduction-band proﬁle of N = 12 GNRs with and without charge impurity. The inset shows the position of the charge impurity in the cross section of the simulated device. (b) I–V characteristics for N = 12 GNRs with charge impurities.

TABLE III EFFECT OF INDEPENDENT VARIATIONS IN GNR WIDTH IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM

TABLE IV EFFECT OF INDEPENDENT CHARGE IMPURITIES IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM

the width of the GNR decreases to N = 9 and decreases as the significantly. When the n-type and p-type GNRFETs of an in- width increases to N = 18. In each entry in the table, the comma verter have the same width, the SNM increases with decrease separates the first scenario when only one GNR is affected from in width due to the increase in inertial delay in the inverter. The the second scenario when all four GNRs in the GNRFET array noise margin decreases from 0.17 to 0.09 V as the width (of both are affected. In the worst case, when one to four GNRs in both n-type and p-type GNRFETs) increases from N = 9toN = 18. the p-type and n-type GNRFETs are N = 9 GNRs, the delay However, the noise margins degrade further when n-type and increases by 6%–77%. On the other hand, there is a 12%–30% p-type GNRFETs have different widths, and reach their worst decrease in the delay of an inverter when one to four GNRs case deviations when there is maximum mismatch of N = 9 and in both the p-type and n-type GNRFETs are N = 18 GNRs. N = 18 between the n-type and p-type GNRFETs. In this case, Variations in GNR width significantly impact both static and the SNM is off by 27%–80% from its nominal value of 0.15 V. dynamic power. When one to four GNRs in both the p-type and n-type GNRFETs are N = 9 GNRs, static and dynamic B. Charge Impurities power are reduced by 13%–47% and 8%–38%, respectively. In the worst case, however, static and dynamic power increase by Table IV shows the delay, power, and noise margin due to in- 313%–643% and 27%–217%, respectively. The impact of vari- dependent charge impurities that affect one to four of the GNRs ations in width on leakage power stands out in this table, since in both the n-type and p-type GNRFETs of an inverter. Note even single GNR variations in the two GNRFETs can increase that a +q charge has the same effect on a p-type GNRFET − static power consumption by 3×. Finally, it is observed that device as a q charge has on an n-type GNRFET device, and GNR width variations affect the SNMs of a GNRFET inverter vice versa. The nominal inverter has both n-type and p-type GNRFETs composed of no charge defects on all four GNRs 734 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011

TABLE V EFFECT OF INDEPENDENT VARIATIONS AND CHARGE IMPURITIES IN N-/P-GNRFET CHANNELS ON INVERTER DELAY,POWER, AND SNM

in the array. The effect of charge impurities is highly asym- upper bound effects is pessimistic and may lead to sub-optimal metric, with large degradation in delay, power, and noise mar- designs. Hence, it is necessary to study the average-case be- gin, but only small improvements. Inverter delay is degraded havior of GNRFETs in the presence of nonidealities through by 8%–92% in the presence of simultaneous −2q and +2q Monte Carlo techniques. A randomly selected nonideality is in- charge impurities in one to four n-type GNRFETs and p-type jected in each GNR of the n-type GNRFET and p-type GN- GNRFETs, respectively. However, the maximum improvement RFET in an inverter. The inverter is simulated using table- in delay observed due to the presence of simultaneous +q and lookup to compute its delay, static power, and dynamic power. −q charge impurities in one to four n-type GNRFETs and p- The average delay, static power, and dynamic power over a type GNRFETs, respectively is 1%–9%. Charge impurities af- large number of runs give the average-case behavior of the fect static power more than dynamic power in a trend similar to device. that observed for variations, but to a smaller extent. When one to We performed Monte Carlo simulations using the aforemen- four GNRs in both the p-type and n-type GNRFETs are subject tioned technique to study the average-case delay, static power, to +q and −q charge impurities, respectively, static and dy- and dynamic power dissipation of an inverter. Independent vari- namic power increase by 11%–37% and 5%–19%, respectively. ations in width (N = 9/12/15) and charge impurities (−q/0/+q) Charge impurity defects have a smaller effect on the noise mar- was assumed for the GNRs. The width and charge impurities gin of an inverter in comparison to variations in GNR width. The for the GNRFETs were drawn from a normal distribution, with presence of simultaneous +q and −q charge impurities affect- mean width N = 12 and mean charge equal to zero. The widths ing one to four n-type and p-type GNRs, respectively, degrades N = 9/15 and charge +q/−q were set to σ for the two distribu- the noise margin by 14%–40%, with a 7% improvement in the tions, which were discretized to reﬂect the nature of occurrence best case. of variations and defects in GNRFETs. 1) Inverter: The delay of a nominal inverter is 18.2 ps. Vari- ations and defects yield inverters with delay ranging from 13.5 C. Simultaneous Defects and Variations to 41.9 ps. The mean delay of a GNRFET inverter in the pres- In this section, we study the impact of simultaneous variations ence of simultaneous variations and defects is 20.2 ps and the in width and charge impurities on an inverter, ring oscillator, standard deviation is 4.2 ps. The static (dynamic) power dissi- and latch. Table V shows the impact of simultaneous variations pation of a nominal inverter is 0.11 μW(0.71 μW). Variations in width and charge impurities on the delay, power, and noise and defects yield inverters with static (dynamic) ranging from margins of an inverter. The nominal inverter has both n-type 0.07 μW(0.39 μW) to 0.4 μW(1.25 μW). The mean static (dy- and p-type GNRFETs composed of four N = 12 GNRs and no namic) power of a GNRFET inverter in the presence of simul- charge defects. taneous variations and defects is 0.14 μW(0.73 μW) and the In the worst case when all GNRs in the array are affected, standard deviation is 0.08 μW(0.13 μW). The mean delay for delay increases by over 2×, static power increases by over 7×, an inverter in the presence of defects and variations is 10% dynamic power increases by over 2×, and the noise margin higher than the delay of the nominal inverter. Similarly, the reduces to zero. These effects are less pronounced on delay mean static (dynamic) power dissipation of an inverter is 27% and noise margin when only one GNR in the array is affected. (3%) higher than the nominal value. Thus, the delay and static However, static power still increases by nearly 4× and dynamic power of an inverter are most affected by variations and defects. power by 1.5×. To summarize, the delay, power, and noise mar- 2) Ring Oscillator: A 15-stage ring oscillator consists of gins for simultaneous defects and variations in the GNRFET 15 inverters that could potentially have different delays, inverter are dominated by variations in GNR width and exacer- static power, and dynamic power dissipation depending on bated by charge impurities. the variation-defect combination of the GNRs in its n-type The lower and upper bounds on the effects of width vari- GNRFET and p-type GNRFET. In each run of the Monte Carlo ations and charge defects were obtained by assuming that a simulation, a variation-defect combination is injected separately nonideal GNRFET has a nonideality in exactly one out of four in each GNR of every inverter in the ring oscillator. The prop- GNRs, or the same nonideality in all the GNRs. However, post- agation delay (Δ), static power (Pstat), and dynamic power fabrication GNRFETs may have different nonidealities on all (Pdyn) for each inverter is computed for a rising and a falling four GNRs. Designing circuits that account for lower bound transition using the aforementioned technique. The frequency, effects of variations and defects may lead to unreliable de- static power, and dynamic power of the 15-stage ring oscillator signs. On the other hand, designing circuits that account for is then computed using the propagation delay, static power, and CHOUDHURY et al.: GRAPHENE NANORIBBON FETs: TECHNOLOGY EXPLORATION FOR PERFORMANCE AND RELIABILITY 735

worst case for inverters), a source of concern for most memory applications. However, both the redundancy required for error detection and correction as well as the high static power may be offset by the advantages of high density and low power that GNRFETs offer over scaled CMOS.

VI. CONCLUSION Fig. 6. Monte Carlo simulations for 15-stage ring oscillator. GNRFETs have been intensively explored both experimentally and theoretically as potential candidates for nanoelectronics applications. Quantum effects and atomistic scale features inevitably play an important role in such nanoscale electronic devices and circuits. We have developed a bottom-up multi- scale simulation framework that treats atomistic scale features in circuit simulations. The simulation framework is applied to technology exploration of GNRFET circuits, with an empha- sis on variability and charge impurity effects. The GNR material promises ultrasmall, fast, and low-energy FETs, but two key effects of variability and defects—leakage and low noise Fig. 7. SNM for latch with variations and defects. margins—are significant. For example, the variation of the channel width by a couple of angstrom changes the leakage current dynamic power of each inverter as follows: by orders of magnitude, and a single Coulomb charge impurity can lower the FET ON-current by about 30%. This assessment 1 f = of the effects of variability, defects, and parasitics indicate their all inverters(Δrise +Δfall) important role on circuit performance. These effects must be carefully considered in the performance assessment and design Pstat = 0.5(Pstat,rise + Pstat,fall) optimization for graphene-based electronics technology. all inverters ACKNOWLEDGMENT Pdyn = 0.5(Pdyn,rise + Pdyn,fall). all inverters M. R. Choudhury and Y. Yoon contributed equally to this Fig. 6 presents the distributions for delay, dynamic power, and work. static power for the oscillator. Although the mean value of dy- REFERENCES namic power remains unchanged, the mean value of frequency [1] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. 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