Graphene Nanoribbon Fets: Technology Exploration for Performance and Reliability Mihir R
Total Page:16
File Type:pdf, Size:1020Kb
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 727 Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability Mihir R. Choudhury, Student Member, IEEE, Youngki Yoon, Member, IEEE,JingGuo, Member, IEEE, and Kartik Mohanram, Member, IEEE Abstract—Graphene nanoribbon FETs (GNRFETs) are promis- Although 2-D graphene is a zero band-gap semi-metal, ing devices for beyond-CMOS nanoelectronics due to their a band-gap opens when a FET channel is fabricated on a excellent carrier-transport properties and potential for large- nanometer-wide graphene nanoribbon (GNR) [6]–[9]. In gen- scale processing and fabrication. This paper combines atomistic quantum-transport modeling with circuit simulation to perform eral, the band-gap of a GNR is inversely proportional to its width, technology exploration for GNRFET circuits. Results indicate that and width confinement down to the sub-10-nm scale is essen- GNRFETs offer significant gains over scaled CMOS at the 22-, 32-, tial to open a band-gap that is sufficient for room temperature and 45-nm nodes, with over 26–144× improvement in the energy- transistor operation. Unlike CNTs, which are mixtures of metal- delay product at comparable operating points. A quantitative study lic and semiconducting materials, recent samples of chemically of the effects of variations and defects on the performance and re- liability of GNRFET circuits is also presented. Simulation results derived sub-10-nm GNRs have exhibited all semiconducting indicate that whereas GNRFET circuits promise higher perfor- behavior [9], generating considerable excitement for transistor mance, lower energy consumption, and comparable reliability at applications. The two main types of GNRs, with the edges of the similar operating points to scaled CMOS circuits, they are more ribbons assumed passivated by hydrogen atoms, are armchair- susceptible to variations and defects. These results motivate signif- edge and zigzag-edge GNRs (AGNRs and ZGNRs). ZGNRs icant engineering, modeling, and simulation challenges facing the device and computer-aided design (CAD) communities involved in are predicted to be metallic by a simple tight-binding model, graphene electronics research. but a band-gap exists in more advanced, spin-unrestricted simu- lations [10]. For digital circuits applications, the focus has been Index Terms—Circuit design, defects, energy, energy-delay product, field-effect transistor, graphene, inverter, latch, nanorib- on using AGNRs as the channel material. AGNRs have an elec- bons, performance, quantum transport, reliability, ring oscillator, tronic structure that is closely related to that of zigzag CNTs. variability. The band-gap in AGNRs originates from quantum confinement, and edge effects play a critical role [10]. I. INTRODUCTION This paper first provides an overview of Schottky barrier (SB) RAPHENE, which is a monolayer of carbon atoms GNRFETs with intrinsic AGNR channels (GNRFETs hence- G packed into a 2-D honeycomb lattice, has emerged as a forth, unless specified otherwise). Unlike traditional MOSFETs, promising candidate material for beyond-CMOS nanoelectron- SBFETs use metal or metal silicide contacts at the source and ics. Graphene-based devices offer high mobility for ballistic drain ends, leading to the formation of SBs at these contacts. transport, high carrier velocity for fast switching, monolayer In SBFETs, the gate modulates the quantum tunneling current thin body for optimum electrostatic scaling, and excellent ther- through the SB [11]. Recently fabricated GNRFETs with chan- mal conductivity [1]–[6]. The potential to produce wafer-scale nel lengths of the order of 200 nm delivered about 21% of the graphene films with full planar processing for devices promises ballistic current at VD = 1 V, and about 4.5% of the ballistic high integration potential with conventional CMOS fabrication current at low VD < 0.1 V [12]. Clearly, these are prelimi- processes, which is a significant advantage over carbon nan- nary devices, and it would be natural to expect further advances otubes (CNTs) [6]. such as the integration of ultrathin high-κ dielectrics [13] and aggressive channel length scaling to move the performance of these devices closer to the ballistic limit, with switching speeds, Manuscript received October 18, 2009; revised June 2, 2010; accepted July ION/IOFF, and sub-threshold slope that is competitive with 19, 2010. Date of publication September 9, 2010; date of current version July scaled CMOS. 8, 2011. This work was supported in part by the National Science Foundation under Grant CCF-0916636 and Grant CCF-0916683, and in part by the Office Although most discussions in this paper focus on SB-type of Naval Research. The review of this paper was arranged by Associate Editor GNRFETs [14], [15], simulation studies of MOSFET-type R. Lake. GNRFETs with doped reservoirs have also been reported in M. R. Choudhury and K. Mohanram are with the Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005 USA (e-mail: [16]–[18]. In [19] and [20], SB-type GNRFETs were also com- [email protected]; [email protected]). pared to MOSFET-type GNRFETs. There is consensus that Y. Yoon was with the Department of Electrical and Computer Engineering, in ideal devices, MOSFET-type GNRFETs show better de- University of Florida, Gainesville, FL 32611 USA. He is now with the University of California, Berkeley, CA 94720 USA (e-mail: ykyoon@ufl.edu). vice characteristics over SB-type GNRFETs: larger maximum J. Guo is with the Department of Electrical and Computer Engineering, achievable ION/IOFF, larger ION, larger transconductance, and University of Florida, Gainesville, FL 32611 USA (e-mail: guoj@ufl.edu). better saturation behavior. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Further, this paper presents extensive results on technology Digital Object Identifier 10.1109/TNANO.2010.2073718 exploration for GNRFET circuits. It couples atomistic quantum- 1536-125X/$26.00 © 2010 IEEE 728 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 transport modeling in intrinsic GNRFETs with a circuit simulator that includes parasitics and nonidealities that are nec- essary to capture extrinsic effects in fabricated GNRFETs. At the device level, GNRFETs are simulated by self-consistently solving an atomistic quantum transport equation based on the nonequilibrium Green’s function (NEGF) formalism with the 3-D Poisson’s equation. These rigorous simulations provide I– V and Q–V data for intrinsic GNRFETs, which are integrated Fig. 1. NEGF formalism for a generic transistor. into a circuit-level simulation framework based on lookup tables for technology exploration of GNRFET circuits. The simulator This paper is an extended version of [21] and is organized is used to study the delay, power, energy, and noise margins of as follows. Section II provides a background in quantum simu- representative GNRFET circuits including inverters, ring oscil- lation of intrinsic GNRFETs. Section III describes technology lators, and latches. Results indicate that GNRFETs offer signif- exploration for GNRFET circuits based on a large-signal circuit icant gains over scaled CMOS at the 22-, 32-, and 45-nm nodes, model for extrinsic GNRFETs. Sections IV and V discuss how with over 26–144× improvement in the energy-delay product variations and defects impact the performance and reliability of (EDP) at comparable operating points. GNRFET circuits. Section VI is a conclusion. Significant technical challenges, however, remain to be met. Due to the atomically thin and nanometer-wide geometries of II. SIMULATION OF INTRINSIC GNRFETS GNRs, variability and defects are projected to have a larger impact on circuit performance and reliability in comparison As devices scale with technology, a powerful quantum trans- to conventional silicon devices. The framework is extended to port simulation framework based on the NEGF formalism pro- perform a quantitative study of the effects of variations and vides an ideal approach for bottom-up device modeling and defects in intrinsic GNRFETs on the performance and reliabil- simulation [22] for the following reasons: 1) atomistic descrip- ity of GNRFET circuits. Independent variations in GNR width, tions of devices can be readily implemented; 2) open boundaries which is the most common source of variation, and independent can be rigorously treated; and 3) multiphenomena (e.g., inelastic charge impurities in the gate oxide, which is the most com- scattering and light emission) can be modeled. mon source of defects, are considered in this paper. Variation Fig. 1 summarizes the procedure to apply the NEGF approach in GNR width affects GNRFET ION/IOFF nonlinearly, which to a generic transistor. The transistor channel, which can be a in turn impacts circuit performance, power, and noise margins. piece of silicon, a GNR, a nanowire, or a single molecule, is Simulation results indicate that variation in GNR width can in- connected to the source and drain contacts. The gate modulates crease the delay, static power, and dynamic power of inverters the conductance of the channel. One first identifies a suitable by 6%–77%, 313%–643%, and 37%–215%, respectively, while basis set and derives the Hamiltonian matrix H for the isolated reducing the noise margin by 27%–80%. Charge impurities af- channel. Then, the self-energy matrices Σ1 , Σ2 , and ΣS , which fect intrinsic GNRFET characteristics nonlinearly and in an describe how the channel couples