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Amiga 1200 Schematic

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Amiga 1200 Schematic Amiga A1200_R1 Rev.1.38 (06.09.2012) Revision History REV DESCRIPTION DATE APRVL MANAGER 0 Engineering Prototype 03/13/92 GRR 1 Advance Engineering Release 06/29/92 GRR Jumpers and Stuff Connectors 1a Pilot Production Release 09/09/92 GRR 1b FTZ Production Release 09/09/92 GRR REF TYPE DESCRIPTION PAGE REF TYPE DESCRIPTION PAGE 1d FCC/FTZ Production Release 10/10/92 GRR R246 SMT NTSC Color Burst 4 CN1 DB9P Mouse/Joystick 1 5 R202 SMT PAL Color Burst 4 CN2 DB9P Mouse/Joystick 2 5 R625 SMT Keyboard MPU Clock 9 CN3 RCA-J Right Audio Output 5 R624 SMT Keyboard/System Reset 9 CN4 RCA-J Left Audio Output 5 CN5 DB23S External Floppy 8 CN6 DB25P RS232 Serial Port 7 CN7 DB25S Parallel Printer Port 7 CN8 SQ DIN Power Supply Connector 13 CN9 DB23P Video Output 6 CN10 RCA-J Composite Video 4 CN11 DIL-34 Internal Floppy Signal 8 CN12 SIL-4 Internal Floppy Power 8 CN13 MEM-30 Keyboard Membrane 9 CN14 SIL-4 Internal Floppy Power 8 CN13 MEM-30 Keyboard Membrane 9 CN14 SIL-4 Keyboard Status LED's 9 CN15 PCMCIA PC"Memory Card" 11 P9 EDGE-80 Memory Bus Expansion 12 Signal Glossary SIGNAL DESCRIPTION (AREA) PAGES SIGNAL DESCRIPTION (AREA) PAGES 28MHZ 28.63636 MHz Master Clock LPEN Light Pen Trigger (Joysticks) 7MHZ 7.15909 MHz Processor Clock MTR Motor On (Floppy) A[23:1] Processor Address Bus (68000) MTR0 Motor On - Drive 0 (Floppy) ACK Data Acknowledge (Parallel Port) M0V/M0H Mouse 0 Quadrature V/H (Joysticks) AS Address Strobe (68000) M1V/M1H Mouse 1 Quadrature V/H (Joysticks) AUDIN Audio Input (RS232 Port) OVL Overlay ROM over RAM AUDOUT Audio Output (RS232 Jack) OVR Override System Decoding BEER Bus Error (68000) PIXELSW Genlock Pixel Switch (Video) BG Bus Grant (68000) POT0X/0Y Pot Lines 0 X/Y (Joysticks) Key Components BGACK Bus Grant Acknowledge (68000) POT1X/1Y Pot Lines 1 X/Y (Joysticks) BLISS Blitter Slowdown (Chips) POUT Paper Out (Parallel Port) REF CHIP DESCRIPTION PAGE BLIT Chip Memory Access (Chips) PPD[7:0] Parallel Port Data (Parallel Port) BR Bus Request (68000) RAMEN RAM Enable (Chips) U1 68000 68000 Processor 16MHz 2 BUSY Device Busy (Parallel Port) REGEN Chip Register Enable (Chips) U2 8374 Alice (AA Agnus) 2 CASL/U Column Address Strobe (DRAM) RAS0/1 Row Address Strobe (DRAM) U3 8364 Paula 5 CCK/CCKQ Color Clock / Quadrature (Chips) RDY Drive Ready (Floppy) U4 4203 Lisa (AA Denise) 4 CDAC 7.15909 MHz Quadrature Clock (Chips) RESET General Reset CHNG Media Change (Floppy) RGA[8:1] Register Address Bus (Chips) U5 f023a AA Gayle (CBM ASIC) 2,8,11 CLKRD/WR Read-Time Clock Read / Write (RTC) R/G/B Red / Green / Blue (Video) U6 asst ROM 512Kx16, 150 nS 10 COMP Monochrome Composite Video (Video) RI Ring Indicate (RS232 Port) U7-8 8520 Amiga VIA, 1 MHz 7 CSYNC Composite Sync (Video) ROMEN ROM Enable (ROM) U10-11 28F10 Flash Memory 128Kx8 10 CTS Clear to Send (RS232 Port) RTS Request to Send (RS232 Port) U12 CXA1145 Sony Video Encoder 4 D[15:0] Processor Data Bus (68000) RST Processor Reset (68000) U13 68HC05 amiga Keyboard MPU 9 DIR Step Direction (Floppy) RXD Receive Data (RS232 Port) U49 PST518 Low Voltage Sense IC 9 DKRD Disk Read Data (Floppy) RW Processor Read/Write (68000) U15 LF347 BiMOS Op-Amp 5 DKWD Disk Write Data (Floppy) SEL Select (Parallel Port) TL084 BiCMOS Op-Amp alt DKWE Disk Write Enable (Floppy) SEL[3:0] Drive Select (Floppy) U16-17 Asst DRAM 256Kx16, 80nS 3 DMAL Chip DMA Request Line (Chips) SIDE Side Select (Floppy) U18-19 Asst DRAM 256Kx16 Optional 3 DRA[8:0] DRAM Address Bus (DRAM) STEP Step In/Out Command (Floppy) U20 391??? Budgie (ASIC) 2 DRD[15:0] DRAM Data Bus (DRAM) TRK0 Track Zero Sense (Floppy) U28 1488 EIA Line Driver 7 DSR Data Set Ready (RS232 Port) TXD Transmit Data (RS232 Port) U29 1489 EIA Line Receiver 7 DTACK Data Transfer Acknowledge (68000) VMA Valid Memory Address (68000) U30 BT101 Triple 8-bit Video DAC 4 DTR Data Terminal Ready (RS232 Port) VPA Valid Peripheral Address (68000) E Peripheral Enable Clock (68000) VSYNC Vertical Sync (Video) EXTICK Expansion Present / RTC Tick WE Write Enable (DRAM) X1 OSC TTL 28.63636 MHz NTSC 2 FC[2:0] Function Code (68000) WPROT Write Protect Sense (Floppy) OSC TTL 28.37512 MHz PAL alt FIRE0/1 Fire Button 0/1 (Joysticks) XCLK External Genlock Clock (Video) Y451 XTAL 4.43619MHz PAL Burst 4 HLT Processor Halt (68000) XCLKEN External Clock Enable (Video) Y621 XTAL 3MHz Ceramic Resonator 9 HSYNC Horizontal Sync (Video) XRDY External Data Ready INDEX Index Pulse (Floppy) X2 asst PAL Video Modulator 4 INT[2,3,6] Interrupt Request (Chips) asst NTSC Video Modulator 4 IORESET I/O Reset IPL[2:0] Interrupt Priority Level (68000) ** Credit Card and IDE Stuff? ** KBCLOCK Keyboard Clock (Keyboard) KBDATA Keyboard Data (Keyboard) KBRESET Keyboard Reset (Keyboard) LDS/UDS Upper / Lower Data Strobes (68000) LED Power On LED / Audio Filter Disable LEFT/RIGHT Left Right Audio (Audio) DIRECTORIES AND REVISION HISTORY DESIGN BY: DATE c 1992 Commodore Business Machines G. Robbins 03/13/92 Commodore Information contained herein is the unpublished, DRAW: GRR 03/13/92 confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board reproduction or disclosure of this information APPR: "Channel Z" without the prior written permission of USED ON NEXT ASSY Commodore is strictly prohibited. SIZE REV A1200 Rev 1->1d PCB C/A1200 364718 C 364717 1a C.A.D. Generated SCALE SHEET 1 OF 13 No manual changes may be made to this document Rev.1.38 (06.09.2012) PATH: /project/a300/channel_z.rev1 sheet1 © rebuild for www.amigawiki.org · for private use only VCC VCC E133 97 XCLK C28MHz 95 1 2 XCLK 2 1 28MHz 14 14 14 14 20 * 98 XCLKEN_ U20 68 2 2 2 2 _XCLKEN 35 E124 1 2 Vcc1 XC1 Vcc1 XC2 Vcc1 XC3 Vcc1 Vcc1 XC9 CCK_4 CC@4 E131 68 2 1 22pF Channel Z XU1 XU2 XU3 U26X XU9 3 1 2 94 0.047uF 0.047uF 0.047uF 0.22uF OUT OSC Gnd1 1 Gnd1 1 Gnd1 1 Gnd1 Gnd1 1 X1 2 1 CCK 36 1 7 7 7 7 28.63636MHz 68 * 10 OSCILLATOR 470 BUDGIE E121 1 2 CPUCLK 90 CPUCLK R100 27 2 1 * 2 E122 391425 1 2 CPUCLK_A CDAC_ 91 27 2 1 * 10/10/92 VCC Note: PAL uses 28.37516 MHz C7MHz 92 E126 D(31:0) CLOCK PART 1 2 CCK_A E128 27 2 1 22pF 1 2 CCKQ_A A(23:0) 27 2 1 22pF 38 E123 1 2 7MHz NC 7MHz 27 2 1 22pF* FC(2:0) 37 E125 1 2 _CDAC NC _CDAC 27 2 1 22pF 20 35 40 E127 1 2 A20 CCK CCK 19 59 A19 27 2 1 22pF 18 77 39 E129 1 2 A18 CCKQ CCKQ 17 76 U2 2 1 A17 27 22pF FC2 12 2 75 OOPS! 16 A16 FC1 11 1 15 74 34 U1 A15 SCLK SCLK FC0 10 0 14 73 A14 13 72 A13 14MHz 36 15 _CDIS All this stuff serves to correct one minor Gayle bug 12 71 14MHz _CDIS A12 and a number of Alice deficiencies not yet corrected. 11 70 A11 10 69 78 A10 _LPEN _FIRE1 A23 97 23 9 68 A9 A22 96 22 Assuming the changes are implemented in the production 8 67 81 _BOSS A8 _HSYNC _HSYNC A21 95 21 Gaule chip, then all this sillyness is best erased... 7 66 A7 1 _BR A20 94 20 6 65 79 _BR A6 _VSYNC _VSYNC A19 93 19 5 64 A5 2 _BG A18 92 18 4 63 80 _BG Reference Old Gayle New Gayle A4 _CSYNC _CSYNC A17 91 17 =========== ========== =========== 3 62 A3 A16 88 16 2 61 A2 A15 87 15 XU1 74F74 none 1 60 A1 DMAL 18 A14 86 14 DMAL A13 85 13 XU2 74F02 none _INTR 17 _IPL(2:0) A12 84 12 _INT3 A11 83 11 41 XU3 74F74 none _NTSC _NTSC 2 67 _IPL2 A10 82 10 8374 1 66 _IPL1 A9 81 9 U26X 74F86 none 0 65 _IPL0 A8 80 8 57 _RAS _RAS MC68EC020 A7 78 7 XJ4 0 Ohm out ALICE A6 77 6 _CAS 54 A5 76 5 _CAS A4 75 4 XJ1 out 0 Ohm _WE 21 A3 74 3 _DWE A2 73 2 XJ2 out 0 Ohm 5 CLK A1 98 1 26 CPUCLK RGA8 A0 99 0 XJ3 out 0 Ohm RGA7 27 8 RGA6 28 7 U26 note 74LS86 RGA5 29 6 D31 27 31 RGA4 30 5 D30 28 30 31 4 VCC RGA3 XU9 D29 29 29 RGA2 32 3 D28 30 28 VCC 33 2 2 XJ4 RGA1 XR9 D27 31 27 1 1K D26 32 26 2 1 2 16R4 R591 D25 33 25 1 11 _EN 16 _AVEC D24 34 24 1K * 56 1 _AVEC DRA9 CPUCLK CLK D23 35 1 51 9 19 23 74LS86 DRA8 P19 _RST 19 _BEER D22 36 22 10 50 8 2 18 _BEER _FPU_SENSE DRA7 _AS P2 P18 D21 37 21 8 49 7 3 P3 P17 17 NC 9 _FPU_MUSH DRA6 _ROMEN 17 _DSACK0 D20 38 20 DRA5 48 6 4 P4 P16 16 NC _DSACK_0 D19 39 19 _INT3 47 5 FC(1) 5 15 DRA4 FC(0) P5 P15 XRDY 18 _DSACK1 D18 40 18 DRA3 46 4 6 P6 P14 14 NC _DSACK_1 D17 41 U26 45 3 A(17) 7 13 17 DRA2 P7 P13 _AVEC D16 42 44 2 A(16) 8 12 16 DRA1 P8 P12 _DSACK_0 9 _RMC D15 45 15 43 1 _DSACK_1 1 2 9 _RMC DRA0 P9 D14 46 14 0 XJ9 0 R_W 25 R_W D13 47 13 D12 48 12 XU3 DRD15 83 23 _AS D11 49 11 74F02 VCC DRD14 84 31 _AS D10 50 9 XU2 1 10 74F74 DRD13 30 24 _DS D9 51 9 10 11 10 DRD12 2 29 _DS D8 53 8 13 12 9 3 8 D _S Q NC DRD11 28 OOPS! - 32-bit / slow ROM 13 SIZE0 D7 54 7 12 DRD10 4 27 SIZE_0 D6 55 6 5 26 XU2 74F02 DRD9 14 SIZE1 D5 56 5 DRD8 6 25 XJ9 in - add ROM wait SIZE_1 D4 60 4 11 CLK 8 7 24 CCK _Q DRD7 D3 61 3 _C 8 23 1 DRD6 6 _RESET D2 62 2 22 9 22 13 R_W DRD5 _RST D1 63 10 1 XJ2 DRD4 21 22 _HALT D0 64 0 VCC 11 20 _HLT * 2 DRD3 RGA(8:1) 16 _RESET DRD2 12 19 DRD1 13 18 DRD0 14 17 DRA(10:0) _INT3 16 XU3 VCC U26X DRD(31:0) VCC XU2 _RAMEN _REGEN _BLS _DBR 4 74F74 5 74F02 10 22 2 5 2 8 4 25 23 19 20 A4 4 D _S Q A3 23 3 6 1 9 4 24 2 3 _RAMEN _FPU_SENSE _SENSE A2 74F02 74LS86 1 A1 25 1 U0 26 3 CLK 6 _REGEN A0 CCK _Q XU2 VCC _C XJ3 33 31 * 2 _BLS D31 1 18 _SIZE D30 34 30 D29 35 29 VCC D28 36 28 _DBR MC68881 D27 37 27 E114 _FPU_CS 29 _CS D26 38 26 1 2 _OEB D25 39 25 68 2 1 22pF D24 40 24 32 31 30 29 28 D23 42 23 D22 44 22 31 _DSACK0 D21 45 21 31 54 D15 22 _BLS _DBR _OEB C14M D20 46 20 30 55 D14 32 47 19 29 56 _RAMEN _REGEN 23 _DSACK1 D19 D13 CCK D18 48 18 28 57 D12 D17 49 17 27 58 D11 28 R_W D16 50 16 26 59 D10 _SENSE 64 _FPU_MUSH D15 54 15 25 60 D9 U5 21 55 14 VCC 24 61 65 _AS D14 4 D8 _FPU_CS _FPU_CS D13 56 13 20 57 2 5 _DS D12 12 D _S Q D11 58 11 23 53 A23 _WIDE 68 _WIDE D10 59 10 22 52 A22 60 9 21 51 21 1 2 E113 D9
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