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Minimizing Short-Circuit Current Amplitude and Pulse Width When Hot-Swap Controller Output Is Shorted

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Minimizing Short-Circuit Current Amplitude and Pulse Width When Hot-Swap Controller Output Is Shorted Maxim > Design Support > Technical Documents > Application Notes > Circuit Protection > APP 2694 Maxim > Design Support > Technical Documents > Application Notes > Hot-Swap and Power Switching Circuits > APP 2694 Keywords: hot-swap, minimizing short-circuit, hot swap controller, current amplitude, short circuit, current spike APPLICATION NOTE 2694 Minimizing Short-Circuit Current Amplitude and Pulse Width When Hot-Swap Controller Output is Shorted Sep 11, 2003 Abstract: When a hot-swap controller's output is short circuited, the internal circuit-breaker function trips to open the circuit. But initial current flow may be several hundred amps before the internal circuit breaker responds. Typical hot-swap controller circuit-breaker delay time may be 200–400ns, and gate turn-off time may be 10-50microseconds due to limited gate pull-down current. Meanwhile, a high short- circuit current flows. A simple external circuit, described in the application note, can minimize the initial current spike and terminate the short circuit in 200–500ns. Typical Hot-Swap Circuit Let's look at a typical +12V 6A hot-swap control circuit using the MAX4272 (Figure 1). Examining the MAX4272 specifications, we see that it contains slow and fast comparators with trip thresholds of 50mV and 200mV, respectively (43.5–56mV and 180–220mV tolerances over temperature). Applying a 1.5–2.0 multiplier usually placed on operating-current to trip-current ratio, we select RSENSE = 5mΩ. Allowing for a 5% tolerance on RSENSE, the trip current range would be 8.28–11.76A for the slow comparator for overload conditions, and 34–46.2A for the fast comparator when a short occurs. Page 1 of 9 Figure 1. Typical hot-swap controller circuit. The minimum slow-comparator trip point is 38% above normal operating current, and the fast-trip threshold is suitable for short-circuit trip at 6–8 times operating current. The 350ns fast comparator delay means that the initial short-circuit current spike is limited only by the circuit resistances during this period. The current trails off slowly thereafter because the 3mA gate pull- down current limits MOSFET M1's 3–4nF gate capacitance discharge rate until complete interruption of the short circuit. Short-circuit current decreases slowly in the 15–40µs while the gate is being pulled from 19V to near ground. Peak Short-Circuit Current Peak current during the initial 350ns period depends upon: (a) source ESR, (b) short-circuit quality, (c) value of RSENSE, (d) M1's RDS(ON), and (e) M1's ID(ON). Assigning approximate best-case practical values to these, we have a total short-circuit resistance of (Source ESR ≈ 4mΩ) + (Short Circuit ≈ 3mΩ) + (RSENSE = 5mΩ) + (RD(ON) ≈ 4mΩ) ≈ 16mΩ. This could produce a brief peak ISC ≈ 750A, depending upon the energy storage capacity of the power source (750A would discharge a low ESR backplane with 2200µF capacitor by only 340mV in 1µs). In this case, the actual peak ISC would probably be limited to ≈400A by M1's ID(ON). ID(ON) is dependent upon VGS so it is instructive to examine the circuit to determine the gate-source voltage during this period. The MAX4272 contains an internal charge pump that sets operating gate voltage at about 7V above VIN. Thus VGS = 7V when the MOS is ON. A secondary effect of the short is that it actually increases VGS. Consider that the short circuit places a voltage step - equal to a part of the full input voltage - across drain-source of M1. As M1's RD(ON) is about 1/3 of the total estimated short-circuit resistance, ≈1/3 of the 12V step is applied as VDS. This step is partially transferred to the gate by the voltage divider action of cdg from drain to gate and cgs from gate to source. Suitable calculations would indicate this additional ΔVGS to be 300–500mV, but measurements taken during short-circuit conditions indicate that is may be as high as ΔVGS = +3V. By now it is probably clear that a good quality short circuit will cause several hundred amps to flow for several microseconds to tens of microseconds. We may wish to limit the peak Isc to perhaps 50A for < 1µs, but that is impractical without adding a very fast comparator and gate pull-down circuit. We can, however, consider some simple circuit modifications. Page 2 of 9 1. We can limit the period of the short circuit to ≤ ½µs by adding a simple external circuit to speed the gate discharge while current is restrained by ID(ON) to several hundred Amperes for the first 350ns response time of the internal fast comparator, or 2. We can limit the peak Isc to somewhere in the 100A range for a period ≤ 200ns with a slightly more complex external circuit. Fast Gate Pull-Down Circuit Limits Duration of High Short-Circuit Current Duration of the high-current short-circuit current can be minimized simply by adding a PNP Darlington transistor Q1 as shown in Figure 2. Diode D1 allows the gate to be charged normally at turn-on, but the controller's 3mA gate-discharge current is redirected to the base of Q1 at turn-off. Q1 then acts to quickly discharge the gate in ≈100ns. The high-current portion of the short circuit is thus limited to only a bit more than the 350ns fast-comparator delay time. Figure 2. Hot-swap controller with fast gate pull-down. Fast Current-Limiting Circuit The short-circuit current can be limited to ≈100A for < 200ns with the circuit shown in Figure 3. The PNP transistor Q1a - triggered when the voltage across Rsense reaches ≈600mV - drives NPN transistor Q1b to quickly discharge M1's gate capacitance. Page 3 of 9 Figure 3. Hot-swap controller with fast short-circuit peak current limiting. C2 is placed across M1 gate to source to further reduce the positive transient step voltage applied to the gate during a short circuit; its value may be anywhere from 10nF to 100nF. Zener diode D1 is added to limit VGS to something less than the 7V available from the MAX4272. Although the Zener diode is rated 5.1V when biased at 5mA, it will limit VGS to ≈3.4V in this circuit because only 100µA of gate charging (Zener bias) current is available from the MAX4272. The limited VGS lowers ID(ON) - at some expense to RD(ON), as the data sheet shows 5mΩ at 3.4V and 3mΩ at 7V - and allows quicker turn off of M1. Zener D1 and capacitor C2 could also be employed to some advantage in the circuit of Figures 1 & 2 to reduce ID(ON) during the short circuit. Test Methods - Creating a Short-Circuit What could be simpler than creating a short-circuit? There is at least one in every British roadster. But a short-circuit of sufficient quality and repeatability for testing turns out to be a bit more challenging. Several methods of creating a short circuit were evaluated for this experiment. Mechanical switches invariably produce bouncing contact closures over a several-millisecond period. A rotary multi-leaf switch would seem to hold some promise, but one wonders about repeatability as the contacts erode, due to arcing from several high-current closures. High-current relay contacts also produce bouncing contact closure and exhibit variable contact resistance during closure. Silicon controlled rectifiers evaluated had a less-than-satisfactory current rate of rise. High-current mercury-displacement relays were expected to be the best method, but the results were not satisfactory. A 60A 600V mercury relay with specified 4mΩ resistance was found to have an initial resistance of 40mΩ at contact initiation, with leisurely relaxation to 4mΩ over a 15µs period as the current pulse progressed. Manual manipulation of a shorting link delivers a haphazard, intermittent, and non-repeatable contact - perhaps closest to the British roadster ideal! However, a very steep current wavefront can be achieved. In the end, this was the most effective (and economical) method, although contact erosion limited the number of closures with repeatable results. Page 4 of 9 The most promising lab-quality method is to use multiple parallel-wired low-RD(ON) NMOS transistors driven from multiple high-output CMOS Schmidt line drivers. This route was not pursued because of limited time and resources. A true low-resistance short circuit with a steep current wavefront is inordinately difficult to produce consistently in the laboratory by mechanical means. And this will almost certainly be true of the inadvertent short circuit to be experienced in an operating circuit. A typical manually-created short circuit will create capacitor-discharge current and voltage waveforms like those shown in Figure 4. The upper curve recording short-circuit output voltage at 5V/div. shows the capacitor to be less than half discharged over most of the time scale (25µs/div.). The lower curve recording short circuit current at 25A/div. clearly shows the intermittent nature of the contact. Figure 4. Ragged mechanical short-circuit waveforms. Nor is it easy to create a power source with an ESR below 5mΩ. Nevertheless, significant effort was expended to create a low-ESR voltage source of 4–5mΩ where careful measurement showed a voltage drop of 440mV during a 100A short circuit. This voltage source utilized a 5500µF computer-grade electrolytic, a 3.3µF multi-layer ceramic, and six 100µF specialty polymer aluminum electrolytic capacitors in parallel mounted directly at the circuit input driven from a 10A power supply. Short-Circuit Current Waveforms The unaltered circuit of Figure 1 exhibited a short-circuit current waveform as shown in Figure 5. The waveform appears inverted because the measurement was made of voltage across current-sense resistor RS with the oscilloscope ground at the +12V input terminal of the test circuit.
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