Design of High-Speed, Low-Power, Nyquist Analog-To-Digital Converters
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Linköping Studies in Science and Technology Thesis No. 1423 Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters Timmy Sundström LiU‐TEK‐LIC‐2009:31 Department of Electrical Engineering Linköping University, SE‐581 83 Linköping, Sweden Linköping 2009 ISBN 978‐91‐7393‐486‐2 ISSN 0280‐7971 ii Abstract The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs while analog circuits designed in the same process have not been able to utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog ‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has to offer. This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters and their lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for low‐accuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results. The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐ power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power. iii iv The concept of low‐accuracy components is taken to its edge in the second ADC which does not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity. Preface This licentiate thesis presents my research during the period March 2006 to July 2009 at the Electronic Devices group, Department of Electrical Engineering, Linköping University, Sweden. The following papers are included in the thesis: • Paper I – Timmy Sundström, Boris Murmann and Christer Svensson, “Power Dissipation Bounds for High‐Speed Nyquist Analog‐to‐Digital Converters,” in IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 56, No. 3, pp. 509‐518, March 2009. • Paper II ‐ Timmy Sundström and Atila Alvandpour, ”A Kick‐back Reduced Comparator for a 4‐6‐bit 3‐GS/s Flash ADC in a 90nm CMOS Process, “ in Mixed Design of Integrated Circuits and Systems, MIXDES, Ciechocinek, Poland, 21‐23 June 2007. • Paper III ‐ Timmy Sundström and Atila Alvandpour, ”A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS, “ accepted for publication in Journal of Analog Integrated Circuits and Signal Processing, Springer, August 2009. • Paper IV ‐ Timmy Sundström and Atila Alvandpour, ”Utilizing Process Variations for Reference Generation in a Flash ADC, “ in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, pp. 364‐368, May 2009. v vi The research has also generated the following peer‐reviewed publications which are not included in the thesis: • Timmy Sundström and Atila Alvandpour, “A comparative analysis of logic styles for secure IC's against DPA attacks, “ in Proceedings of the 23rd Norchip conference, Oulu, Finland, Nov 21‐22, 2005, pp 297 ‐ 300. • Timmy Sundström, Behzad Mesgarzadeh, Mattias Krysander, Markus Klein, Ingemar Söderquist, Anneli Crona, Torbjörn Fransson and Atila Alvandpour, “Prognostics of Electronic Systems through Power Supply Current Trends, “ in International Conference on Prognostics and Health Management 2008, PHM2008. • Timmy Sundström and Atila Alvandpour, “A 2.5‐GS/s 30‐mW 4‐bit Flash ADC in 90nm CMOS,” in Proceedings of the 26rd Norchip conference, Tallinn, Estonia, Nov 16‐17, 2008, pp 264 ‐ 267. Abbreviations ADC Analog‐to‐digital converter AGC Automatic gain control CMOS Complementary metal‐oxide‐semiconductor DNL Differential non‐linearity DR Dynamic range INL Integral non‐linearity LSB Least significant bit LUT Look‐up table MLSD Maximum‐likelihood sequence detection MMF Multimode fibre MSB Most significant bit PCM Pulse‐coded modulation PCB Printedd circuit boar PLL Phase‐locked loop SAR Successive approximation register SINAD Signal to noise and distortion ratio vii viii SNDR Signal to noise and distortion ratio SNR Signal to noise ratio UWB Ultra‐wideband Acknowledgments I would especially like to thank the following persons for their support and encouragement. • My supervisor Professor Atila Alvandpour, for the support and guidance and for keeping me focused on that which is relevant. • Professor Christer Svensson for all valuable discussions and insight. • Dr. Martin Hansson for the great collaboration with tape‐outs and teaching and for being a great friend. • M.Sc. Jonas Fritzin for your great friendship and support. • Dr. Henrik Fredriksson and Dr. Stefan Andersson for all the valuable technical discussions. • Our secretary Anna Folkesson for helping with the non‐technical aspects of Dbeing a Ph. student. • Research Engineer Arta Alvandpour for his assistance in a wide variety of problems. • All the past and present members of the Electronic Devices research group especially, Ass. Prof. Jerzy Dabrowski, Ass. Prof. Behzad Mesgarzadeh, Adj. Prof. Aziz Ouacha, Adj. Prof. Ted Johansson, Dr. Peter ix x Caputa, Dr. Håkan Bengtsson, , Dr. Rashad Ramzan, Dr. Naveed Ahsan, Dr. Christer Jansson, Dr. Ingemar Söderquist, Dr. Sriram Vangal, M.Sc. Shakeel Ahmad, M.Sc. Ali Fazli, M.Sc. Dai Zhang and M.Sc. Amin Ojani. • All my friends for enriching my out‐of‐work life. • My family, especially my parents for all the love and support. • Finally I would like to thank Camilla for all the patience and love, and for always being there for me. Timmy Sundström Linköping, October 2009 Table of Contents Abstract iii Preface v Abbreviations vii Acknowledgments ix List of Figures xv Part I Design of High Speed ADCs 1 Chapter 1 Introduction 3 1.1 Introduction to Analog‐to‐Digital Converters .................................. 3 1.2 Brief History and Trends .................................................................. 3 1.3 Applications ..................................................................................... 4 1.3.1 Ultra‐Wideband Radio .................................................................................. 4 1.3.2 Serial‐Link Applications ................................................................................. 5 1.4 Motivation and Scope of the Thesis ................................................. 5 1.5 Organization of the Thesis ............................................................... 7 1.6 References ....................................................................................... 7 xi xii Chapter 2 Analog‐to‐Digital Conversion Basics 9 2.1 The Analog‐to‐Digital Converter ...................................................... 9 2.2 Quantization Error ........................................................................... 9 2.3 Static Errors ....................................................................................12 2.4 Dynamic Errors ...............................................................................13 2.5 References .....................................................................................14 Chapter 3 High‐Speed ADC Architectures 15 3.1 Flash ADCs ......................................................................................16 3.1.1 Inherent Sample and Hold .......................................................................... 17 3.1.2 Flash Decoders ............................................................................................ 18 3.1.3 Flash ADC Performance .............................................................................. 18 3.2 Interpolating and Folding ADCs .....................................................19 3.2.1 Folding ADC Performance ........................................................................... 21 3.3 Successive Approximation and Algorithmic ADCs ..........................21 3.3.1 Redundancy or Reduced Radix ................................................................... 23 3.3.2 Performance of Successive Approximation ADCs ....................................... 24 3.4 Pipeline ADCs .................................................................................24 3.4.1 Pipeline ADC Performance .......................................................................... 26 3.5 Interleaved ADCs............................................................................26 3.5.1 Performance of Interleaved ADCs .............................................................. 27 3.6 References .....................................................................................28 Chapter 4 The CMOS Process and its Limitations 33 4.1 Effects and Limitations due to Scaling ...........................................33 4.1.1 Reduced Supply Voltage ............................................................................