ACDC: Towards a Universal Mutator for Benchmarking Heap Management Systems
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Quantifying the Performance of Garbage Collection Vs. Explicit Memory Management
Quantifying the Performance of Garbage Collection vs. Explicit Memory Management ¤ Matthew Hertz Emery D. Berger Computer Science Department Dept. of Computer Science Canisius College University of Massachusetts Amherst Buffalo, NY 14208 Amherst, MA 01003 [email protected] [email protected] ABSTRACT physical memory is scarce, paging causes garbage collection to run Garbage collection yields numerous software engineering benefits, an order of magnitude slower than explicit memory management. but its quantitative impact on performance remains elusive. One Categories and Subject Descriptors can compare the cost of conservative garbage collection to explicit memory management in C/C++ programs by linking in an appro- D.3.3 [Programming Languages]: Dynamic storage management; priate collector. This kind of direct comparison is not possible for D.3.4 [Processors]: Memory management (garbage collection) languages designed for garbage collection (e.g., Java), because pro- General Terms grams in these languages naturally do not contain calls to free. Experimentation, Measurement, Performance Thus, the actual gap between the time and space performance of explicit memory management and precise, copying garbage collec- Keywords tion remains unknown. oracular memory management, garbage collection, explicit mem- We introduce a novel experimental methodology that lets us quan- ory management, performance analysis, time-space tradeoff, through- tify the performance of precise garbage collection versus explicit put, paging memory management. Our system allows us to treat unaltered Java programs as if they used explicit memory management by relying 1. Introduction on oracles to insert calls to free. These oracles are generated Garbage collection, or automatic memory management, provides from profile information gathered in earlier application runs. -
Linux Multicore Performance Analysis and Optimization in a Nutshell
LLiinnuuxx MMuullttiiccoorree PPeerrffoorrmmaannccee AAnnaallyyssiiss aanndd OOppttiimmiizzaattiioonn iinn aa NNuuttsshheellll PPhhiilliipp MMuuccccii mmuuccccii aatt eeeeccss..uuttkk..eedduu NNOOTTUURR 22000099 TTrroonnddhheeiimm,, NNoorrwwaayy NOTUR2009 Philip Mucci, Multicore Optimization 1 SScchheedduullee ● 10:15 Begin ● (1:00) ● 11:15 – 11:30 Coffee ● (1:30) ● 13:00 – 14:00 Lunch ● (2:00) ● 16:00 Finish ● 18:00 Beer NOTUR2009 Philip Mucci, Multicore Optimization 2 OOuuttlliinnee ● Commentary ● Programming Models ● HW/SW Overview ● Multicore ● Working With the Optimization Compiler ● Performance Analysis ● Single Core Optimization NOTUR2009 Philip Mucci, Multicore Optimization 3 IInniittiiaall CCoommmmeennttaarryy NOTUR2009 Philip Mucci, Multicore Optimization 4 OOppttiimmiizzaattiioonn iiss aann AArrtt FFoorrmm ● As such, this tutorial is partially subjective. ● Expect some contradictions to your experience(s). – Don't panic. ● Negative comments (on the tutorial) are welcomed (afterwards). – Please include “bug fixes”. – mucci at eecs.utk.edu NOTUR2009 Philip Mucci, Multicore Optimization 5 WWhhaatt''ss ssoo ssppeecciiaall aabboouutt MMuullttiiccoorree?? ● Parallel programming is somewhat easier... – Shared address space means direct access to data. ● Multicore is a great latency hiding mechanism. – Most computers are doing many different activities at once. (What about us?) ● We really can't get much faster without liquid cooling. ● Multicore appears to lower power and cooling requirements per FLOP. NOTUR2009 Philip Mucci, Multicore -
Predicting Execution Times with Partial Simulations in Virtual Memory Research: Why and How
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) Predicting Execution Times With Partial Simulations in Virtual Memory Research: Why and How Mohammad Agbarya∗ Idan Yaniv∗ Jayneel Gandhi Dan Tsafrir Technion – Israel Institute of Technology VMware Research Technion & VMware Research Abstract—Computer architects frequently use cycle-accurate simulations, which incur heavy overheads. Recently, virtual mem- workload W full simulator runtime ory studies increasingly employ a lighter-weight methodology (e.g., gem5) that utilizes partial simulations—of only the memory subsystem— of processor P whose output is fed into a mathematical linear model that predicts execution runtimes. The latter methodology is much faster, but its accuracy is only assumed, never rigorously validated. workload W partial simulator TLB metrics runtime model runtime We question the assumption and put it to the test by developing (e.g., only TLB) for processor P e.g., the TLB Mosalloc, the Mosaic Memory Allocator. Mosalloc backs the of processor P and workload W virtual memory of applications with arbitrary combinations of miss-rate 4KB, 2MB, and 1GB pages (each combination forms a “mosaic” of pages). Previous studies used a single page size per execution Figure 1: Partial vs. full (cycle-accurate) simulation. (either 4KB or 2MB) to generate exactly two execution samples, which defined the aforementioned linear model. In contrast, Mosalloc can generate numerous samples, allowing us to test processor P while experiencing a TLB miss rate of M (where instead of assume the model’s accuracy. We find that prediction M can be the output of a partial simulation), then the runtime of errors of existing models can be as high as 25%–192%. -
Quantifying and Improving the Performance of Garbage Collection
QUANTIFYING AND IMPROVING THE PERFORMANCE OF GARBAGE COLLECTION A Dissertation Presented by MATTHEW HERTZ Submitted to the Graduate School of the University of Massachusetts Amherst in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY September 2006 Computer Science °c Copyright by Matthew Hertz 2006 All Rights Reserved QUANTIFYING AND IMPROVING THE PERFORMANCE OF GARBAGE COLLECTION A Dissertation Presented by MATTHEW HERTZ Approved as to style and content by: Emery D. Berger, Chair J. Eliot B. Moss , Member Kathryn S. McKinley, Member Scott F. Kaplan, Member Andras Csaba Moritz, Member W. Bruce Croft, Department Chair Computer Science To Sarah for reminding me of everything I can do and to Shoshanna for inspiring me to do more. ACKNOWLEDGMENTS I am most grateful to my advisor, Emery Berger, for everything he has done throughout this thesis. I appreciate his guidance, suggestions, and inspiration. I feel especially fortu- nate for the patience he has shown with me throughout all the twists and turns my life took getting through this dissertation. I must also thank Eliot Moss and Kathryn McKinley for their leadership and support. I will be forever grateful that they took a chance on a student with a less-than-stellar aca- demic record and provided me with a fertile, inspiring research environment. They are both very knowledgeable and I benefited from our discussions in a myriad of ways. They have also served as members of my committee and I appreciate their helpful comments and sug- gestions. Thanks also to Scott Kaplan, another member of my committee, for his advice and feedback. -
Efficient Intra-Operating System Protection Against Harmful Dmas
Efficient Intra-Operating System Protection Against Harmful DMAs Moshe Malka, Nadav Amit, and Dan Tsafrir, Technion—Israel Institute of Technology https://www.usenix.org/conference/fast15/technical-sessions/presentation/malka This paper is included in the Proceedings of the 13th USENIX Conference on File and Storage Technologies (FAST ’15). February 16–19, 2015 • Santa Clara, CA, USA ISBN 978-1-931971-201 Open access to the Proceedings of the 13th USENIX Conference on File and Storage Technologies is sponsored by USENIX Efficient Intra-Operating System Protection Against Harmful DMAs Moshe Malka Nadav Amit Dan Tsafrir Technion – Israel Institute of Technology Abstract this mode, the VM directly programs device DMAs using Operating systems can defend themselves against mis- its notion of (guest) “physical” addresses. The host uses behaving I/O devices and drivers by employing intra-OS the IOMMU to redirect these accesses to where the VM protection. With “strict” intra-OS protection, the OS uses memory truly resides, thus protecting its own memory the IOMMU to map each DMA buffer immediately before and the memory of the other VMs. With inter protec- the DMA occurs and to unmap it immediately after. Strict tion, IOVAs are mapped to physical memory locations protection is costly due to IOMMU-related hardware over- infrequently, only upon such events as VM creation and heads, motivating “deferred” intra-OS protection, which migration, and host management operations such as mem- trades off some safety for performance. ory swapping, deduplication, and NUMA migration. Such We investigate the Linux intra-OS protection mapping mappings are therefore denoted persistent or static [57]. -
Heapshield: Library-Based Heap Overflow Protection for Free
HeapShield: Library-Based Heap Overflow Protection for Free Emery D. Berger Dept. of Computer Science University of Massachusetts Amherst Amherst, MA 01003 [email protected] Abstract scalable multiprocessor memory management [6, 21]. It has also While numerous approaches have been proposed to prevent stack been used as the basis for the default memory manager in the overflows, heap overflows remain both a security vulnerability and FreeBSD operating system [19]. a frequent source of bugs. Previous approaches to preventing these We show here how we can apply this heap layout to ensure that overflows require source code or can slow programs down by a library functions never cause heap overflows. Our approach incurs factor of two or more. We present HeapShield, an approach that no space overhead beyond that used to manage the heap because it prevents all library-based heap overflows at runtime. It works with relies only on data structures already in place to support ordinary malloc free arbitrary, unaltered binaries. It incurs no space overhead and is memory allocation operations ( and ). We use this efficient, imposing minimal impact on real application performance heap layout to efficiently implement a function that computes the (2% on average). remaining size of any allocated buffer, and then replace all unsafe library functions with safe variants that silently truncate overflows. HeapShield imposes no perceivable performance impact on 1. Introduction these library functions, and it adds no overhead to any other as- The C library contains a host of library calls that present well- pect of program execution. It is also orthogonal to techniques that known security vulnerabilities. -
Vysok´E Uˇcení Technick´Ev Brnˇe
VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ INTELIGENTN´ICH SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF INTELLIGENT SYSTEMS A TOOL FOR ANALYZING PERFORMANCE OF MEM- ORY ALLOCATORS IN LINUX DIPLOMOVA´ PRACE´ MASTER’S THESIS AUTOR PRACE´ Bc. PETR MULLER AUTHOR BRNO 2010 VYSOKEU´ CENˇ ´I TECHNICKE´ V BRNEˇ BRNO UNIVERSITY OF TECHNOLOGY FAKULTA INFORMACNˇ ´ICH TECHNOLOGI´I USTAV´ INTELIGENTN´ICH SYSTEM´ U˚ FACULTY OF INFORMATION TECHNOLOGY DEPARTMENT OF INTELLIGENT SYSTEMS NASTROJ´ PRO ANALYZU´ VYKONU´ ALOKATOR´ U˚ PAMETIˇ V OPERACNˇ ´IM SYSTEMU´ LINUX A TOOL FOR ANALYZING PERFORMANCE OF MEMORY ALLOCATORS IN LINUX DIPLOMOVA´ PRACE´ MASTER’S THESIS AUTOR PRACE´ Bc. PETR MULLER AUTHOR VEDOUC´I PRACE´ Doc. Ing. TOMA´ Sˇ VOJNAR, Ph.D. SUPERVISOR BRNO 2010 Abstrakt Tato diplomov´apr´ace prezentuje n´astroj, kter´yumoˇzˇnujeanal´yzuvlastnost´ıdynamick´ych pamˇet'ov´ych alok´ator˚use zamˇeˇren´ımna jejich v´ykon. Pr´aceidentifikuje d˚uleˇzit´ev´ykonnostn´ı metriky pamˇet'ov´ych alok´ator˚ua tak´efaktory prostˇred´ıa programu, kter´etyto metriky mo- hou ovlivnit. Na z´akladˇetˇechto nalezen´ych metrik byl navrhnut a implementov´ann´astroj, kter´yumoˇznuje jejich sbˇera anal´yzu. N´astroj umoˇzˇnujetvorbu r˚uzn´ych sc´en´aˇr˚upouˇzit´ı alok´ator˚utak, aby bylo moˇzn´eanalyzovat chov´an´ıalok´ator˚uza r˚uzn´ych podm´ınek. Tento n´astroj byl testov´anna nˇekolika dostupn´ych pamˇet'ov´ych alok´atorech se svobodnou licenc´ı. Abstract This diploma thesis presents a tool for dynamic memory allocator analysis, focused on their performance. The work identifies the important memory allocator performance metrics, as well as the environment and program factors influencing these metrics. -
Bilal Shirazi 98107317 CS499 Research Paper: an Analysis of Concurrent Memory Allocators Presented To: Dr
Bilal Shirazi 98107317 CS499 Research Paper: An analysis of concurrent memory allocators Presented To: Dr. Peter Buhr 1 1.0 Introduction: This project examines concurrent dynamic memory-allocation. Dynamic memory-allocation occurs when a program requests storage other than for local variables on the stack. Dynamic memory- allocation and deallocation is made available via programming language statements such as new and delete, or via runtime routines such as malloc and free. Some programming languages provide garbage collection so there is no explicit deallocation. In a concurrent environment, each task has its own stack so allocation and deallocation of local variables never causes contention among tasks. Furthermore, it is rare to share stack storage among tasks. However, heap allocation and deallocation often occurs among tasks via the shared heap-storage area. This shared resource can cause significant contention during allocation and deallocation. Furthermore, allocated heap storage is often passed around among tasks, resulting in shared access. These issues do not exist in a sequential environment. Hence, the demands of dynamic memory allocation are more complex in a concurrent environment and can have a significant effect on the performance of dynamic memory-intensive applications. Therefore, it is crucial to have good dynamic memory-allocation in a concurrent system. 2 2.0 Objectives : The objectives of this research project are: 1. To understand and validate the claims made by the researchers who created the Hoard memory allocator [1], currently considered the best dynamic memory allocator for concurrent systems. 2. To compare the uC++ memory allocator to the Hoard memory allocator. uC++ [3] is a concurrent system for C++. -
0Sim: Preparing System Software for a World with Terabyte-Scale Memories
Session 4A: Huge memories and distributed databases — Now I remember! 0sim: Preparing System Software for a World with Terabyte-scale Memories Mark Mansi Michael M. Swift [email protected] [email protected] University of Wisconsin – Madison University of Wisconsin – Madison Abstract of the Twenty-Fifth International Conference on Architectural Support Recent advances in memory technologies mean that com- for Programming Languages and Operating Systems (ASPLOS ’20), modity machines may soon have terabytes of memory; how- March 16–20, 2020, Lausanne, Switzerland. ACM, New York, NY, USA, 16 pages. https://doi.org/10.1145/3373376.3378451 ever, such machines remain expensive and uncommon today. Hence, few programmers and researchers can debug and pro- totype fixes for scalability problems or explore new system 1 Introduction behavior caused by terabyte-scale memories. Computer memory sizes have grown continuously since the To enable rapid, early prototyping and exploration of sys- dawn of computing. Past designs that rigidly limited the max- tem software for such machines, we built and open-sourced imum amount of memory faced huge difficulties as memory the 0sim simulator. 0sim uses virtualization to simulate the capacity increased exponentially (e.g., IBM’s System/360 had execution of huge workloads on modest machines. Our key an architectural limit of 28MB [11]). This growth trend will observation is that many workloads follow the same control continue as technological advances greatly expand the den- flow regardless of their input. We call such workloads data- sity and decrease the cost of memory. Most recently, Intel’s oblivious. 0sim harnesses data-obliviousness to make huge 3D Xpoint memory supports up to 6TB on a two-socket simulations feasible and fast via memory compression. -
Hoard: a Scalable Memory Allocator For
Hoard: A Scalable Memory Allocator for Multithreaded Applications Ý £ £ Emery D. Berger£ Kathryn S. McKinley Robert D. Blumofe Paul R. Wilson Ý £ Department of Computer Sciences Department of Computer Science The University of Texas at Austin University of Massachusetts Austin, Texas 78712 Amherst, Massachusetts 01003 g femery, rdb, wilson @cs.utexas.edu [email protected] ABSTRACT servers. Many of these applications make intensive use of dynamic Parallel, multithreaded C and C++ programs such as web servers, memory allocation. Unfortunately, the memory allocator is often a database managers, news servers, and scientific applications are be- bottleneck that severely limits program scalability on multiproces- coming increasingly prevalent. For these applications, the memory sor systems [21]. Existing serial memory allocators do not scale allocator is often a bottleneck that severely limits program perfor- well for multithreaded applications, and existing concurrent allo- mance and scalability on multiprocessor systems. Previous alloca- cators do not provide one or more of the following features, all of tors suffer from problems that include poor performance and scal- which are needed in order to attain scalable and memory-efficient ability, and heap organizations that introduce false sharing. Worse, allocator performance: many allocators exhibit a dramatic increase in memory consump- Speed. A memory allocator should perform memory operations tion when confronted with a producer-consumer pattern of object (i.e., malloc and free) about as fast as a state-of-the-art se- allocation and freeing. This increase in memory consumption can rial memory allocator. This feature guarantees good allocator range from a factor of È (the number of processors) to unbounded performance even when a multithreaded program executes memory consumption. -
Copyright by Emery D. Berger 2002
Copyright by Emery D. Berger 2002 The Dissertation Committee for Emery D. Berger certifies that this is the approved version of the following dissertation: Memory Management for High-Performance Applications Committee: Kathryn S. McKinley, Supervisor James C. Browne Michael D. Dahlin Stephen W. Keckler Benjamin G. Zorn Memory Management for High-Performance Applications by Emery D. Berger, M.S., B.S. Dissertation Presented to the Faculty of the Graduate School of The University of Texas at Austin in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy The University of Texas at Austin August 2002 Memory Management for High-Performance Applications Publication No. Emery D. Berger, Ph.D. The University of Texas at Austin, 2002 Supervisor: Kathryn S. McKinley Fast and effective memory management is crucial for many applications, including web servers, database managers, and scientific codes. Unfortunately, current memory managers often do not meet these requirements. These memory managers also do not provide the support required to avoid memory leaks in server applications, and prevent multithreaded applications from scaling on multiprocessor systems. In fact, current memory managers cause some applications to slow down with the addition of more processors. In this thesis, we address these memory management problems for high-performance applications. We develop a memory management infrastructure called heap layers that allows us to compose efficient general-purpose memory managers from components. We show that most custom memory managers achieve slight or no performance improvements over current general-purpose memory managers. We build a hybrid memory manager called reap that combines region-based and general-purpose memory management, sim- plifying memory management for server applications. -
Topic : an Overview Multi-Core Processors - Architecture, Prog
C-DAC Four Days Technology Workshop ON Hybrid Computing – Coprocessors/Accelerators Power-Aware Computing – Performance of Application Kernels hyPACK-2013 Mode-1 : Multi-Core & Mode-2 : ARM Processors Topic : An Overview Multi-Core Processors - Architecture, Prog. Env - Software Threading & Performance Issues & An Overview of ARM Multi-Core Processors Venue : CMSD, UoHYD ; Date : October 15-18, 2013 C-DAC hyPACK-2013 Multi-Core Processors & ARM Processors An Overview 1 An Overview of Multi-Core & ARM Processors Lecture Outline Following topics will be discussed Understanding of Multi-Core Architectures Programming on Multi-Core Processors Tuning & Performance – Software Threading An Overview or ARM Processors – Prog. Env C-DAC hyPACK-2013 Multi-Core Processors & ARM Processors An Overview 2 Part-I : An Overview of Multi-Core Processors History C-DAC hyPACK-2013 Multi-Core Processors & ARM Processors An Overview 3 Multi-Core History Parallel computing has been used for HPCs and networking. PRAM & other shared memory models - Limitations. BSP & LogP (message passing models) were used. – Only for HPC specialists. – Demand complicated system analyze per application. Clusters are becoming popular (NUMA, CC NUMA) HW (Scalability) Constraints force Multicore architectures. Era of frequency race C-DAC hyPACK-2013 Multi-Core Processors & ARM Processors An Overview 4 Multi-Core History No more frequency race The era of multi cores Parallel programming is not easy Split a sequential task into multiple sub tasks Data Parallelism – Task Paralleism Performance Year Pentium Pentium 4 Core Duo (1993) (2000) (2006) C-DAC hyPACK-2013 Multi-Core Processors & ARM Processors An Overview 5 Multi-Core History Moving from Multiple processor on single box (SMP) Multiple Core on Single Chip.