Fuzzy Inference Engi

Blending Methodologies for Optimizing Fuzzy Inference Engine Designs Rob Chapman, Adam F. Gobi and Witold Pedrycz Department of Electrical and Computer Engineering University of Alberta Edmonton, AB T6G 2V4 {rchapman,gobia,pedrycz}@ece.ualberta.ca Abstract -- The software paradigm of writing sequential pro- the rooms, but you can not easily change the number of rooms, gramming tasks executed on a single processor has pervaded turrets or add other novel structures. computers since their dawning. In spite of progress, sequential Our development platform is a granular computer (GC): a execution of certain algorithms remain limited by this paradigm. flexible architecture and methodology for combining software In particular, fuzzy control systems involve fuzzy set operations programs and hardware engines in programmable hardware. which require significant amounts of vector and matrix computa- This ability to blend the domains of software and hardware, as tion. This computation can be considered an inherently parallel task, and performing these operations in software results in ineffi- well as program with data, will be exploited later in the paper. cient execution, severely limiting the use of fuzzy operations in The GC model for programming is a simplified, parameter- real-time systems where fast responses are required. This paper ized processor with no instruction set. As part of a design, will explore solutions to this problem using software, hardware instructions and instruction sequences, known as primitives, and finally a hybrid approach with a proposed computing archi- are either created or included from a library set, and are used to tecture and platform known as a granular computer (GC). construct sequential programs. For speeding up algorithms which have parts that can be parallelized or would benefit from I. INTRODUCTION specific hardware support, new parts can be added to the pro- In the last decade there have been many proposed solutions cessor components and then controlled through new opera- to speed up fuzzy set operations. These include: tions. Even though there are no math operations in hardware, • algorithmic tuning [3][4] such as data driven execution to by using specific logic operations in parallel and in sequence, minimize the number of void computations addition, subtraction, multiplication and division can be simu- • enhanced microcontrollers [1][2][3] with fuzzy hardware lated but they do cost more in cycles than on a microcontroller and fuzzy instructions or fuzzy co-processors with dedicated math hardware. • parameterized hardware [4][5][6] This paper explores architectures and ideas encompassed in While each of these proposed solutions offer benefits, they implementing a fuzzy interface and fuzzy logic operators with all have limitations in some way [3]. These include disadvan- the application being fuzzy control. Using these concepts, we tages in speed, flexibility, support for other system tasks, or the demonstrate how one would use the GC to go about building a number of chips and support hardware required. In this paper, fuzzy inference engine. Results from experiments with our we propose a different approach by blending software and fast fuzzy inference engine are presented, with comparisons to hardware paradigms. industrial platforms offering similar functionality. Our aim is Our novel approach attempts to address these limitations by to have a fuzzy inference engine that offers an unparalleled modeling an FPGA development platform, which offers an combination of optimal speed, flexibility, and size. excellent environment for exploration of fuzzy operations, as a familiar software programming environment. The FPGA plat- II. FUZZY INFERENCE REALIZATION OPTIONS form serves as a fast, compact single chip solution, allowing A fuzzy inference engine consists of three fundamental very powerful integration of hardware with software with the parts[11]: sizes commercially available today and with a big nod to the 1. fuzzification - a single crisp input value is characterized future. The microprocessor has had its peak and the next rise by expressing membership in a family of fuzzy sets in computational power will be from FPGA-like chips. 2. rule evaluation - logical inferences are made from the Conventionally programmed in a hardware language, FPGA fuzzified inputs using t-norms and t-conorms to create programming environments have started to offer embedded fuzzy outputs processors. Xilinix offers up to four 400MHz, embedded IBM 3. defuzzification - fuzzy outputs are coalesced into singular PowerPC 405 Processor hard cores or a soft processing solu- crisp outputs tion with the MicroBlaze™ core. Altera offers the equivalent with an ARM922T™ processor, and the Nios® soft RISC pro- A. Realization Strategies cessor. While this integrates the software programming envi- Given software and hardware designs, there are three basic ronment with an FPGA, it does little to take advantage of it. It ways to realize the fuzzy inference components: is not unlike having a prebuilt castle which you can decorate 0-7803-8376-1/04/$20.00 Copyright 2004 IEEE. • Software - One approach is to define the entire fuzzy B. Granular Computer Platform engine in software. This is appealing in that the design is A granular computer is similar to a conventional processor flexible and quick to turn around and test. It also makes but all aspects are parametrized or optioned. The width of the use of the powerful software programming paradigm. data can be set as needed from 1 bit to as wide as required. The • Hardware - Alternatively, a hardware solution [5][6][8] length of the memory space is definable as well and can can be used where the engine is described using hardware include ROM, RAM and external IO (EIO) sections. EIO is components and the parameters are used to adapt it to the where all external control spaces are made to other hardware specific problem. This, however, is usually supplemented components such as serial peripherals, special execution units, with a microprocessor to take care of all the other tasks attached devices and other GCs. Working data and program required. This approach allows algorithms which operate context are kept on stacks whose depth is also definable. The in parallel to be implemented in parallel, creating a signif- initial instruction set is empty with instructions added as icant speed advantage over the software approach. needed for the computing task at hand. This granularization of • Hybrid - The best approach is a hybrid approach which the processor is where we gain the power of hardware without involves integration of hardware for speed and software sacrificing the power of software. for complexity management. This means mixing a proces- While software and hardware design are well understood, sor with support hardware. GC design is new and will be explored here with detail enough 1) Fuzzy Enhanced Microcontroller for the reader to understand the fundamentals. Eight years ago, Motorola introduced an augmented micro- 1) Multi-Layer Programming processor solution with the production of the 68HC12 [1][2]. A GC is programmed at up to four different levels depending Their projections indicate they will have sold a billion of these on the requirements of the task: processors in the next five years. 1. Operations - VHDL is used to define the default compo- With the HC12 bringing fuzzy logic into the mainstream nents and any extensions to the basic processor architec- embedded market through the use of dedicated on-board logic ture illustrated in Fig. 1. and an augmented instruction set, it makes a good reference 2. Primitives - The components are controlled by a sequence point for alternatives when parameterization is insufficient and of instructions which are composed of parallel operations a change in structure or embedded algorithm is necessary to for the components as illustrated in Fig. 2. solve more complex problems, increase speed, increase inte- 3. Program - At the highest level, programs are built in a con- gration or change precision. ventional manner from primitives and other programs. 2) Granular Computer 4. Compiler - The compiler consists of a Timbre [10] script Software can offer precision, integration and complexity and can be modified to support different GC language con- management but at a sacrifice of speed [3]. By moving one TR - top register FU TR RS level deeper in layers of programmability, from software FU - function unit parameterizing a fixed microprocessor architecture to a matrix DS - data stack of programmable hardware, we gain this increase in all aspects DS ME PC PC - program counter but complexity. Complexity comes at a cost of programmabil- ME - memory ity. The software model supported with the microprocessor IR RS - return stack architecture is a very successful and powerful one that has IR - instruction register grown out of a need to solve problems of a greater degree of complexity that would otherwise be impractical with hardware Figure 1: GC components and data flows. Each component executes an operation every clock cycle. [3] In this moving down one level of programmability, we have Instruction Set lost the ability to solve complex problems, assuming we pro- array of gram hardware. Instead, if we abstract the microprocessor instructions architecture, granulate it by component, parameter and opera- parallel operations tion, then we create a platform with the blending of solutions current=> instruction next = +0 that gives us the programmability of software but the speed of +1 +2 new op1 op2 op3 op4 op5 op6 op7 hardware. This proposed model for hardware computing is referred to as a granular computer (GC). primitive: To illustrate how we may adapt to this new platform, the instruction HC12 model of fuzzy control will be examined and then cop- sequence To components ied onto the GC. Different algorithms, will be presented to explore the flexibility obtained by this proposed platform and Figure 2: Parallel operations are combined to form an instruc- some measurements will be made. tion. Several sequential instructions form a primitive. structs. This would be used to define the executable data B.

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