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Admission Control for Independently-Authored Realtime Applications Admission Control for Independently-authored Realtime Applications by Robert Kroeger Athesis presented to the University of Waterloo in fulfilment of the thesis requirement for the degree of Doctor of Philosophy in Computer Science Waterloo, Ontario, Canada, 2004 c Robert Kroeger 2004 AUTHOR’S DECLARATION FOR ELECTRONIC SUBMISSION OF A THESIS I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. ii Abstract This thesis presents the LiquiMedia operating system architecture. LiquiMedia is specialized to schedule multimedia applications. Because they generate output for a human observer, multimedia applications such as video games, video conferencing and video players have both unique scheduling requirements and unique allowances: a multimedia stream must synchro- nize sub-streams generated for different sensory modalities within 20 milliseconds, it is not successfully segregated until it has existed for over 200 milliseconds and tolerates occasional scheduling failures. LiquiMedia is specialized around these requirements and allowances. First, LiquiMedia synchronizes multimedia tasks by invoking them from a shared realtime timer interrupt. Sec- ond, owing to multimedia’s tolerance of scheduling failures, LiquiMedia schedules tasks based on a probabilistic model of their running times. Third, LiquiMedia can infer per-task models while a user is segregating the streams that the tasks generate. These specializations provide novel capabilities: up to 2.5 times higher utilization than RMS scheduling, use of an atomic task primitive 9.5 times more efficient than preemptive threading, and most importantly, the ability to schedule arbitrary tasks to a known probability of realtime execution without a priori knowledge of their running times. iii Acknowledgements Friends, money and academic advice got me through this thesis. Slowly. All deserve my thanks. First, on the subject of academic advice, I thank my supervisor, Bill Cowan for his guidance, insight and particularly his patience. Also, I thank my committee for their prompt and valuable feedback. As for money, many organizations have supported this research — I am grateful for the support of NSERC, IBM, ITRC and LiquiMedia Inc. Ironically, I am also grateful for the lack of money: the stock crash of 2001 bankrupted my salaried thesis avoidance opportunity. I would have given up long ago without the encouragement of family and friends: many CGL members over the years, Tresidder alumni and the yawners. Of these, special thanks must go out to Ian Bell, Igor Benko, Celine Latulipe, Peter Mayo, Alex Nicolaou and Shinji Sato for (sometimes inadvertently) convincing me to continue. Lastly, thanks to Peter Kokkovas for the totally cool name. iv Trademarks HRV, Java, JMF, JavaBeans, NeWS, VIS, TAAC-1, Solaris and SPARC are trademarks of Sun Microsystems Inc. DirectX, DirectShow, COM, Windows NT, Windows 2000 and Vizact are trademarks of Microsoft Inc. QuickTime, Core Image, Aqua and MacOS X are trademarks of Apple Computer Inc. LiquiMedia, LiquiOS and MVM were trademarks of LiquiMedia Inc. Pentium, SSE and MMX are trademarks of Intel Inc. POSIX and UNIX are trademarks of the X/Open group. WindRiver and VxWorks are trademarks of WindRiver Inc. Virtuoso and Eonic are trademarks of Eonic Systems Inc. Precise is a trademark of Precise Software Technologies. SPARK is a trademark of Realtime Microsystems Inc.. HP, DEC, VMS and Alpha are trademarks of HP Inc. Qualcomm and BREW are trademarks of Qualcomm Inc. Streammaster and Motorola are trademarks of Motorola Inc. TeraLogic is a trademark of TeraLogic Inc. Mwave is a trademark of Texas Instruments Inc. Chromatic is possibly a trademark of ATI Inc. Trimedia is a trademark of Philips Inc. SGI, REACT and IRIX are trademarks or SGI Inc. Harmony is a trademark reserved for the Crown. v Contents 1 Introduction 1 1.1InformationStreams................................. 1 1.2SpecializedDesign.................................. 3 1.2.1 TheRecitalModel.............................. 4 1.2.2 DesignPrinciples............................... 4 1.3Applications...................................... 8 1.3.1 OntheDesktop................................ 8 1.3.2 TheEmbeddedSpace............................ 11 1.4LiquiMediaOverview................................. 13 1.5Organization..................................... 15 2 The RTOS Design Space 17 2.1TaxonomyOverview................................. 18 2.2TaskAbstraction................................... 21 2.2.1 Performers.................................. 22 2.2.2 PreemptiveThreads............................. 23 2.2.3 Non-preemptiveThreads........................... 23 2.3DeadlineSensitivity................................. 24 2.4Externalization.................................... 25 2.4.1 Time-Triggered................................ 26 2.4.2 Event-Triggered............................... 26 vi 2.5Scheduling....................................... 27 2.5.1 DistributedScheduling............................ 28 2.5.2 StaticPriorityScheduling.......................... 28 2.5.3 EDFScheduling............................... 29 2.5.4 Rate-BasedScheduling............................ 30 2.6AdmissionControl.................................. 33 2.6.1 AdmissionControlOpportunities...................... 33 2.6.2 AbsentAdmissionControl.......................... 34 2.6.3 Declarative Admission Control . 34 2.6.4 StatisticalAdmissionControl........................ 34 2.6.5 MechanicalAdmissionControl....................... 35 2.7ProcessorPartitioning................................ 35 2.7.1 HardwarePartitioning............................ 35 2.7.2 HierarchicalPartitioning........................... 36 2.7.3 TaskPartitioning............................... 36 2.8Inter-processCommunication............................ 36 2.8.1 DivisibleTaskIPC.............................. 37 2.8.2 AtomicTaskIPC............................... 37 2.9Summary....................................... 38 3 Previous Work 39 3.1EmbeddedOperatingSystems............................ 39 3.1.1 CyclicExecutives............................... 40 3.1.2 RMSOperatingSystems........................... 42 3.2 Hardware Partitioning Operating Systems . 43 3.3MediaGenerationFrameworks........................... 46 3.4DistributedSchedulingOperatingSystems..................... 50 3.5HierarchicalPartitioningOperatingSystems.................... 52 3.6TaskPartitioningOperatingSystems........................ 53 vii 3.6.1 RealtimeMachandDescendants...................... 53 3.6.2 Rialto..................................... 55 3.6.3 YARTOSandDiRT............................. 57 3.6.4 SMART.................................... 58 3.6.5 BERT..................................... 58 3.6.6 Summary................................... 58 3.7StatisticalAdmissionControl............................ 59 3.7.1 DSACOSs.................................. 59 3.7.2 ESACOSs.................................. 61 3.8Summary....................................... 62 4 Architecture Overview 65 4.1TaxonomicPosition................................. 66 4.2SoftRealtime..................................... 69 4.3HierarchicalPartitioning............................... 70 4.4RealtimePerformers................................. 72 4.4.1 PracticalandNatural............................ 72 4.4.2 Efficient.................................... 72 4.5Non-realtimeThreads................................ 73 4.6 ConduitIPC ..................................... 73 4.7Task-partitionedPerformers............................. 75 4.8ScheduleGraph.................................... 75 4.9StatisticalAdmissionControl............................ 78 4.9.1 LifetimeAdmissionControl......................... 79 4.10InstantaneousAdmissionControl.......................... 81 4.11 Satisfies Fundamental Principles . 83 4.12Summary....................................... 84 viii 5 Implementation 85 5.1ExtendingSolaris................................... 85 5.2ImplementationStructures.............................. 88 5.2.1 Conduits . 88 5.2.2 ExceptionHandlers............................. 88 5.2.3 Applications................................. 89 5.2.4 MemoryManagement............................ 89 5.2.5 TimingandMeasurement.......................... 90 5.3ImplementationStrategy............................... 91 5.4 The Scheduler Simulator . 91 5.5Summary....................................... 92 6 Performance Measurements 93 6.1ApparatusandMethodology............................ 93 6.1.1 Metrics.................................... 93 6.1.2 OverviewofTests.............................. 95 6.1.3 TestPerformers................................ 95 6.1.4 RealtimeTestDetails............................ 101 6.1.5 Summary................................... 104 6.2Partitioning...................................... 104 6.3SynchronousRealtime................................ 105 6.4 Ultra-Fine Granularity Performers . 111 6.4.1 Conductor and Performer Overhead . 113 6.4.2 Comparison.................................. 113 6.5Modularity...................................... 115 6.5.1 Convergence................................. 116 6.5.2 InstantaneousAdmissionControl...................... 123 6.5.3 LifetimeAdmissionControl......................... 123 6.5.4 FeedbackandScheduleConvergence.................... 126 6.6Summary....................................... 128 ix 7 Future Work 129
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