! ! Development!Board!
Reference Manual
Date: September 3, 2015
Revision: 1.0
Disclaimers and Restrictions
© 2015 COVELOZ®
Revision History
Version Date Author Description
September 1.0 Jane Biggs Initial Release. 2015
Table of Contents
Chapter 1: Overview ...... 8! 1.1 General Description ...... 8! 1.2 Features ...... 8! 1.3 Development Board Block Diagram ...... 9! 1.4 Handling the Development Board ...... 10! Chapter 2: Development Board Components ...... 10! 2.1 Development Board Overview ...... 10! 2.2 BACH SOM Connector ...... 11! 2.3 Configuration Elements ...... 12! 2.3.1 Jumper J2 ...... 12! 2.3.2 Jumper J22 ...... 12! 2.3.3 Jumper J27 ...... 12! 2.3.4 Jumpers J29, J30 and J31 ...... 12! 2.4 General User Input / Output ...... 13! 2.4.1 GPIO Extender ...... 13! 2.4.2 Push Buttons ...... 14! 2.4.3 LEDs ...... 14! 2.5 Audio Interfaces ...... 14! 2.5.1 Audio De-Jittering Clock ...... 14! 2.5.2 MADI ...... 14! 2.5.3 AES3/EBU ...... 15! 2.5.4 TDM and I2S ...... 16! 2.5.5 Analog ...... 17! 2.6 Synchronization ...... 17! 2.6.1 Word Clock ...... 17! 2.6.2 Pulse per Second (PPS) ...... 18! 2.6.3 Grandmaster Clock ...... 18! 2.7 GigE Interfaces ...... 19! 2.7.1 GigE HPS ...... 19! 2.7.2 GigE FPGA ...... 19! 2.8 HPS Communications Interfaces ...... 20!
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2.8.1 USB/UART ...... 20! 2.8.2 USB 2.0 OTG ...... 20! 2.8.3 SPI: Serial Peripheral Interface ...... 21! 2.8.4 I2C Interface ...... 21! 2.9 Real-Time Clock (RTC) ...... 21! 2.10 MicroSD FLASH ...... 22! 2.11 Power ...... 22! 2.11.1 Power Jack ...... 23! 2.11.2 Power Distribution ...... 23! Chapter 3: Additional Information ...... 23! 3.1 Board Revision History ...... 23! 3.1.1 How to Contact Coveloz ...... 23!
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Index of Figures
Figure 1-1: Development Board Block Diagram ...... 9!
Figure 2-1: Development Board Features ...... 10!
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Index of Tables
Table 2-1: Development Board Components ...... 11!
Table 2-2: Development Board GPIO Extender Connections ...... 13!
Table 2-3: Development Board-Specific Audio De-Jittering Clock ...... 14!
Table 2-4: Development Board-Specific MADI ...... 15!
Table 2-5: Development Board-Specific AES3/EBU ...... 15!
Table 2-6: Development Board-Specific TDM and I2S ...... 16!
Table 2-7: Development Board-Specific Analogue ...... 17!
Table 2-8: Development Board-Specific Word Clock ...... 18!
Table 2-9: Development Board-Specific PPS ...... 18!
Table 2-10: Development Board-Specific Grandmaster Clock ...... 18!
Table 2-11: Development Board-Specific GigE HPS ...... 19!
Table 2-12: Development Board-Specific GigE FPGA ...... 19!
Table 2-13: Development Board-Specific USB/UART ...... 20!
Table 2-14: Development Board-Specific USB 2.0 OTG ...... 21!
Table 2-15: Development Board-Specific Serial Peripheral Interface ...... 21!
Table 2-16: Development Board-Specific Real-Time Clock ...... 22!
Table 2-17: Development Board-Specific MicroSD Flash ...... 22!
Table 2-18: Development Board-Specific Power ...... 22!
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Chapter 1: !Overview
This document describes the hardware features of the Bach Development Board, including the detailed pin-out and component reference information required to design custom AVB or AES67 endpoints.
1.1!General Description
The BACH Development Board is part of the BACH Pro-Audio FPGA Development Kit which offers a robust design platform built around the Altera System-on-Chip (SoC) FPGA.
The Development Board serves as a platform for developing AVB and AES67 related applications running on the Coveloz BACH System on Module which features an Altera SoC FPGA.
1.2!Features
The features of the Development Board are:
•! Audio Processing o! Provide for DMA to host CPU for audio processing o! Use Ping-Pong Media (Audio) o! Low latency Implementation o! Support Up to 128 channels o! Each channel can be 48, 96, or 192 kHz o! Sample size is 32-bit •! AVB Audio Transport o! Support AVB 1722 AVTP o! Support up to 64 Streams o! Support Multiple Audio encapsulation (L16/L24/AM824) •! AES67 Audio Transport o! Support AES67-2013 using RTP o! Support up to 64 Streams o! Support Multiple Audio encapsulation (L16/L24/AM824) •! Media Clock Transport & Synchronization o! Support gPTP based synchronization (AVB) o! Support PTP Default Profile synchcronization (AES67) o! Support media clock transport (1722a)
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1.3!Development Board Block Diagram
Figure 1-1 shows a block diagram of the Development Board.
Figure 1-1: Development Board Block Diagram
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1.4!Handling the Development Board
Without proper anti-static handling, the Development Board can be damaged. Always use anti-static handling precautions when touching the Development Board.
Chapter 2: !Development Board Components
This chapter introduces the major components on the Bach Development Board.
A complete set of schematics, a physical layout database and fabrication files for the development board are available from Coveloz upon request.
Refer to the Bach Development Kit User Guide for information on powering up and configuring the Development Board.
2.1!Development Board Overview
This section provides an overview of the Development Board including an annotated board image and component descriptions.
Figure 2-1 shows the Development Board features.
Figure 2-1: Development Board Features
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Table 2-1 describes the components and lists their corresponding Development Board references.
Table 2-1: Development Board Components
Board Type Part Number Description Reference Featured Devices U1 5CSEBA5U23C8N Coveloz Bach SOM Board Configuration, Status and Setup Elements U9 USB to UART CP2102 USB/UART Bridge U8 USB2.0 OTG USB3300 USB Controller U7 Gigabit Ethernet KSZ9031RNX HPS Ethernet PHY U5, U6 Gigabit Ethernet KSZ9031RNX FPGA Ethernet PHY x2 (ENET0, ENET1) U2 GPIOs PCAL9535A GPIO extender Clock Circuitry Grand Master Clock In Level Shifter U20 SN74LVC1T45 configurable for 3.3V or 5V Audio Word Clock In/Out Level Shifter U19, U17 SN74LVC1T45 configurable for 3.3V or 5V PPS In/Out Level Shifter configurable for U18, U16 SN74LVC1T45 3.3V or 5V U13 DS1339U Real Time Clock with coin battery backup General User Input / Output EDGE 144-pin SODIMM connector compatible J1 1735251-2 connector with the Bach SOM Memory Devices J11 SD card DM3D-SF MicroSD Card Holder Audio Interfaces U23, U24, TDM and I2S Audio input and output U25, U26, 8x TDM or I2S SN74LVC8T245 control U27, U28 U21 AES3 CS8416 192kHz Digital Audio AES Receiver U22 AES3 CS8406 192kHz Digital Audio AES Transmitter 1/8” analogue U29 SSM2603 Audio Codec audio U14 MADI TX LMH0002 MADI 75-ohm Coax Cable Driver U15 MADI RX LMH0034 MADI 75-ohm Coax Cable Equalizer Logic U12 Audio PLL CS2000CP Audio Clock De jittering Power U3 EN6337QI Input power to 3.3V switching regulator U4 EY1501DI Input power to 5V linear regulator
2.2!BACH SOM Connector
The Development board contains a SODIMM compatible connector labeled J1 that is used to host the Bach SOM. The Bach SOM features a 144-pin edge connector compatible with the development board. Do not connect any other modules to this connector unless the pin out is guaranteed to be compatible.
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2.3!Configuration Elements
This section describes the various configuration jumpers on the Development Board
2.3.1!Jumper J2
Jumper 2 is used in the GPIO component of the Development Board to select where the board will be booted from.
BOOTSEL1 Option for J2, pins 29-30:
•! Short = boot from SD/MMC (default) •! Open = boot from QSPI flash
2.3.2!Jumper J22
Jumper 22 is used in the TDM Audio In and Out component of the Development Board to configure the input or output direction.
SN74LVC1T45 Direction Control:
•! Jumper removed = Output from this board •! Jumper installed = Input to this board (default)
2.3.3!Jumper J27
Jumper 27 is used in the Audio CODEC to configure a Line Out or Headphone Out Option:
•! Line Out: Short 4-2 and 3-1 (default) •! Headphone Out: Short 4-6 and 3-5
2.3.4!Jumpers J29, J30 and J31
Jumpers 29, 30, and 31 are used in the Audio Word Clock component if the Development Board for Word Clock input termination and to control the buffer voltage.
J29 controls word clock input termination:
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•! Jumper installed = 75 Ohm termination (default) •! Jumper removed = unterminated
J30 and J31 control the buffer voltage:
•! Short 2 to 1 = 3.3V level •! Short 2 to 3 = 5V level (default)
2.4!General User Input / Output
This section describes the user input and output features including push buttons, GPIO signals, LEDs and expansion headers.
2.4.1!GPIO Extender
The Development Board features a GPIO extender IC controlled by the HPS I2C interface. The IC has 16 GPIOs connected to LEDs, Pushbuttons, Jumpers and headers.
The GPIOs are organized into two groups of 8 signals, labeled PORT0[7:0] and PORT1[7:0].
The GPIO signals are connected to headers as described in Table 2-2
Table 2-2: Development Board GPIO Extender Connections
Board Schematic Name I/O Connection Reference Standard U2.P0_0 I2C_GPIO0 3.3V J2.8 U2.P0_1 I2C_GPIO1 3.3V J2.10 U2.P0_2 I2C_GPIO2 3.3V J2.12 U2.P0_3 I2C_GPIO3 3.3V J2.14 U2.P0_4 I2C_GPIO4 3.3V J2.16 U2.P0_5 I2C_GPIO5 3.3V J2.18 U2.P0_6 I2C_GPIO6 3.3V J2.20 U2.P0_7 I2C_GPIO7 3.3V J2.22 U2.P1_0 I2C_GPIO8 3.3V J2.24 U2.P1_1 I2C_GPIO9 3.3V J2.26 U2.P1_2 I2C_GPIO10 3.3V J2.28 U2.P1_3 I2C_GPIO11 3.3V J3.3 U2.P1_4 I2C_GPIO12 3.3V J3.1 and LED D2 U2.P1_5 I2C_GPIO13 3.3V J3.2 and LED D1 U2.P1_6 I2C_GPIO14 3.3V J3.4 and SW3 U2.P1_7 I2C_GPIO15 3.3V J3.6 and SW2
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2.4.2!Push Buttons
The U2 GPIO extender has PORT1[6] and PORT1[7] connected to pushbutton SW3 and SW2. Pushing the buttons connects the GPIOs to GND.
2.4.3!LEDs
The GPIO extender has PORT1[4] and PORT1[5] connected to LEDs D2 and D1. Setting these as outputs and driving them high turns on the LEDs.
2.5!Audio Interfaces
2.5.1!Audio De-Jittering Clock
The CS2000 audio de-jittering clock and PLL is connected to the HPS_I2C bus at address 7’b1001110.
Table 2-3 lists the Development Board specific Audio De-Jittering Clock references, names and their functional descriptions.
Table 2-3: Development Board-Specific Audio De-Jittering Clock
Board Schematic Name I/O Description Reference Standard A Cirrus Logic CS2000 provides an audio clock de- jittering resource for the FPGA and features a 24.576MHz reference clock. −! CLK_OUT: PLL output, connect to CS2000_CLK_OUT −! AUX_OUT: Buffered clock output, connect to CS2000_AUX_OUT U12 Audio PLL 3.3V −! CLK_IN: Frequency reference clock input, connect to CS2000_CLK_IN −! REF_CLK: Connected to 24.576MHz oscillator XTO: NC −! AD0/CS#: Pull-down −! SCL/CCLK: I2C0_SCL −! SDA/CDIN: I2C0_SDA
2.5.2!MADI
A MADI TX and RX interface is provided via BNC connectors. The MADI external interface is connected to the FPGA using LVDS differential pairs via equalizer and driver ICs. The FPGA performs all clock and data recovery functions.
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MADI TX:
•! Differential pair from the FPGA •! LMH0002 driver IC •! 75 Ohm BNC
MADI RX:
•! 75 Ohm BNC •! LMH0034 equalizer IC •! Differential pair to the FPGA
Table 2-4 lists the Development Board specific MADI references, names and their functional descriptions.
Table 2-4: Development Board-Specific MADI
Board Schematic Name I/O Description Reference Standard MADI receiver circuit – SDI Equalizer U14 MADI Tx Output 3.3V FPGA I/O - Differential Input and output, - 2 pins each J14 MADI Tx Output 75 Ohm U15 MADI Rx Input 3.3V MADI Driver circuit – SDI Driver J13 MADI Rx Input 75 Ohm BNC
2.5.3!AES3/EBU
The Development Board features an AES3 input and output interface which include audio transformers and XLR connectors.
The AES3 input decoding is provided by the CS8416 which is connected to the HPS_I2C1 bus at address 7’b0010110.
The AES3 output encoding is provided by the CS8406 which is connected to the HPS_I2C1 bus at address 7’b0010001.
Table 2-5 lists the Development Board specific AES3/EBU references, names and their functional descriptions.
Table 2-5: Development Board-Specific AES3/EBU
Board Schematic Name I/O Description Reference Standard
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Board Schematic Name I/O Description Reference Standard AES3 XLR Digital Input −! ADC IC – CS8416 U21 AES3 Receiver 3.3V −! 3.3V Power and IO −! SPI or I2C Isolation T1 AES 192kHz Audio Transformer Transformer J20 AES3 Receiver XLR Female Connector AES3 XLR Digital Output (male pins with female shell) U22 AES3 Transmitter 3.3V −! DAC IC - CS8406 −! 3.3V Power and IO −! SPI or I2C Isolation T2 AES 192kHz Audio Transformer Transformer J21 AES3 Transmitter XLR Male Connector
2.5.4!TDM and I2S
Table 2-6 lists the Development Board specific TDM and I2S references, names and their functional descriptions.
Table 2-6: Development Board-Specific TDM and I2S
Board Pin Board Reference FPGA Signal Reference 1 Ground GND 2 FSYNC Input/Output TDM_FSYNC 3 SCLK Input/Output TDM_SCLK 4 TDM/I2S Audio In TDM_I2S_IN0 5 TDM/I2S Audio In TDM_I2S_IN1 6 TDM/I2S Audio In TDM_I2S_IN2 J23 7 TDM/I2S Audio In TDM_I2S_IN3 8 TDM/I2S Audio In TDM_I2S_IN4 9 TDM/I2S Audio In TDM_I2S_IN5 10 TDM/I2S Audio In TDM_I2S_IN6 11 TDM/I2S Audio In TDM_I2S_IN7 12 Ground GND 1 Ground GND 2 LRCK Input/Output I2S_LRCK 3 SCLK Input/Output I2S_SCLK 4 TDM/I2S Audio Out TDM_I2S_OUT0 5 TDM/I2S Audio Out TDM_I2S_OUT1 6 TDM/I2S Audio Out TDM_I2S_OUT2 J24 7 TDM/I2S Audio Out TDM_I2S_OUT3 8 TDM/I2S Audio Out TDM_I2S_OUT4 9 TDM/I2S Audio Out TDM_I2S_OUT5 10 TDM/I2S Audio Out TDM_I2S_OUT6 11 TDM/I2S Audio Out TDM_I2S_OUT7 12 Ground GND
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2.5.5!Analog
The Development board contains an audio codec that provides ADC and DAC functions for external analog audio connections. The codec uses an SSM2603 which is connected to the HPS_I2C1 at address 7’b0011010.
Table 2-7 lists the Development Board specific Analogue references, names and their functional descriptions.
Table 2-7: Development Board-Specific Analogue
Board Schematic Name I/O Description Reference Standard Analog DevicesSSM2603 Codec IC −! I2C Control - 2 pins −! Audio (I2S) 5 pin interface (Data In, out, WCLK, BCLK, MCLK) 12.288MHz or 24.576MHz clock reference from U29 Audio Codec 3.3V Audio PLL or FPGA 1/8" Jacks x 3 (Line In, Line Out, Mic) −! 3.5mm audio jack (1/8") −! Green: Line Out −! Blue: Mic −! Pink: Line In See Section 2.3.3 for the configuration of this J25 6-pin Header jumper: Line Out or Headphone Out. 3.5mm (1/8”) J26 Analog Audio Line In Connector Blue 3.5mm (1/8”) J27 Analog Headphone Output Connector Green 3.5mm (1/8”) J28 Analog Audio Line Out Connector Pink
2.6!Synchronization
The section describes the synchronization components of the Development Board.
2.6.1!Word Clock
Table 2-8 lists the Development Board specific Word Clock references, names and their functional descriptions.
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Table 2-8: Development Board-Specific Word Clock
Board Schematic Name I/O Description Reference Standard Uses BNC for input and another for output Audio Word Clock The signal is typically "LVTTL level" 3.3 volt p-p and U17, U19 3.3V Input and Output is carried on 75 Ohm coaxial cable with BNC connectors
2.6.2!Pulse per Second (PPS)
Table 2-9 lists the Development Board specific PPS references, names and their functional descriptions.
Table 2-9: Development Board-Specific PPS
Board Schematic Name I/O Description Reference Standard PPS Input and U16 3.3V Output PPS Input and J15 50 Ohm BNC Output PPS Input and PPS Out U18 3.3V Output Regular FPGA output drives PPS Out PPS Input and J7 50 Ohm BNC Output
2.6.3!Grandmaster Clock
Table 2-10 lists the Development Board specific Grandmaster Clock references, names and their functional descriptions.
Table 2-10: Development Board-Specific Grandmaster Clock
Board Schematic Name I/O Description Reference Standard
Grandmaster U20 3.3V Synch Input
Grandmaster J19 50 Ohm BNC Synch Input
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2.7!GigE Interfaces
Ethernet MAC uses an off-the-shelf MAC. The MAC is generated without FIFOs to reduce jitter. The FIFOs will be implemented in packet engines.
The following assumptions are made:
•! Full Duplex only •! 100 &1000 Mb/s (no support for10 Mb/s) •! No Flow control •! Statistics support
2.7.1!GigE HPS
Table 2-11 lists the Development Board specific GigE HPS, names and their functional descriptions.
Table 2-11: Development Board-Specific GigE HPS
Board Schematic Name I/O Description Reference Standard
U7 HPS Ethernet PHY 3.3V
J7 HPS Ethernet RJ45
2.7.2!GigE FPGA
Table 2-12 lists the Development Board specific GigE FPGA, names and their functional descriptions.
Table 2-12: Development Board-Specific GigE FPGA
Board Schematic Name I/O Description Reference Standard
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Board Schematic Name I/O Description Reference Standard Micrel KSZ9031 −! • 3.3/2.5 and 1.2V supplies −! • 3.3/2.5/1.8 IO voltage FPGA Ethernet −! • 25MHz reference oscillator +/- 50ppm U5 3.3V PHY 0 −! • 15 FPGA Pins Oscillator: TSM32-H50CQ25ST-25.000M-TR Ethernet jack with integrated magnetics −! Wurth 7499011121A FPGA Ethernet J5 RJ45 Micrel KSZ9031 −! • 3.3/2.5 and 1.2V supplies −! • 3.3/2.5/1.8 IO voltage FPGA Ethernet −! • 25MHz reference oscillator +/- 50ppm U6 3.3V PHY 1 −! • 15 FPGA Pins Oscillator: TSM32-H50CQ25ST-25.000M-TR Ethernet jack with integrated magnetics −! Wurth 7499011121A FPGA Ethernet J6 RJ45
2.8!HPS Communications Interfaces
This section describes the HPS communications interfaces.
2.8.1!USB/UART
Table 2-13 lists the Development Board specific USB/UART references, names and their functional descriptions.
Table 2-13: Development Board-Specific USB/UART
Board Schematic Name I/O Description Reference Standard FTDI FTFTDI FT230X U9 USB/UART Bridge 3.3V 1.8V to 3.3V IO operation 4 pins (TX, RX, CTS, RTS) U11 USB/UART Bridge J9 USB/UART Bridge USB Mini-B
2.8.2!USB 2.0 OTG
Table 2-14 lists the Development Board specific USB 2.0 OTG references, names and their functional descriptions.
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Table 2-14: Development Board-Specific USB 2.0 OTG
Board Schematic Name I/O Description Reference Standard USB OTG 2.0 host chip, PHY ULPI compatible USB3300 from Microchip U10 USB Controller 3.3V −! 12 bit interface to HPS 24MHz external crystal 3.3V IO operation U8 USB Controller 5V J10 USB Controller Mini-AB
2.8.3!SPI: Serial Peripheral Interface
Table 2-15 lists the Development Board specific Serial Peripheral Interface references, names and their functional descriptions.
Table 2-15: Development Board-Specific Serial Peripheral Interface
Board Schematic Name I/O Description Reference Standard SODIMM 144-pin Edge connector compatible with standards U1 3.3V Connector SODIMM connector
2.8.4!I2C Interface
Maxim DS1339
•! 357 Coin battery at 1.55V •! Provides 120,000 backup hours (14 years) •! I2C interface - 2 pins •! 3.3V IO
2.9!Real-Time Clock (RTC)
The Development Board contains a real-time clock with battery backup that is connected to the HPS_I2C bus at address 7’b1101000.
Table 2-16 lists the Development Board specific Real-Time Clock references, names and their functional descriptions.
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Table 2-16: Development Board-Specific Real-Time Clock
Board Schematic Name I/O Description Reference Standard U13 Real Time Clock 3.3V Real-time clock that provides battery backup J12 Battery Backup Real-time clock battery backup lithium coin cell
2.10!MicroSD FLASH
The microSD card provides low cost storage for a connected SOM. It can be used for OS images, FPGA images, data capture and media storage.
Table 2-17 lists the Development Board specific MicroSD Flash references, names and their functional descriptions.
Table 2-17: Development Board-Specific MicroSD Flash
Board Schematic Name I/O Description Reference Standard J11 SD/MMC Card 3.3V 6 pins to HPS
2.11!Power
You must power up the Development Board from a 6V power supply capable of at least 1A of current (6W).
Table 2-18 lists the Development Board specific Power references, names and their functional descriptions.
Table 2-18: Development Board-Specific Power
Board Schematic Name Voltage Description Reference Output U3 Power 3.3V 3.3V DC-DC converter U4 Power 5V 5V linear regulator Reverse polarity protection Supply = 6 Volts, Min 1 Amps J4 Power Barrel = NEG Pin = POS
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2.11.1!Power Jack
The power connector is located at J4. It has a 2.1mm ID and 5.5mm OD with positive center pin.
2.11.2!Power Distribution
The Development Board has power supply circuitry to generate the voltages needed by all onboard functions. The 6V input power is also passed directly to the Bach SOM.
A 3.3V switching supply generates most of the power required by on-board ICs. A 5V linear regulator generates the supplies needed for some of the USB functions.
Chapter 3: !Additional Information
This section provides additional information about the Bach Development Board, this document and Coveloz.
3.1!Board Revision History
The following table lists the versions of all releases of the Bach Development Board.
Release Date Version Description June 2015 Initial release for ??
3.1.1!How to Contact Coveloz
For any questions or support issues contacts are found at Coveloz’s website, http://coveloz.com/contact-us/ .
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