! ! Development!Board! Reference Manual Date: September 3, 2015 Revision: 1.0 Disclaimers and Restrictions © 2015 COVELOZ® Revision History Version Date Author Description September 1.0 Jane Biggs Initial Release. 2015 Table of Contents Chapter 1: Overview ......................................................................................................... 8! 1.1 General Description .............................................................................................................. 8! 1.2 Features ..................................................................................................................................... 8! 1.3 Development Board Block Diagram .............................................................................. 9! 1.4 Handling the Development Board ............................................................................... 10! Chapter 2: Development Board Components ............................................................. 10! 2.1 Development Board Overview ....................................................................................... 10! 2.2 BACH SOM Connector ..................................................................................................... 11! 2.3 Configuration Elements ................................................................................................... 12! 2.3.1 Jumper J2 .................................................................................................................... 12! 2.3.2 Jumper J22 ................................................................................................................. 12! 2.3.3 Jumper J27 ................................................................................................................. 12! 2.3.4 Jumpers J29, J30 and J31 ................................................................................... 12! 2.4 General User Input / Output ......................................................................................... 13! 2.4.1 GPIO Extender ............................................................................................................ 13! 2.4.2 Push Buttons .............................................................................................................. 14! 2.4.3 LEDs ............................................................................................................................... 14! 2.5 Audio Interfaces .................................................................................................................. 14! 2.5.1 Audio De-Jittering Clock ........................................................................................ 14! 2.5.2 MADI ............................................................................................................................... 14! 2.5.3 AES3/EBU .................................................................................................................... 15! 2.5.4 TDM and I2S ............................................................................................................... 16! 2.5.5 Analog ............................................................................................................................ 17! 2.6 Synchronization .................................................................................................................. 17! 2.6.1 Word Clock .................................................................................................................. 17! 2.6.2 Pulse per Second (PPS) ......................................................................................... 18! 2.6.3 Grandmaster Clock .................................................................................................. 18! 2.7 GigE Interfaces .................................................................................................................... 19! 2.7.1 GigE HPS ...................................................................................................................... 19! 2.7.2 GigE FPGA .................................................................................................................... 19! 2.8 HPS Communications Interfaces ................................................................................. 20! Draft: June 2015 Page 4 of 23 2.8.1 USB/UART ................................................................................................................... 20! 2.8.2 USB 2.0 OTG ............................................................................................................... 20! 2.8.3 SPI: Serial Peripheral Interface ........................................................................... 21! 2.8.4 I2C Interface ................................................................................................................ 21! 2.9 Real-Time Clock (RTC) ..................................................................................................... 21! 2.10 MicroSD FLASH ................................................................................................................ 22! 2.11 Power .................................................................................................................................... 22! 2.11.1 Power Jack ................................................................................................................ 23! 2.11.2 Power Distribution ................................................................................................. 23! Chapter 3: Additional Information ............................................................................... 23! 3.1 Board Revision History .................................................................................................... 23! 3.1.1 How to Contact Coveloz ......................................................................................... 23! Draft: June 2015 Page 5 of 23 Index of Figures Figure 1-1: Development Board Block Diagram ......................................................................... 9! Figure 2-1: Development Board Features ................................................................................... 10! Draft: June 2015 Page 6 of 23 Index of Tables Table 2-1: Development Board Components ............................................................................ 11! Table 2-2: Development Board GPIO Extender Connections ............................................. 13! Table 2-3: Development Board-Specific Audio De-Jittering Clock ................................... 14! Table 2-4: Development Board-Specific MADI ......................................................................... 15! Table 2-5: Development Board-Specific AES3/EBU .............................................................. 15! Table 2-6: Development Board-Specific TDM and I2S ......................................................... 16! Table 2-7: Development Board-Specific Analogue ................................................................. 17! Table 2-8: Development Board-Specific Word Clock ............................................................. 18! Table 2-9: Development Board-Specific PPS ............................................................................ 18! Table 2-10: Development Board-Specific Grandmaster Clock .......................................... 18! Table 2-11: Development Board-Specific GigE HPS .............................................................. 19! Table 2-12: Development Board-Specific GigE FPGA ........................................................... 19! Table 2-13: Development Board-Specific USB/UART ........................................................... 20! Table 2-14: Development Board-Specific USB 2.0 OTG ...................................................... 21! Table 2-15: Development Board-Specific Serial Peripheral Interface ............................ 21! Table 2-16: Development Board-Specific Real-Time Clock ................................................ 22! Table 2-17: Development Board-Specific MicroSD Flash .................................................... 22! Table 2-18: Development Board-Specific Power ..................................................................... 22! Draft: June 2015 Page 7 of 23 Development Board Reference Manual ! Chapter 1: Overview Chapter 1: !Overview This document describes the hardware features of the Bach Development Board, including the detailed pin-out and component reference information required to design custom AVB or AES67 endpoints. 1.1!General Description The BACH Development Board is part of the BACH Pro-Audio FPGA Development Kit which offers a robust design platform built around the Altera System-on-Chip (SoC) FPGA. The Development Board serves as a platform for developing AVB and AES67 related applications running on the Coveloz BACH System on Module which features an Altera SoC FPGA. 1.2!Features The features of the Development Board are: •! Audio Processing o! Provide for DMA to host CPU for audio processing o! Use Ping-Pong Media (Audio) o! Low latency Implementation o! Support Up to 128 channels o! Each channel can be 48, 96, or 192 kHz o! Sample size is 32-bit •! AVB Audio Transport o! Support AVB 1722 AVTP o! Support up to 64 Streams o! Support Multiple Audio encapsulation (L16/L24/AM824) •! AES67 Audio Transport o! Support AES67-2013 using RTP o! Support up to 64 Streams o! Support Multiple Audio encapsulation (L16/L24/AM824) •! Media Clock Transport & Synchronization o! Support gPTP based synchronization (AVB)