System Programmer Reference (Cray SV1™ Series)
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® System Programmer Reference (Cray SV1™ Series) 108-0245-003 Cray Proprietary (c) Cray Inc. All Rights Reserved. Unpublished Proprietary Information. This unpublished work is protected by trade secret, copyright, and other laws. Except as permitted by contract or express written permission of Cray Inc., no part of this work or its content may be used, reproduced, or disclosed in any form. U.S. GOVERNMENT RESTRICTED RIGHTS NOTICE: The Computer Software is delivered as "Commercial Computer Software" as defined in DFARS 48 CFR 252.227-7014. All Computer Software and Computer Software Documentation acquired by or for the U.S. Government is provided with Restricted Rights. Use, duplication or disclosure by the U.S. Government is subject to the restrictions described in FAR 48 CFR 52.227-14 or DFARS 48 CFR 252.227-7014, as applicable. Technical Data acquired by or for the U.S. Government, if any, is provided with Limited Rights. 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Box 6000 Chippewa Falls, WI 54729-0080 USA E-mail: [email protected] Fax: +1 715-726-4991 System Programmer Reference System Programmer Reference 108-0245-003 Cray SV1 Series Last Modified: February 2002 RecordofRevision .............................................. 10 CraySV1SeriesSystemOverview.................................. 11 CraySV1eProcessor.......................................... 12 CraySV1ex-1andCraySV1ex-1ASystems ....................... 12 MainframeOverview............................................. 13 SIOOverview .................................................. 15 GigaRingOverview........................................... 15 VME-basedI/OSubsystemOverview................................ 17 NetworkInterfaces............................................... 18 MaintenancePlatform ............................................ 19 CentralMemory................................................. 19 MemoryInstructions .......................................... 20 LogicalOrganization.......................................... 22 PortUtilization............................................... 24 ConflictResolution ........................................... 27 GuaranteeingMemoryAccessOrder ............................. 30 CalculatingAbsoluteMemoryAddress............................ 32 AddressRangeChecking....................................... 33 ErrorDetectionandCorrection.................................. 34 CentralMemoryPerformanceSummary........................... 37 VMEI/OSection................................................ 39 Y1ChannelPairs............................................. 40 ErrorHandling............................................... 46 HighPerformanceParallelInterface(HIPPI) ....................... 47 GigaRingI/OSection............................................. 52 MPN-1FunctionalOverview.................................... 53 IPN-1FunctionalOverview..................................... 54 108-0245-003 Cray Proprietary 1 System Programmer Reference FCN-1andFCN-2FunctionalOverview........................... 56 HPNFunctionalOverview...................................... 57 BMN-1FunctionalOverview ................................... 58 ESN-1FunctionalOverview.................................... 59 FOXOverview............................................... 60 ErrorReportingandHandling................................... 61 InterprocessorCommunication ..................................... 62 Clusters .................................................... 62 SharedRegisters ............................................. 63 Semaphore Registers .......................................... 63 TestandSetControl........................................... 66 Deadlock ................................................... 66 InterprocessorInterrupts ....................................... 67 Real-time Clock ................................................. 68 ExchangeMechanism ............................................ 70 ExchangePackage............................................ 70 ExchangeSequence........................................... 79 ExchangePackageManagement................................. 82 InstructionFetchSequence ........................................ 83 InstructionFetchHardware..................................... 83 InstructionIssue................................................. 87 InstructionIssueHardware ..................................... 87 ReservationsandHoldIssueConditions........................... 96 ProgrammableClock............................................. 97 InterruptIntervalRegister...................................... 98 Operation................................................... 98 StatusRegister.................................................. 98 PerformanceMonitor............................................. 99 SelectingandReadingPerformanceEvents ........................ 102 Testing Performance Counters . .................................. 104 CacheMemory.................................................. 104 DetailedOperationofCacheMemory............................. 106 2 Cray Proprietary 108-0245-003 System Programmer Reference CPUComputation ............................................... 109 OperatingRegisters.............................................. 110 Address(A)Registers ......................................... 110 IntermediateScalar(T)Registers ................................ 124 Vector(V)Registers........................................... 125 VectorInstructionIssueTiming.................................. 132 Vector Instruction Issue Conflict Timing ........................... 133 VectorControlRegisters ....................................... 136 VectorLengthRegister ........................................ 137 VectorMaskRegister.......................................... 137 UserModeVectorInstructionTiming............................. 137 BitMatrixMultiply(BMM)Register ............................. 141 FunctionalUnits................................................. 141 AddressFunctionalUnits....................................... 142 ScalarFunctionalUnits........................................ 143 VectorFunctionalUnits........................................ 144 Floating-pointFunctionalUnits.................................. 147 Bit-matrixMultiplyFunctionalUnit.............................. 149 FunctionalUnitOperations........................................ 155 LogicalOperations............................................ 156 IntegerArithmetic ............................................ 157 24-bit Integer Multiplication . .................................. 157 MultiplicationofOperandsGreaterthan24Bits..................... 158 Floating-pointArithmetic ...................................... 159 ParallelProcessingFeatures ....................................... 172 PipeliningandSegmentation....................................... 173 FunctionalUnitIndependence...................................... 174 Multiprocessing and Multitasking . .................................. 175 AutotaskingFeature.............................................. 176 EnablingandDisablingtheMaintenanceMode ........................ 176 UsingMaintenanceMode ......................................... 177 CPUInstructions ................................................ 179 108-0245-003 Cray Proprietary 3 System Programmer Reference Quick-referenceTableofCPUInstructions............................ 180 Notational Conventions ........................................... 188 InstructionFormats .............................................. 188 1-parcel Instruction Format with Discrete j and k Fields............... 189 1-parcel Instruction Format with Combined j and k Fields............. 189 2-parcel Instruction Format with Combined i, j, k,andm Fields ........ 190 3-parcel Instruction Format with Combined m and n Fields............ 190 SpecialRegisterValues..........................................